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afdfe8f0 | 1 | /**@file\r |
2 | \r | |
3 | Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r | |
fbcd5cea | 4 | Copyright (c) 2011 Hewlett Packard Corporation. All rights reserved.<BR>\r |
6f050ad6 | 5 | Copyright (c) 2011-2013, ARM Limited. All rights reserved.<BR>\r |
44788bae | 6 | \r |
4059386c | 7 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
afdfe8f0 | 8 | \r |
9 | Module Name:\r | |
10 | \r | |
11 | MemoryInit.c\r | |
3402aac7 | 12 | \r |
afdfe8f0 | 13 | Abstract:\r |
14 | \r | |
15 | PEIM to provide fake memory init\r | |
16 | \r | |
17 | **/\r | |
18 | \r | |
afdfe8f0 | 19 | //\r |
20 | // The package level header files this module uses\r | |
21 | //\r | |
22 | #include <PiPei.h>\r | |
23 | //\r | |
ff5fef14 | 24 | // The protocols, PPI and GUID definitions for this module\r |
afdfe8f0 | 25 | //\r |
44788bae | 26 | #include <Ppi/ArmMpCoreInfo.h>\r |
afdfe8f0 | 27 | \r |
28 | //\r | |
29 | // The Library classes this module consumes\r | |
30 | //\r | |
31 | #include <Library/DebugLib.h>\r | |
32 | #include <Library/PeimEntryPoint.h>\r | |
44788bae | 33 | #include <Library/PeiServicesLib.h>\r |
afdfe8f0 | 34 | #include <Library/PcdLib.h>\r |
35 | #include <Library/HobLib.h>\r | |
36 | #include <Library/ArmLib.h>\r | |
37 | \r | |
afdfe8f0 | 38 | /*++\r |
39 | \r | |
40 | Routine Description:\r | |
41 | \r | |
afdfe8f0 | 42 | Arguments:\r |
43 | \r | |
44 | FileHandle - Handle of the file being invoked.\r | |
45 | PeiServices - Describes the list of possible PEI Services.\r | |
3402aac7 | 46 | \r |
afdfe8f0 | 47 | Returns:\r |
48 | \r | |
49 | Status - EFI_SUCCESS if the boot mode could be set\r | |
50 | \r | |
51 | --*/\r | |
44788bae | 52 | EFI_STATUS\r |
53 | EFIAPI\r | |
54 | InitializeCpuPeim (\r | |
55 | IN EFI_PEI_FILE_HANDLE FileHandle,\r | |
56 | IN CONST EFI_PEI_SERVICES **PeiServices\r | |
57 | )\r | |
afdfe8f0 | 58 | {\r |
429309e0 MK |
59 | EFI_STATUS Status;\r |
60 | ARM_MP_CORE_INFO_PPI *ArmMpCoreInfoPpi;\r | |
61 | UINTN ArmCoreCount;\r | |
62 | ARM_CORE_INFO *ArmCoreInfoTable;\r | |
44788bae | 63 | \r |
afdfe8f0 | 64 | // Enable program flow prediction, if supported.\r |
65 | ArmEnableBranchPrediction ();\r | |
66 | \r | |
44788bae | 67 | // Publish the CPU memory and io spaces sizes\r |
a3b65371 | 68 | BuildCpuHob (ArmGetPhysicalAddressBits (), PcdGet8 (PcdPrePiCpuIoSize));\r |
149daa61 | 69 | \r |
44788bae | 70 | // Only MP Core platform need to produce gArmMpCoreInfoPpiGuid\r |
429309e0 MK |
71 | Status = PeiServicesLocatePpi (&gArmMpCoreInfoPpiGuid, 0, NULL, (VOID **)&ArmMpCoreInfoPpi);\r |
72 | if (!EFI_ERROR (Status)) {\r | |
44788bae | 73 | // Build the MP Core Info Table\r |
74 | ArmCoreCount = 0;\r | |
429309e0 MK |
75 | Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);\r |
76 | if (!EFI_ERROR (Status) && (ArmCoreCount > 0)) {\r | |
44788bae | 77 | // Build MPCore Info HOB\r |
78 | BuildGuidDataHob (&gArmMpCoreInfoGuid, ArmCoreInfoTable, sizeof (ARM_CORE_INFO) * ArmCoreCount);\r | |
79 | }\r | |
80 | }\r | |
afdfe8f0 | 81 | \r |
82 | return EFI_SUCCESS;\r | |
83 | }\r |