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afdfe8f0 | 1 | /**@file\r |
2 | \r | |
3 | Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r | |
fbcd5cea | 4 | Copyright (c) 2011 Hewlett Packard Corporation. All rights reserved.<BR>\r |
6f050ad6 | 5 | Copyright (c) 2011-2013, ARM Limited. All rights reserved.<BR>\r |
44788bae | 6 | \r |
afdfe8f0 | 7 | This program and the accompanying materials \r |
8 | are licensed and made available under the terms and conditions of the BSD License \r | |
9 | which accompanies this distribution. The full text of the license may be found at \r | |
10 | http://opensource.org/licenses/bsd-license.php \r | |
11 | \r | |
12 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
13 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
14 | \r | |
15 | Module Name:\r | |
16 | \r | |
17 | MemoryInit.c\r | |
18 | \r | |
19 | Abstract:\r | |
20 | \r | |
21 | PEIM to provide fake memory init\r | |
22 | \r | |
23 | **/\r | |
24 | \r | |
25 | \r | |
26 | \r | |
27 | //\r | |
28 | // The package level header files this module uses\r | |
29 | //\r | |
30 | #include <PiPei.h>\r | |
31 | //\r | |
32 | // The protocols, PPI and GUID defintions for this module\r | |
33 | //\r | |
44788bae | 34 | #include <Ppi/ArmMpCoreInfo.h>\r |
afdfe8f0 | 35 | \r |
36 | //\r | |
37 | // The Library classes this module consumes\r | |
38 | //\r | |
39 | #include <Library/DebugLib.h>\r | |
40 | #include <Library/PeimEntryPoint.h>\r | |
44788bae | 41 | #include <Library/PeiServicesLib.h>\r |
afdfe8f0 | 42 | #include <Library/PcdLib.h>\r |
43 | #include <Library/HobLib.h>\r | |
44 | #include <Library/ArmLib.h>\r | |
45 | \r | |
46 | //\r | |
47 | // Module globals\r | |
48 | //\r | |
49 | \r | |
50 | #define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK\r | |
51 | #define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED\r | |
52 | \r | |
fbcd5cea | 53 | EFI_STATUS\r |
438311a3 | 54 | FindMainMemory (\r |
fbcd5cea | 55 | OUT UINT32 *PhysicalBase,\r |
56 | OUT UINT32 *Length\r | |
57 | )\r | |
58 | {\r | |
59 | EFI_PEI_HOB_POINTERS NextHob;\r | |
60 | \r | |
44788bae | 61 | // Look at the resource descriptor hobs, choose the first system memory one\r |
fbcd5cea | 62 | NextHob.Raw = GetHobList ();\r |
63 | while ((NextHob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, NextHob.Raw)) != NULL) {\r | |
64 | if(NextHob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY)\r | |
65 | {\r | |
66 | *PhysicalBase = (UINT32)NextHob.ResourceDescriptor->PhysicalStart;\r | |
67 | *Length = (UINT32)NextHob.ResourceDescriptor->ResourceLength;\r | |
68 | return EFI_SUCCESS;\r | |
69 | }\r | |
70 | \r | |
71 | NextHob.Raw = GET_NEXT_HOB (NextHob);\r | |
72 | }\r | |
73 | \r | |
74 | return EFI_NOT_FOUND;\r | |
75 | }\r | |
76 | \r | |
afdfe8f0 | 77 | VOID\r |
438311a3 | 78 | ConfigureMmu (\r |
79 | VOID\r | |
80 | )\r | |
afdfe8f0 | 81 | {\r |
44788bae | 82 | EFI_STATUS Status;\r |
fbcd5cea | 83 | UINTN Idx;\r |
afdfe8f0 | 84 | UINT32 CacheAttributes;\r |
fbcd5cea | 85 | UINT32 SystemMemoryBase;\r |
86 | UINT32 SystemMemoryLength;\r | |
87 | UINT32 SystemMemoryLastAddress;\r | |
88 | ARM_MEMORY_REGION_DESCRIPTOR MemoryTable[4];\r | |
afdfe8f0 | 89 | VOID *TranslationTableBase;\r |
90 | UINTN TranslationTableSize;\r | |
91 | \r | |
92 | if (FeaturePcdGet(PcdCacheEnable) == TRUE) {\r | |
93 | CacheAttributes = DDR_ATTRIBUTES_CACHED;\r | |
94 | } else {\r | |
95 | CacheAttributes = DDR_ATTRIBUTES_UNCACHED;\r | |
96 | }\r | |
97 | \r | |
fbcd5cea | 98 | Idx = 0;\r |
99 | \r | |
100 | // Main Memory\r | |
101 | Status = FindMainMemory (&SystemMemoryBase, &SystemMemoryLength);\r | |
102 | ASSERT_EFI_ERROR (Status);\r | |
103 | \r | |
104 | SystemMemoryLastAddress = SystemMemoryBase + (SystemMemoryLength-1);\r | |
105 | \r | |
44788bae | 106 | // If system memory does not begin at 0\r |
fbcd5cea | 107 | if(SystemMemoryBase > 0) {\r |
108 | MemoryTable[Idx].PhysicalBase = 0;\r | |
109 | MemoryTable[Idx].VirtualBase = 0;\r | |
110 | MemoryTable[Idx].Length = SystemMemoryBase;\r | |
111 | MemoryTable[Idx].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r | |
112 | Idx++;\r | |
113 | }\r | |
afdfe8f0 | 114 | \r |
fbcd5cea | 115 | MemoryTable[Idx].PhysicalBase = SystemMemoryBase;\r |
116 | MemoryTable[Idx].VirtualBase = SystemMemoryBase;\r | |
117 | MemoryTable[Idx].Length = SystemMemoryLength;\r | |
118 | MemoryTable[Idx].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;\r | |
119 | Idx++;\r | |
120 | \r | |
44788bae | 121 | // If system memory does not go to the last address (0xFFFFFFFF)\r |
fbcd5cea | 122 | if( SystemMemoryLastAddress < MAX_ADDRESS ) {\r |
123 | MemoryTable[Idx].PhysicalBase = SystemMemoryLastAddress + 1;\r | |
124 | MemoryTable[Idx].VirtualBase = MemoryTable[Idx].PhysicalBase;\r | |
125 | MemoryTable[Idx].Length = MAX_ADDRESS - MemoryTable[Idx].PhysicalBase + 1;\r | |
126 | MemoryTable[Idx].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r | |
127 | Idx++;\r | |
128 | }\r | |
afdfe8f0 | 129 | \r |
130 | // End of Table\r | |
fbcd5cea | 131 | MemoryTable[Idx].PhysicalBase = 0;\r |
132 | MemoryTable[Idx].VirtualBase = 0;\r | |
133 | MemoryTable[Idx].Length = 0;\r | |
134 | MemoryTable[Idx].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;\r | |
135 | \r | |
136 | DEBUG ((EFI_D_INFO, "Enabling MMU, setting 0x%08x + %d MB to %a\n",\r | |
137 | SystemMemoryBase, SystemMemoryLength/1024/1024,\r | |
138 | (CacheAttributes == DDR_ATTRIBUTES_CACHED) ? "cacheable" : "uncacheable"));\r | |
139 | \r | |
6f050ad6 OM |
140 | Status = ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize);\r |
141 | if (EFI_ERROR (Status)) {\r | |
142 | DEBUG ((EFI_D_ERROR, "Error: Failed to enable MMU (error code: %r)\n", Status));\r | |
143 | }\r | |
afdfe8f0 | 144 | \r |
145 | BuildMemoryAllocationHob((EFI_PHYSICAL_ADDRESS)(UINTN)TranslationTableBase, TranslationTableSize, EfiBootServicesData);\r | |
146 | }\r | |
147 | \r | |
afdfe8f0 | 148 | /*++\r |
149 | \r | |
150 | Routine Description:\r | |
151 | \r | |
152 | \r | |
153 | \r | |
154 | Arguments:\r | |
155 | \r | |
156 | FileHandle - Handle of the file being invoked.\r | |
157 | PeiServices - Describes the list of possible PEI Services.\r | |
158 | \r | |
159 | Returns:\r | |
160 | \r | |
161 | Status - EFI_SUCCESS if the boot mode could be set\r | |
162 | \r | |
163 | --*/\r | |
44788bae | 164 | EFI_STATUS\r |
165 | EFIAPI\r | |
166 | InitializeCpuPeim (\r | |
167 | IN EFI_PEI_FILE_HANDLE FileHandle,\r | |
168 | IN CONST EFI_PEI_SERVICES **PeiServices\r | |
169 | )\r | |
afdfe8f0 | 170 | {\r |
44788bae | 171 | EFI_STATUS Status;\r |
172 | ARM_MP_CORE_INFO_PPI *ArmMpCoreInfoPpi;\r | |
173 | UINTN ArmCoreCount;\r | |
174 | ARM_CORE_INFO *ArmCoreInfoTable;\r | |
175 | \r | |
afdfe8f0 | 176 | // Enable program flow prediction, if supported.\r |
177 | ArmEnableBranchPrediction ();\r | |
178 | \r | |
44788bae | 179 | // Publish the CPU memory and io spaces sizes\r |
149daa61 | 180 | BuildCpuHob (PcdGet8 (PcdPrePiCpuMemorySize), PcdGet8 (PcdPrePiCpuIoSize));\r |
181 | \r | |
44788bae | 182 | //ConfigureMmu();\r |
183 | \r | |
184 | // Only MP Core platform need to produce gArmMpCoreInfoPpiGuid\r | |
185 | Status = PeiServicesLocatePpi (&gArmMpCoreInfoPpiGuid, 0, NULL, (VOID**)&ArmMpCoreInfoPpi);\r | |
186 | if (!EFI_ERROR(Status)) {\r | |
187 | // Build the MP Core Info Table\r | |
188 | ArmCoreCount = 0;\r | |
189 | Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);\r | |
190 | if (!EFI_ERROR(Status) && (ArmCoreCount > 0)) {\r | |
191 | // Build MPCore Info HOB\r | |
192 | BuildGuidDataHob (&gArmMpCoreInfoGuid, ArmCoreInfoTable, sizeof (ARM_CORE_INFO) * ArmCoreCount);\r | |
193 | }\r | |
194 | }\r | |
afdfe8f0 | 195 | \r |
196 | return EFI_SUCCESS;\r | |
197 | }\r |