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1bfda055 | 1 | /** @file\r |
2 | *\r | |
3 | * Copyright (c) 2011, ARM Limited. All rights reserved.\r | |
4 | * \r | |
5 | * This program and the accompanying materials \r | |
6 | * are licensed and made available under the terms and conditions of the BSD License \r | |
7 | * which accompanies this distribution. The full text of the license may be found at \r | |
8 | * http://opensource.org/licenses/bsd-license.php \r | |
9 | *\r | |
10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
12 | *\r | |
13 | **/\r | |
14 | \r | |
438311a3 | 15 | #include <Uefi.h>\r |
1bfda055 | 16 | #include <Library/IoLib.h>\r |
17 | #include <Drivers/PL390Gic.h>\r | |
18 | \r | |
19 | \r | |
20 | VOID\r | |
21 | EFIAPI\r | |
22 | PL390GicEnableInterruptInterface (\r | |
23 | IN INTN GicInterruptInterfaceBase\r | |
24 | )\r | |
2ac288f9 | 25 | { \r |
26 | /*\r | |
438311a3 | 27 | * Enable the CPU interface in Non-Secure world\r |
28 | * Note: The ICCICR register is banked when Security extensions are implemented\r | |
29 | */\r | |
30 | MmioWrite32 (GicInterruptInterfaceBase + GIC_ICCICR,0x00000001);\r | |
1bfda055 | 31 | }\r |
32 | \r | |
33 | VOID\r | |
34 | EFIAPI\r | |
35 | PL390GicEnableDistributor (\r | |
36 | IN INTN GicDistributorBase\r | |
37 | )\r | |
38 | {\r | |
438311a3 | 39 | /*\r |
40 | * Enable GIC distributor in Non-Secure world.\r | |
41 | * Note: The ICDDCR register is banked when Security extensions are implemented\r | |
42 | */\r | |
43 | MmioWrite32 (GicDistributorBase + GIC_ICDDCR, 0x00000001);\r | |
1bfda055 | 44 | }\r |
45 | \r | |
46 | VOID\r | |
47 | EFIAPI\r | |
48 | PL390GicSendSgiTo (\r | |
49 | IN INTN GicDistributorBase,\r | |
50 | IN INTN TargetListFilter,\r | |
51 | IN INTN CPUTargetList\r | |
52 | )\r | |
53 | {\r | |
438311a3 | 54 | MmioWrite32 (GicDistributorBase + GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16));\r |
1bfda055 | 55 | }\r |
56 | \r | |
57 | UINT32\r | |
58 | EFIAPI\r | |
59 | PL390GicAcknowledgeSgiFrom (\r | |
60 | IN INTN GicInterruptInterfaceBase,\r | |
61 | IN INTN CoreId\r | |
62 | )\r | |
63 | {\r | |
438311a3 | 64 | INTN InterruptId;\r |
1bfda055 | 65 | \r |
438311a3 | 66 | InterruptId = MmioRead32 (GicInterruptInterfaceBase + GIC_ICCIAR);\r |
1bfda055 | 67 | \r |
438311a3 | 68 | // Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID\r |
2ac288f9 | 69 | if (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) {\r |
438311a3 | 70 | // Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR\r |
71 | MmioWrite32 (GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);\r | |
72 | return 1;\r | |
73 | } else {\r | |
74 | return 0;\r | |
75 | }\r | |
1bfda055 | 76 | }\r |
77 | \r | |
78 | UINT32\r | |
79 | EFIAPI\r | |
80 | PL390GicAcknowledgeSgi2From (\r | |
81 | IN INTN GicInterruptInterfaceBase,\r | |
82 | IN INTN CoreId,\r | |
83 | IN INTN SgiId\r | |
84 | )\r | |
85 | {\r | |
438311a3 | 86 | INTN InterruptId;\r |
1bfda055 | 87 | \r |
438311a3 | 88 | InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);\r |
1bfda055 | 89 | \r |
438311a3 | 90 | // Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID\r |
2ac288f9 | 91 | if((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) {\r |
438311a3 | 92 | // Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR\r |
93 | MmioWrite32 (GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);\r | |
94 | return 1;\r | |
95 | } else {\r | |
96 | return 0;\r | |
97 | }\r | |
1bfda055 | 98 | }\r |