[mirror_edk2.git] / ArmPkg / Include / Drivers / PL390Gic.h

/** @file\r
*\r
*  Copyright (c) 2011, ARM Limited. All rights reserved.\r
*  \r
*  This program and the accompanying materials                          \r
*  are licensed and made available under the terms and conditions of the BSD License         \r
*  which accompanies this distribution.  The full text of the license may be found at        \r
*  http://opensource.org/licenses/bsd-license.php                                            \r
*\r
*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
*\r
**/\r
\r
#ifndef __PL390GIC_H\r
#define __PL390GIC_H\r
\r
//\r
// GIC definitions\r
//\r
\r
// Distributor\r
#define GIC_ICDDCR          0x000 // Distributor Control Register\r
#define GIC_ICDICTR         0x004 // Interrupt Controller Type Register\r
#define GIC_ICDIIDR         0x008 // Implementer Identification Register\r
\r
// each reg base below repeats for VE_NUM_GIC_REG_PER_INT_BITS (see GIC spec)\r
#define GIC_ICDISR          0x080 // Interrupt Security Registers\r
#define GIC_ICDISER         0x100 // Interrupt Set-Enable Registers\r
#define GIC_ICDICER         0x180 // Interrupt Clear-Enable Registers\r
#define GIC_ICDSPR          0x200 // Interrupt Set-Pending Registers\r
#define GIC_ICDICPR         0x280 // Interrupt Clear-Pending Registers\r
#define GIC_ICDABR          0x300 // Active Bit Registers\r
\r
// each reg base below repeats for VE_NUM_GIC_REG_PER_INT_BYTES\r
#define GIC_ICDIPR          0x400 // Interrupt Priority Registers\r
\r
// each reg base below repeats for VE_NUM_GIC_INTERRUPTS\r
#define GIC_ICDIPTR         0x800 // Interrupt Processor Target Registers\r
#define GIC_ICDICFR         0xC00 // Interrupt Configuration Registers\r
\r
// just one of these\r
#define GIC_ICDSGIR         0xF00 // Software Generated Interrupt Register\r
\r
// Cpu interface\r
#define GIC_ICCICR          0x00  // CPU Interface Control Register\r
#define GIC_ICCPMR          0x04  // Interrupt Priority Mask Register\r
#define GIC_ICCBPR          0x08  // Binary Point Register\r
#define GIC_ICCIAR          0x0C  // Interrupt Acknowledge Register\r
#define GIC_ICCEIOR         0x10  // End Of Interrupt Register\r
#define GIC_ICCRPR          0x14  // Running Priority Register\r
#define GIC_ICCPIR          0x18  // Highest Pending Interrupt Register\r
#define GIC_ICCABPR         0x1C  // Aliased Binary Point Register\r
#define GIC_ICCIDR          0xFC  // Identification Register\r
\r
#define GIC_ICDSGIR_FILTER_TARGETLIST       0x0\r
#define GIC_ICDSGIR_FILTER_EVERYONEELSE     0x1\r
#define GIC_ICDSGIR_FILTER_ITSELF           0x2\r
\r
//Bit-masks to configure the CPU Interface Control register\r
#define GIC_ICCICR_ENABLE_SECURE(a)       ((a << 0) & 0x01)\r
#define GIC_ICCICR_ENABLE_NS(a)           ((a << 1) & 0x02)\r
#define GIC_ICCICR_ACK_CTL(a)             ((a << 2) & 0x04)\r
#define GIC_ICCICR_SIGNAL_SECURE_TO_FIQ(a)((a << 3) & 0x08)\r
#define GIC_ICCICR_USE_SBPR(a)            ((a << 4) & 0x10)\r
\r
\r
//\r
// GIC SEC interfaces\r
//\r
VOID\r
EFIAPI\r
PL390GicSetupNonSecure (\r
  IN  INTN          GicDistributorBase,\r
  IN  INTN          GicInterruptInterfaceBase\r
  );\r
\r
VOID\r
EFIAPI\r
PL390GicEnableInterruptInterface (\r
  IN  INTN          GicInterruptInterfaceBase\r
  );\r
\r
VOID\r
EFIAPI\r
PL390GicEnableDistributor (\r
  IN  INTN          GicDistributorBase\r
  );\r
\r
VOID\r
EFIAPI\r
PL390GicSendSgiTo (\r
  IN  INTN          GicDistributorBase,\r
  IN  INTN          TargetListFilter,\r
  IN  INTN          CPUTargetList\r
  );\r
\r
UINT32\r
EFIAPI\r
PL390GicAcknowledgeSgiFrom (\r
  IN  INTN          GicInterruptInterfaceBase,\r
  IN  INTN          CoreId\r
  );\r
\r
UINT32\r
EFIAPI\r
PL390GicAcknowledgeSgi2From (\r
  IN  INTN          GicInterruptInterfaceBase,\r
  IN  INTN          CoreId,\r
  IN  INTN          SgiId\r
  );\r
\r
UINTN\r
EFIAPI\r
PL390GicSetPriorityMask (\r
  IN  INTN          GicInterruptInterfaceBase,\r
  IN  INTN          PriorityMask\r
  );\r
\r
#endif\r
Commit	Line	Data
1bfda055	1	/** @file\r
	2	*\r
	3	* Copyright (c) 2011, ARM Limited. All rights reserved.\r
	4	* \r
	5	* This program and the accompanying materials \r
	6	* are licensed and made available under the terms and conditions of the BSD License \r
	7	* which accompanies this distribution. The full text of the license may be found at \r
	8	* http://opensource.org/licenses/bsd-license.php \r
	9	*\r
	10	* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
	11	* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
	12	*\r
	13	**/\r
	14	\r
	15	#ifndef __PL390GIC_H\r
	16	#define __PL390GIC_H\r
	17	\r
	18	//\r
	19	// GIC definitions\r
	20	//\r
	21	\r
	22	// Distributor\r
	23	#define GIC_ICDDCR 0x000 // Distributor Control Register\r
	24	#define GIC_ICDICTR 0x004 // Interrupt Controller Type Register\r
	25	#define GIC_ICDIIDR 0x008 // Implementer Identification Register\r
	26	\r
	27	// each reg base below repeats for VE_NUM_GIC_REG_PER_INT_BITS (see GIC spec)\r
	28	#define GIC_ICDISR 0x080 // Interrupt Security Registers\r
	29	#define GIC_ICDISER 0x100 // Interrupt Set-Enable Registers\r
	30	#define GIC_ICDICER 0x180 // Interrupt Clear-Enable Registers\r
	31	#define GIC_ICDSPR 0x200 // Interrupt Set-Pending Registers\r
	32	#define GIC_ICDICPR 0x280 // Interrupt Clear-Pending Registers\r
	33	#define GIC_ICDABR 0x300 // Active Bit Registers\r
	34	\r
	35	// each reg base below repeats for VE_NUM_GIC_REG_PER_INT_BYTES\r
	36	#define GIC_ICDIPR 0x400 // Interrupt Priority Registers\r
	37	\r
	38	// each reg base below repeats for VE_NUM_GIC_INTERRUPTS\r
	39	#define GIC_ICDIPTR 0x800 // Interrupt Processor Target Registers\r
	40	#define GIC_ICDICFR 0xC00 // Interrupt Configuration Registers\r
	41	\r
	42	// just one of these\r
	43	#define GIC_ICDSGIR 0xF00 // Software Generated Interrupt Register\r
	44	\r
	45	// Cpu interface\r
	46	#define GIC_ICCICR 0x00 // CPU Interface Control Register\r
	47	#define GIC_ICCPMR 0x04 // Interrupt Priority Mask Register\r
	48	#define GIC_ICCBPR 0x08 // Binary Point Register\r
	49	#define GIC_ICCIAR 0x0C // Interrupt Acknowledge Register\r
	50	#define GIC_ICCEIOR 0x10 // End Of Interrupt Register\r
	51	#define GIC_ICCRPR 0x14 // Running Priority Register\r
	52	#define GIC_ICCPIR 0x18 // Highest Pending Interrupt Register\r
	53	#define GIC_ICCABPR 0x1C // Aliased Binary Point Register\r
	54	#define GIC_ICCIDR 0xFC // Identification Register\r
	55	\r
	56	#define GIC_ICDSGIR_FILTER_TARGETLIST 0x0\r
	57	#define GIC_ICDSGIR_FILTER_EVERYONEELSE 0x1\r
	58	#define GIC_ICDSGIR_FILTER_ITSELF 0x2\r
	59	\r
	60	//Bit-masks to configure the CPU Interface Control register\r
	61	#define GIC_ICCICR_ENABLE_SECURE(a) ((a << 0) & 0x01)\r
	62	#define GIC_ICCICR_ENABLE_NS(a) ((a << 1) & 0x02)\r
	63	#define GIC_ICCICR_ACK_CTL(a) ((a << 2) & 0x04)\r
	64	#define GIC_ICCICR_SIGNAL_SECURE_TO_FIQ(a)((a << 3) & 0x08)\r
65	#define GIC_ICCICR_USE_SBPR(a) ((a << 4) & 0x10)\r
66	\r
67	\r
68	//\r
69	// GIC SEC interfaces\r
70	//\r
71	VOID\r
72	EFIAPI\r
73	PL390GicSetupNonSecure (\r
74	IN INTN GicDistributorBase,\r
75	IN INTN GicInterruptInterfaceBase\r
76	);\r
77	\r
78	VOID\r
79	EFIAPI\r
80	PL390GicEnableInterruptInterface (\r
81	IN INTN GicInterruptInterfaceBase\r
82	);\r
83	\r
84	VOID\r
85	EFIAPI\r
86	PL390GicEnableDistributor (\r
87	IN INTN GicDistributorBase\r
88	);\r
89	\r
90	VOID\r
91	EFIAPI\r
92	PL390GicSendSgiTo (\r
93	IN INTN GicDistributorBase,\r
94	IN INTN TargetListFilter,\r
95	IN INTN CPUTargetList\r
96	);\r
97	\r
98	UINT32\r
99	EFIAPI\r
100	PL390GicAcknowledgeSgiFrom (\r
101	IN INTN GicInterruptInterfaceBase,\r
102	IN INTN CoreId\r
103	);\r
104	\r
105	UINT32\r
106	EFIAPI\r
107	PL390GicAcknowledgeSgi2From (\r
108	IN INTN GicInterruptInterfaceBase,\r
109	IN INTN CoreId,\r
110	IN INTN SgiId\r
111	);\r
112	\r
113	UINTN\r
114	EFIAPI\r
115	PL390GicSetPriorityMask (\r
116	IN INTN GicInterruptInterfaceBase,\r
117	IN INTN PriorityMask\r
118	);\r
119	\r
120	#endif\r