]>
Commit | Line | Data |
---|---|---|
a63914d3 RC |
1 | /** @file\r |
2 | \r | |
3 | Copyright (c) 2020 - 2021, NUVIA Inc. All rights reserved.<BR>\r | |
4 | \r | |
5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
6 | \r | |
7 | **/\r | |
8 | \r | |
9 | #ifndef ARM_CACHE_H_\r | |
10 | #define ARM_CACHE_H_\r | |
11 | \r | |
12 | #include <Uefi/UefiBaseType.h>\r | |
13 | \r | |
14 | // The ARM Architecture Reference Manual for ARMv8-A defines up\r | |
15 | // to 7 levels of cache, L1 through L7.\r | |
16 | #define MAX_ARM_CACHE_LEVEL 7\r | |
17 | \r | |
18 | /// Defines the structure of the CSSELR (Cache Size Selection) register\r | |
19 | typedef union {\r | |
20 | struct {\r | |
21 | UINT32 InD :1; ///< Instruction not Data bit\r | |
22 | UINT32 Level :3; ///< Cache level (zero based)\r | |
23 | UINT32 TnD :1; ///< Allocation not Data bit\r | |
24 | UINT32 Reserved :27; ///< Reserved, RES0\r | |
25 | } Bits; ///< Bitfield definition of the register\r | |
26 | UINT32 Data; ///< The entire 32-bit value\r | |
27 | } CSSELR_DATA;\r | |
28 | \r | |
29 | /// The cache type values for the InD field of the CSSELR register\r | |
30 | typedef enum\r | |
31 | {\r | |
32 | /// Select the data or unified cache\r | |
33 | CsselrCacheTypeDataOrUnified = 0,\r | |
34 | /// Select the instruction cache\r | |
35 | CsselrCacheTypeInstruction,\r | |
36 | CsselrCacheTypeMax\r | |
37 | } CSSELR_CACHE_TYPE;\r | |
38 | \r | |
39 | /// Defines the structure of the CCSIDR (Current Cache Size ID) register\r | |
40 | typedef union {\r | |
41 | struct {\r | |
42 | UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4)\r | |
43 | UINT64 Associativity :10; ///< Associativity - 1\r | |
44 | UINT64 NumSets :15; ///< Number of sets in the cache -1\r | |
45 | UINT64 Unknown :4; ///< Reserved, UNKNOWN\r | |
46 | UINT64 Reserved :32; ///< Reserved, RES0\r | |
47 | } BitsNonCcidx; ///< Bitfield definition of the register when FEAT_CCIDX is not supported.\r | |
48 | struct {\r | |
49 | UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4)\r | |
50 | UINT64 Associativity :21; ///< Associativity - 1\r | |
51 | UINT64 Reserved1 :8; ///< Reserved, RES0\r | |
52 | UINT64 NumSets :24; ///< Number of sets in the cache -1\r | |
53 | UINT64 Reserved2 :8; ///< Reserved, RES0\r | |
54 | } BitsCcidxAA64; ///< Bitfield definition of the register when FEAT_IDX is supported.\r | |
55 | struct {\r | |
56 | UINT64 LineSize : 3;\r | |
57 | UINT64 Associativity : 21;\r | |
58 | UINT64 Reserved : 8;\r | |
59 | UINT64 Unallocated : 32;\r | |
60 | } BitsCcidxAA32;\r | |
61 | UINT64 Data; ///< The entire 64-bit value\r | |
62 | } CCSIDR_DATA;\r | |
63 | \r | |
64 | /// Defines the structure of the AARCH32 CCSIDR2 register.\r | |
65 | typedef union {\r | |
66 | struct {\r | |
67 | UINT32 NumSets :24; ///< Number of sets in the cache - 1\r | |
68 | UINT32 Reserved :8; ///< Reserved, RES0\r | |
69 | } Bits; ///< Bitfield definition of the register\r | |
70 | UINT32 Data; ///< The entire 32-bit value\r | |
71 | } CCSIDR2_DATA;\r | |
72 | \r | |
73 | /** Defines the structure of the CLIDR (Cache Level ID) register.\r | |
74 | *\r | |
75 | * The lower 32 bits are the same for both AARCH32 and AARCH64\r | |
76 | * so we can use the same structure for both.\r | |
77 | **/\r | |
78 | typedef union {\r | |
79 | struct {\r | |
80 | UINT32 Ctype1 : 3; ///< Level 1 cache type\r | |
81 | UINT32 Ctype2 : 3; ///< Level 2 cache type\r | |
82 | UINT32 Ctype3 : 3; ///< Level 3 cache type\r | |
83 | UINT32 Ctype4 : 3; ///< Level 4 cache type\r | |
84 | UINT32 Ctype5 : 3; ///< Level 5 cache type\r | |
85 | UINT32 Ctype6 : 3; ///< Level 6 cache type\r | |
86 | UINT32 Ctype7 : 3; ///< Level 7 cache type\r | |
87 | UINT32 LoUIS : 3; ///< Level of Unification Inner Shareable\r | |
88 | UINT32 LoC : 3; ///< Level of Coherency\r | |
89 | UINT32 LoUU : 3; ///< Level of Unification Uniprocessor\r | |
90 | UINT32 Icb : 3; ///< Inner Cache Boundary\r | |
91 | } Bits; ///< Bitfield definition of the register\r | |
92 | UINT32 Data; ///< The entire 32-bit value\r | |
93 | } CLIDR_DATA;\r | |
94 | \r | |
95 | /// The cache types reported in the CLIDR register.\r | |
96 | typedef enum {\r | |
97 | /// No cache is present\r | |
98 | ClidrCacheTypeNone = 0,\r | |
99 | /// There is only an instruction cache\r | |
100 | ClidrCacheTypeInstructionOnly,\r | |
101 | /// There is only a data cache\r | |
102 | ClidrCacheTypeDataOnly,\r | |
103 | /// There are separate data and instruction caches\r | |
104 | ClidrCacheTypeSeparate,\r | |
105 | /// There is a unified cache\r | |
106 | ClidrCacheTypeUnified,\r | |
107 | ClidrCacheTypeMax\r | |
108 | } CLIDR_CACHE_TYPE;\r | |
109 | \r | |
110 | #define CLIDR_GET_CACHE_TYPE(x, level) ((x >> (3 * (level))) & 0b111)\r | |
111 | \r | |
112 | #endif /* ARM_CACHE_H_ */\r |