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55a0d64b | 1 | /** @file\r |
2 | *\r | |
919697ae | 3 | * Copyright (c) 2011-2015, ARM Limited. All rights reserved.\r |
55a0d64b | 4 | *\r |
1cb13673 OM |
5 | * This program and the accompanying materials\r |
6 | * are licensed and made available under the terms and conditions of the BSD License\r | |
7 | * which accompanies this distribution. The full text of the license may be found at\r | |
8 | * http://opensource.org/licenses/bsd-license.php\r | |
9 | *\r | |
10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
55a0d64b | 12 | *\r |
13 | **/\r | |
14 | \r | |
017baa1c OM |
15 | #ifndef __ARMGIC_H\r |
16 | #define __ARMGIC_H\r | |
55a0d64b | 17 | \r |
18 | //\r | |
19 | // GIC definitions\r | |
20 | //\r | |
d5c6b7fc | 21 | typedef enum {\r |
5f525769 OM |
22 | ARM_GIC_ARCH_REVISION_2,\r |
23 | ARM_GIC_ARCH_REVISION_3\r | |
d5c6b7fc | 24 | } ARM_GIC_ARCH_REVISION;\r |
55a0d64b | 25 | \r |
26 | //\r | |
27 | // GIC Distributor\r | |
28 | //\r | |
29 | #define ARM_GIC_ICDDCR 0x000 // Distributor Control Register\r | |
30 | #define ARM_GIC_ICDICTR 0x004 // Interrupt Controller Type Register\r | |
31 | #define ARM_GIC_ICDIIDR 0x008 // Implementer Identification Register\r | |
32 | \r | |
919697ae | 33 | // Each reg base below repeats for Number of interrupts / 4 (see GIC spec)\r |
55a0d64b | 34 | #define ARM_GIC_ICDISR 0x080 // Interrupt Security Registers\r |
35 | #define ARM_GIC_ICDISER 0x100 // Interrupt Set-Enable Registers\r | |
36 | #define ARM_GIC_ICDICER 0x180 // Interrupt Clear-Enable Registers\r | |
37 | #define ARM_GIC_ICDSPR 0x200 // Interrupt Set-Pending Registers\r | |
38 | #define ARM_GIC_ICDICPR 0x280 // Interrupt Clear-Pending Registers\r | |
39 | #define ARM_GIC_ICDABR 0x300 // Active Bit Registers\r | |
40 | \r | |
919697ae | 41 | // Each reg base below repeats for Number of interrupts / 4\r |
55a0d64b | 42 | #define ARM_GIC_ICDIPR 0x400 // Interrupt Priority Registers\r |
43 | \r | |
919697ae | 44 | // Each reg base below repeats for Number of interrupts\r |
55a0d64b | 45 | #define ARM_GIC_ICDIPTR 0x800 // Interrupt Processor Target Registers\r |
46 | #define ARM_GIC_ICDICFR 0xC00 // Interrupt Configuration Registers\r | |
47 | \r | |
48 | #define ARM_GIC_ICDPPISR 0xD00 // PPI Status register\r | |
49 | \r | |
50 | // just one of these\r | |
51 | #define ARM_GIC_ICDSGIR 0xF00 // Software Generated Interrupt Register\r | |
52 | \r | |
919697ae OM |
53 | // GICv3 specific registers\r |
54 | #define ARM_GICD_IROUTER 0x6100 // Interrupt Routing Registers\r | |
55 | \r | |
56 | //\r | |
57 | // GIC Redistributor\r | |
58 | //\r | |
59 | \r | |
60 | #define ARM_GICR_CTLR_FRAME_SIZE SIZE_64KB\r | |
61 | #define ARM_GICR_SGI_PPI_FRAME_SIZE SIZE_64KB\r | |
62 | \r | |
63 | // GIC Redistributor Control frame\r | |
64 | #define ARM_GICR_TYPER 0x0008 // Redistributor Type Register\r | |
65 | \r | |
66 | // GIC SGI & PPI Redistributor frame\r | |
67 | #define ARM_GICR_ISENABLER 0x0100 // Interrupt Set-Enable Registers\r | |
68 | #define ARM_GICR_ICENABLER 0x0180 // Interrupt Clear-Enable Registers\r | |
69 | \r | |
55a0d64b | 70 | //\r |
71 | // GIC Cpu interface\r | |
72 | //\r | |
73 | #define ARM_GIC_ICCICR 0x00 // CPU Interface Control Register\r | |
74 | #define ARM_GIC_ICCPMR 0x04 // Interrupt Priority Mask Register\r | |
75 | #define ARM_GIC_ICCBPR 0x08 // Binary Point Register\r | |
76 | #define ARM_GIC_ICCIAR 0x0C // Interrupt Acknowledge Register\r | |
77 | #define ARM_GIC_ICCEIOR 0x10 // End Of Interrupt Register\r | |
78 | #define ARM_GIC_ICCRPR 0x14 // Running Priority Register\r | |
79 | #define ARM_GIC_ICCPIR 0x18 // Highest Pending Interrupt Register\r | |
80 | #define ARM_GIC_ICCABPR 0x1C // Aliased Binary Point Register\r | |
e700a1fc | 81 | #define ARM_GIC_ICCIIDR 0xFC // Identification Register\r |
55a0d64b | 82 | \r |
83 | #define ARM_GIC_ICDSGIR_FILTER_TARGETLIST 0x0\r | |
84 | #define ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE 0x1\r | |
85 | #define ARM_GIC_ICDSGIR_FILTER_ITSELF 0x2\r | |
86 | \r | |
87 | // Bit-masks to configure the CPU Interface Control register\r | |
88 | #define ARM_GIC_ICCICR_ENABLE_SECURE 0x01\r | |
89 | #define ARM_GIC_ICCICR_ENABLE_NS 0x02\r | |
90 | #define ARM_GIC_ICCICR_ACK_CTL 0x04\r | |
91 | #define ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ 0x08\r | |
92 | #define ARM_GIC_ICCICR_USE_SBPR 0x10\r | |
93 | \r | |
1cb13673 | 94 | // Bit Mask for GICC_IIDR\r |
e700a1fc OM |
95 | #define ARM_GIC_ICCIIDR_GET_PRODUCT_ID(IccIidr) (((IccIidr) >> 20) & 0xFFF)\r |
96 | #define ARM_GIC_ICCIIDR_GET_ARCH_VERSION(IccIidr) (((IccIidr) >> 16) & 0xF)\r | |
97 | #define ARM_GIC_ICCIIDR_GET_REVISION(IccIidr) (((IccIidr) >> 12) & 0xF)\r | |
98 | #define ARM_GIC_ICCIIDR_GET_IMPLEMENTER(IccIidr) ((IccIidr) & 0xFFF)\r | |
55a0d64b | 99 | \r |
5f81082e OM |
100 | // Bit Mask for\r |
101 | #define ARM_GIC_ICCIAR_ACKINTID 0x3FF\r | |
102 | \r | |
d5c6b7fc OM |
103 | ARM_GIC_ARCH_REVISION\r |
104 | EFIAPI\r | |
105 | ArmGicGetSupportedArchRevision (\r | |
106 | VOID\r | |
107 | );\r | |
108 | \r | |
e700a1fc OM |
109 | UINTN\r |
110 | EFIAPI\r | |
111 | ArmGicGetInterfaceIdentification (\r | |
112 | IN INTN GicInterruptInterfaceBase\r | |
113 | );\r | |
114 | \r | |
55a0d64b | 115 | //\r |
92534106 | 116 | // GIC Secure interfaces\r |
55a0d64b | 117 | //\r |
118 | VOID\r | |
119 | EFIAPI\r | |
120 | ArmGicSetupNonSecure (\r | |
5e773144 | 121 | IN UINTN MpId,\r |
55a0d64b | 122 | IN INTN GicDistributorBase,\r |
123 | IN INTN GicInterruptInterfaceBase\r | |
124 | );\r | |
125 | \r | |
92534106 | 126 | VOID\r |
127 | EFIAPI\r | |
128 | ArmGicSetSecureInterrupts (\r | |
129 | IN UINTN GicDistributorBase,\r | |
130 | IN UINTN* GicSecureInterruptMask,\r | |
131 | IN UINTN GicSecureInterruptMaskSize\r | |
132 | );\r | |
133 | \r | |
55a0d64b | 134 | VOID\r |
135 | EFIAPI\r | |
136 | ArmGicEnableInterruptInterface (\r | |
137 | IN INTN GicInterruptInterfaceBase\r | |
138 | );\r | |
139 | \r | |
9736c297 | 140 | VOID\r |
141 | EFIAPI\r | |
142 | ArmGicDisableInterruptInterface (\r | |
143 | IN INTN GicInterruptInterfaceBase\r | |
144 | );\r | |
145 | \r | |
55a0d64b | 146 | VOID\r |
147 | EFIAPI\r | |
148 | ArmGicEnableDistributor (\r | |
149 | IN INTN GicDistributorBase\r | |
150 | );\r | |
151 | \r | |
e700a1fc OM |
152 | VOID\r |
153 | EFIAPI\r | |
154 | ArmGicDisableDistributor (\r | |
155 | IN INTN GicDistributorBase\r | |
156 | );\r | |
157 | \r | |
e9f7c58f | 158 | UINTN\r |
159 | EFIAPI\r | |
160 | ArmGicGetMaxNumInterrupts (\r | |
161 | IN INTN GicDistributorBase\r | |
162 | );\r | |
163 | \r | |
55a0d64b | 164 | VOID\r |
165 | EFIAPI\r | |
166 | ArmGicSendSgiTo (\r | |
167 | IN INTN GicDistributorBase,\r | |
168 | IN INTN TargetListFilter,\r | |
4c19ece3 | 169 | IN INTN CPUTargetList,\r |
170 | IN INTN SgiId\r | |
55a0d64b | 171 | );\r |
172 | \r | |
1b0ac0de OM |
173 | /*\r |
174 | * Acknowledge and return the value of the Interrupt Acknowledge Register\r | |
175 | *\r | |
176 | * InterruptId is returned separately from the register value because in\r | |
177 | * the GICv2 the register value contains the CpuId and InterruptId while\r | |
178 | * in the GICv3 the register value is only the InterruptId.\r | |
179 | *\r | |
180 | * @param GicInterruptInterfaceBase Base Address of the GIC CPU Interface\r | |
181 | * @param InterruptId InterruptId read from the Interrupt Acknowledge Register\r | |
182 | *\r | |
183 | * @retval value returned by the Interrupt Acknowledge Register\r | |
184 | *\r | |
185 | */\r | |
2ca815a4 | 186 | UINTN\r |
55a0d64b | 187 | EFIAPI\r |
315649cd | 188 | ArmGicAcknowledgeInterrupt (\r |
1b0ac0de OM |
189 | IN UINTN GicInterruptInterfaceBase,\r |
190 | OUT UINTN *InterruptId\r | |
55a0d64b | 191 | );\r |
192 | \r | |
d80401a1 OM |
193 | VOID\r |
194 | EFIAPI\r | |
195 | ArmGicEndOfInterrupt (\r | |
196 | IN UINTN GicInterruptInterfaceBase,\r | |
197 | IN UINTN Source\r | |
198 | );\r | |
199 | \r | |
55a0d64b | 200 | UINTN\r |
201 | EFIAPI\r | |
202 | ArmGicSetPriorityMask (\r | |
203 | IN INTN GicInterruptInterfaceBase,\r | |
204 | IN INTN PriorityMask\r | |
205 | );\r | |
206 | \r | |
e700a1fc OM |
207 | VOID\r |
208 | EFIAPI\r | |
209 | ArmGicEnableInterrupt (\r | |
210 | IN UINTN GicDistributorBase,\r | |
41fb5d46 | 211 | IN UINTN GicRedistributorBase,\r |
e700a1fc OM |
212 | IN UINTN Source\r |
213 | );\r | |
214 | \r | |
215 | VOID\r | |
216 | EFIAPI\r | |
217 | ArmGicDisableInterrupt (\r | |
218 | IN UINTN GicDistributorBase,\r | |
41fb5d46 | 219 | IN UINTN GicRedistributorBase,\r |
e700a1fc OM |
220 | IN UINTN Source\r |
221 | );\r | |
222 | \r | |
223 | BOOLEAN\r | |
224 | EFIAPI\r | |
225 | ArmGicIsInterruptEnabled (\r | |
226 | IN UINTN GicDistributorBase,\r | |
41fb5d46 | 227 | IN UINTN GicRedistributorBase,\r |
e700a1fc OM |
228 | IN UINTN Source\r |
229 | );\r | |
230 | \r | |
55a0d64b | 231 | #endif\r |