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55a0d64b | 1 | /** @file\r |
2 | *\r | |
e700a1fc | 3 | * Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r |
55a0d64b | 4 | *\r |
1cb13673 OM |
5 | * This program and the accompanying materials\r |
6 | * are licensed and made available under the terms and conditions of the BSD License\r | |
7 | * which accompanies this distribution. The full text of the license may be found at\r | |
8 | * http://opensource.org/licenses/bsd-license.php\r | |
9 | *\r | |
10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
55a0d64b | 12 | *\r |
13 | **/\r | |
14 | \r | |
017baa1c OM |
15 | #ifndef __ARMGIC_H\r |
16 | #define __ARMGIC_H\r | |
55a0d64b | 17 | \r |
18 | //\r | |
19 | // GIC definitions\r | |
20 | //\r | |
d5c6b7fc | 21 | typedef enum {\r |
5f525769 OM |
22 | ARM_GIC_ARCH_REVISION_2,\r |
23 | ARM_GIC_ARCH_REVISION_3\r | |
d5c6b7fc | 24 | } ARM_GIC_ARCH_REVISION;\r |
55a0d64b | 25 | \r |
26 | //\r | |
27 | // GIC Distributor\r | |
28 | //\r | |
29 | #define ARM_GIC_ICDDCR 0x000 // Distributor Control Register\r | |
30 | #define ARM_GIC_ICDICTR 0x004 // Interrupt Controller Type Register\r | |
31 | #define ARM_GIC_ICDIIDR 0x008 // Implementer Identification Register\r | |
32 | \r | |
33 | // Each reg base below repeats for VE_NUM_ARM_GIC_REG_PER_INT_BITS (see GIC spec)\r | |
34 | #define ARM_GIC_ICDISR 0x080 // Interrupt Security Registers\r | |
35 | #define ARM_GIC_ICDISER 0x100 // Interrupt Set-Enable Registers\r | |
36 | #define ARM_GIC_ICDICER 0x180 // Interrupt Clear-Enable Registers\r | |
37 | #define ARM_GIC_ICDSPR 0x200 // Interrupt Set-Pending Registers\r | |
38 | #define ARM_GIC_ICDICPR 0x280 // Interrupt Clear-Pending Registers\r | |
39 | #define ARM_GIC_ICDABR 0x300 // Active Bit Registers\r | |
40 | \r | |
41 | // Each reg base below repeats for VE_NUM_ARM_GIC_REG_PER_INT_BYTES\r | |
42 | #define ARM_GIC_ICDIPR 0x400 // Interrupt Priority Registers\r | |
43 | \r | |
44 | // Each reg base below repeats for VE_NUM_ARM_GIC_INTERRUPTS\r | |
45 | #define ARM_GIC_ICDIPTR 0x800 // Interrupt Processor Target Registers\r | |
46 | #define ARM_GIC_ICDICFR 0xC00 // Interrupt Configuration Registers\r | |
47 | \r | |
48 | #define ARM_GIC_ICDPPISR 0xD00 // PPI Status register\r | |
49 | \r | |
50 | // just one of these\r | |
51 | #define ARM_GIC_ICDSGIR 0xF00 // Software Generated Interrupt Register\r | |
52 | \r | |
53 | //\r | |
54 | // GIC Cpu interface\r | |
55 | //\r | |
56 | #define ARM_GIC_ICCICR 0x00 // CPU Interface Control Register\r | |
57 | #define ARM_GIC_ICCPMR 0x04 // Interrupt Priority Mask Register\r | |
58 | #define ARM_GIC_ICCBPR 0x08 // Binary Point Register\r | |
59 | #define ARM_GIC_ICCIAR 0x0C // Interrupt Acknowledge Register\r | |
60 | #define ARM_GIC_ICCEIOR 0x10 // End Of Interrupt Register\r | |
61 | #define ARM_GIC_ICCRPR 0x14 // Running Priority Register\r | |
62 | #define ARM_GIC_ICCPIR 0x18 // Highest Pending Interrupt Register\r | |
63 | #define ARM_GIC_ICCABPR 0x1C // Aliased Binary Point Register\r | |
e700a1fc | 64 | #define ARM_GIC_ICCIIDR 0xFC // Identification Register\r |
55a0d64b | 65 | \r |
66 | #define ARM_GIC_ICDSGIR_FILTER_TARGETLIST 0x0\r | |
67 | #define ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE 0x1\r | |
68 | #define ARM_GIC_ICDSGIR_FILTER_ITSELF 0x2\r | |
69 | \r | |
70 | // Bit-masks to configure the CPU Interface Control register\r | |
71 | #define ARM_GIC_ICCICR_ENABLE_SECURE 0x01\r | |
72 | #define ARM_GIC_ICCICR_ENABLE_NS 0x02\r | |
73 | #define ARM_GIC_ICCICR_ACK_CTL 0x04\r | |
74 | #define ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ 0x08\r | |
75 | #define ARM_GIC_ICCICR_USE_SBPR 0x10\r | |
76 | \r | |
1cb13673 | 77 | // Bit Mask for GICC_IIDR\r |
e700a1fc OM |
78 | #define ARM_GIC_ICCIIDR_GET_PRODUCT_ID(IccIidr) (((IccIidr) >> 20) & 0xFFF)\r |
79 | #define ARM_GIC_ICCIIDR_GET_ARCH_VERSION(IccIidr) (((IccIidr) >> 16) & 0xF)\r | |
80 | #define ARM_GIC_ICCIIDR_GET_REVISION(IccIidr) (((IccIidr) >> 12) & 0xF)\r | |
81 | #define ARM_GIC_ICCIIDR_GET_IMPLEMENTER(IccIidr) ((IccIidr) & 0xFFF)\r | |
55a0d64b | 82 | \r |
5f81082e OM |
83 | // Bit Mask for\r |
84 | #define ARM_GIC_ICCIAR_ACKINTID 0x3FF\r | |
85 | \r | |
d5c6b7fc OM |
86 | ARM_GIC_ARCH_REVISION\r |
87 | EFIAPI\r | |
88 | ArmGicGetSupportedArchRevision (\r | |
89 | VOID\r | |
90 | );\r | |
91 | \r | |
e700a1fc OM |
92 | UINTN\r |
93 | EFIAPI\r | |
94 | ArmGicGetInterfaceIdentification (\r | |
95 | IN INTN GicInterruptInterfaceBase\r | |
96 | );\r | |
97 | \r | |
55a0d64b | 98 | //\r |
92534106 | 99 | // GIC Secure interfaces\r |
55a0d64b | 100 | //\r |
101 | VOID\r | |
102 | EFIAPI\r | |
103 | ArmGicSetupNonSecure (\r | |
5e773144 | 104 | IN UINTN MpId,\r |
55a0d64b | 105 | IN INTN GicDistributorBase,\r |
106 | IN INTN GicInterruptInterfaceBase\r | |
107 | );\r | |
108 | \r | |
92534106 | 109 | VOID\r |
110 | EFIAPI\r | |
111 | ArmGicSetSecureInterrupts (\r | |
112 | IN UINTN GicDistributorBase,\r | |
113 | IN UINTN* GicSecureInterruptMask,\r | |
114 | IN UINTN GicSecureInterruptMaskSize\r | |
115 | );\r | |
116 | \r | |
55a0d64b | 117 | VOID\r |
118 | EFIAPI\r | |
119 | ArmGicEnableInterruptInterface (\r | |
120 | IN INTN GicInterruptInterfaceBase\r | |
121 | );\r | |
122 | \r | |
9736c297 | 123 | VOID\r |
124 | EFIAPI\r | |
125 | ArmGicDisableInterruptInterface (\r | |
126 | IN INTN GicInterruptInterfaceBase\r | |
127 | );\r | |
128 | \r | |
55a0d64b | 129 | VOID\r |
130 | EFIAPI\r | |
131 | ArmGicEnableDistributor (\r | |
132 | IN INTN GicDistributorBase\r | |
133 | );\r | |
134 | \r | |
e700a1fc OM |
135 | VOID\r |
136 | EFIAPI\r | |
137 | ArmGicDisableDistributor (\r | |
138 | IN INTN GicDistributorBase\r | |
139 | );\r | |
140 | \r | |
e9f7c58f | 141 | UINTN\r |
142 | EFIAPI\r | |
143 | ArmGicGetMaxNumInterrupts (\r | |
144 | IN INTN GicDistributorBase\r | |
145 | );\r | |
146 | \r | |
55a0d64b | 147 | VOID\r |
148 | EFIAPI\r | |
149 | ArmGicSendSgiTo (\r | |
150 | IN INTN GicDistributorBase,\r | |
151 | IN INTN TargetListFilter,\r | |
4c19ece3 | 152 | IN INTN CPUTargetList,\r |
153 | IN INTN SgiId\r | |
55a0d64b | 154 | );\r |
155 | \r | |
1b0ac0de OM |
156 | /*\r |
157 | * Acknowledge and return the value of the Interrupt Acknowledge Register\r | |
158 | *\r | |
159 | * InterruptId is returned separately from the register value because in\r | |
160 | * the GICv2 the register value contains the CpuId and InterruptId while\r | |
161 | * in the GICv3 the register value is only the InterruptId.\r | |
162 | *\r | |
163 | * @param GicInterruptInterfaceBase Base Address of the GIC CPU Interface\r | |
164 | * @param InterruptId InterruptId read from the Interrupt Acknowledge Register\r | |
165 | *\r | |
166 | * @retval value returned by the Interrupt Acknowledge Register\r | |
167 | *\r | |
168 | */\r | |
2ca815a4 | 169 | UINTN\r |
55a0d64b | 170 | EFIAPI\r |
315649cd | 171 | ArmGicAcknowledgeInterrupt (\r |
1b0ac0de OM |
172 | IN UINTN GicInterruptInterfaceBase,\r |
173 | OUT UINTN *InterruptId\r | |
55a0d64b | 174 | );\r |
175 | \r | |
d80401a1 OM |
176 | VOID\r |
177 | EFIAPI\r | |
178 | ArmGicEndOfInterrupt (\r | |
179 | IN UINTN GicInterruptInterfaceBase,\r | |
180 | IN UINTN Source\r | |
181 | );\r | |
182 | \r | |
55a0d64b | 183 | UINTN\r |
184 | EFIAPI\r | |
185 | ArmGicSetPriorityMask (\r | |
186 | IN INTN GicInterruptInterfaceBase,\r | |
187 | IN INTN PriorityMask\r | |
188 | );\r | |
189 | \r | |
e700a1fc OM |
190 | VOID\r |
191 | EFIAPI\r | |
192 | ArmGicEnableInterrupt (\r | |
193 | IN UINTN GicDistributorBase,\r | |
194 | IN UINTN Source\r | |
195 | );\r | |
196 | \r | |
197 | VOID\r | |
198 | EFIAPI\r | |
199 | ArmGicDisableInterrupt (\r | |
200 | IN UINTN GicDistributorBase,\r | |
201 | IN UINTN Source\r | |
202 | );\r | |
203 | \r | |
204 | BOOLEAN\r | |
205 | EFIAPI\r | |
206 | ArmGicIsInterruptEnabled (\r | |
207 | IN UINTN GicDistributorBase,\r | |
208 | IN UINTN Source\r | |
209 | );\r | |
210 | \r | |
55a0d64b | 211 | #endif\r |