| 1e57a462 |
1 | /** @file\r |
| 2 | \r |
| 3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r |
| 4 | Copyright (c) 2011 - 2012, ARM Ltd. All rights reserved.<BR>\r |
| 5 | \r |
| 6 | This program and the accompanying materials\r |
| 7 | are licensed and made available under the terms and conditions of the BSD License\r |
| 8 | which accompanies this distribution. The full text of the license may be found at\r |
| 9 | http://opensource.org/licenses/bsd-license.php\r |
| 10 | \r |
| 11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
| 12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
| 13 | \r |
| 14 | **/\r |
| 15 | \r |
| 16 | #ifndef __ARM_LIB__\r |
| 17 | #define __ARM_LIB__\r |
| 18 | \r |
| 19 | #include <Uefi/UefiBaseType.h>\r |
| 20 | \r |
| 21 | #ifdef ARM_CPU_ARMv6\r |
| 22 | #include <Chipset/ARM1176JZ-S.h>\r |
| 23 | #else\r |
| 24 | #include <Chipset/ArmV7.h>\r |
| 25 | #endif\r |
| 26 | \r |
| 27 | typedef enum {\r |
| 28 | ARM_CACHE_TYPE_WRITE_BACK,\r |
| 29 | ARM_CACHE_TYPE_UNKNOWN\r |
| 30 | } ARM_CACHE_TYPE;\r |
| 31 | \r |
| 32 | typedef enum {\r |
| 33 | ARM_CACHE_ARCHITECTURE_UNIFIED,\r |
| 34 | ARM_CACHE_ARCHITECTURE_SEPARATE,\r |
| 35 | ARM_CACHE_ARCHITECTURE_UNKNOWN\r |
| 36 | } ARM_CACHE_ARCHITECTURE;\r |
| 37 | \r |
| 38 | typedef struct {\r |
| 39 | ARM_CACHE_TYPE Type;\r |
| 40 | ARM_CACHE_ARCHITECTURE Architecture;\r |
| 41 | BOOLEAN DataCachePresent;\r |
| 42 | UINTN DataCacheSize;\r |
| 43 | UINTN DataCacheAssociativity;\r |
| 44 | UINTN DataCacheLineLength;\r |
| 45 | BOOLEAN InstructionCachePresent;\r |
| 46 | UINTN InstructionCacheSize;\r |
| 47 | UINTN InstructionCacheAssociativity;\r |
| 48 | UINTN InstructionCacheLineLength;\r |
| 49 | } ARM_CACHE_INFO;\r |
| 50 | \r |
| 51 | /**\r |
| 52 | * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.\r |
| 53 | *\r |
| 54 | * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only\r |
| 55 | * be used in Secure World to distinguished Secure to Non-Secure memory.\r |
| 56 | */\r |
| 57 | typedef enum {\r |
| 58 | ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,\r |
| 59 | ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,\r |
| 60 | ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,\r |
| 61 | ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,\r |
| 62 | ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,\r |
| 63 | ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,\r |
| 64 | ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,\r |
| 65 | ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE\r |
| 66 | } ARM_MEMORY_REGION_ATTRIBUTES;\r |
| 67 | \r |
| 68 | #define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)\r |
| 69 | \r |
| 70 | typedef struct {\r |
| 71 | EFI_PHYSICAL_ADDRESS PhysicalBase;\r |
| 72 | EFI_VIRTUAL_ADDRESS VirtualBase;\r |
| 73 | UINTN Length;\r |
| 74 | ARM_MEMORY_REGION_ATTRIBUTES Attributes;\r |
| 75 | } ARM_MEMORY_REGION_DESCRIPTOR;\r |
| 76 | \r |
| 77 | typedef VOID (*CACHE_OPERATION)(VOID);\r |
| 78 | typedef VOID (*LINE_OPERATION)(UINTN);\r |
| 79 | \r |
| 80 | //\r |
| 81 | // ARM Processor Mode\r |
| 82 | //\r |
| 83 | typedef enum {\r |
| 84 | ARM_PROCESSOR_MODE_USER = 0x10,\r |
| 85 | ARM_PROCESSOR_MODE_FIQ = 0x11,\r |
| 86 | ARM_PROCESSOR_MODE_IRQ = 0x12,\r |
| 87 | ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,\r |
| 88 | ARM_PROCESSOR_MODE_ABORT = 0x17,\r |
| 89 | ARM_PROCESSOR_MODE_HYP = 0x1A,\r |
| 90 | ARM_PROCESSOR_MODE_UNDEFINED = 0x1B,\r |
| 91 | ARM_PROCESSOR_MODE_SYSTEM = 0x1F,\r |
| 92 | ARM_PROCESSOR_MODE_MASK = 0x1F\r |
| 93 | } ARM_PROCESSOR_MODE;\r |
| 94 | \r |
| 95 | //\r |
| 96 | // ARM Cpu IDs\r |
| 97 | //\r |
| 98 | #define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)\r |
| 99 | #define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)\r |
| 100 | #define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)\r |
| 101 | #define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)\r |
| 102 | #define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)\r |
| 103 | #define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)\r |
| 104 | \r |
| 105 | #define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)\r |
| 106 | #define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)\r |
| 107 | #define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)\r |
| 108 | #define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)\r |
| 109 | #define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)\r |
| 110 | #define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)\r |
| 111 | \r |
| 112 | //\r |
| 113 | // ARM MP Core IDs\r |
| 114 | //\r |
| 115 | #define IS_PRIMARY_CORE(MpId) (((MpId) & PcdGet32(PcdArmPrimaryCoreMask)) == PcdGet32(PcdArmPrimaryCore))\r |
| 116 | #define ARM_CORE_MASK 0xFF\r |
| 117 | #define ARM_CLUSTER_MASK (0xFF << 8)\r |
| 118 | #define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)\r |
| 119 | #define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)\r |
| 120 | // Get the position of the core for the Stack Offset (4 Core per Cluster)\r |
| 121 | // Position = (ClusterId * 4) + CoreId\r |
| 122 | #define GET_CORE_POS(MpId) ((((MpId) & ARM_CLUSTER_MASK) >> 6) + ((MpId) & ARM_CORE_MASK))\r |
| 123 | #define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)\r |
| 124 | \r |
| 125 | ARM_CACHE_TYPE\r |
| 126 | EFIAPI\r |
| 127 | ArmCacheType (\r |
| 128 | VOID\r |
| 129 | );\r |
| 130 | \r |
| 131 | ARM_CACHE_ARCHITECTURE\r |
| 132 | EFIAPI\r |
| 133 | ArmCacheArchitecture (\r |
| 134 | VOID\r |
| 135 | );\r |
| 136 | \r |
| 137 | VOID\r |
| 138 | EFIAPI\r |
| 139 | ArmCacheInformation (\r |
| 140 | OUT ARM_CACHE_INFO *CacheInfo\r |
| 141 | );\r |
| 142 | \r |
| 143 | BOOLEAN\r |
| 144 | EFIAPI\r |
| 145 | ArmDataCachePresent (\r |
| 146 | VOID\r |
| 147 | );\r |
| 148 | \r |
| 149 | UINTN\r |
| 150 | EFIAPI\r |
| 151 | ArmDataCacheSize (\r |
| 152 | VOID\r |
| 153 | );\r |
| 154 | \r |
| 155 | UINTN\r |
| 156 | EFIAPI\r |
| 157 | ArmDataCacheAssociativity (\r |
| 158 | VOID\r |
| 159 | );\r |
| 160 | \r |
| 161 | UINTN\r |
| 162 | EFIAPI\r |
| 163 | ArmDataCacheLineLength (\r |
| 164 | VOID\r |
| 165 | );\r |
| 166 | \r |
| 167 | BOOLEAN\r |
| 168 | EFIAPI\r |
| 169 | ArmInstructionCachePresent (\r |
| 170 | VOID\r |
| 171 | );\r |
| 172 | \r |
| 173 | UINTN\r |
| 174 | EFIAPI\r |
| 175 | ArmInstructionCacheSize (\r |
| 176 | VOID\r |
| 177 | );\r |
| 178 | \r |
| 179 | UINTN\r |
| 180 | EFIAPI\r |
| 181 | ArmInstructionCacheAssociativity (\r |
| 182 | VOID\r |
| 183 | );\r |
| 184 | \r |
| 185 | UINTN\r |
| 186 | EFIAPI\r |
| 187 | ArmInstructionCacheLineLength (\r |
| 188 | VOID\r |
| 189 | );\r |
| 190 | \r |
| 191 | UINT32\r |
| 192 | EFIAPI\r |
| 193 | Cp15IdCode (\r |
| 194 | VOID\r |
| 195 | );\r |
| 196 | \r |
| 197 | UINT32\r |
| 198 | EFIAPI\r |
| 199 | Cp15CacheInfo (\r |
| 200 | VOID\r |
| 201 | );\r |
| 202 | \r |
| 203 | BOOLEAN\r |
| 204 | EFIAPI\r |
| 205 | ArmIsMpCore (\r |
| 206 | VOID\r |
| 207 | );\r |
| 208 | \r |
| 209 | VOID\r |
| 210 | EFIAPI\r |
| 211 | ArmInvalidateDataCache (\r |
| 212 | VOID\r |
| 213 | );\r |
| 214 | \r |
| 215 | \r |
| 216 | VOID\r |
| 217 | EFIAPI\r |
| 218 | ArmCleanInvalidateDataCache (\r |
| 219 | VOID\r |
| 220 | );\r |
| 221 | \r |
| 222 | VOID\r |
| 223 | EFIAPI\r |
| 224 | ArmCleanDataCache (\r |
| 225 | VOID\r |
| 226 | );\r |
| 227 | \r |
| 228 | VOID\r |
| 229 | EFIAPI\r |
| 230 | ArmCleanDataCacheToPoU (\r |
| 231 | VOID\r |
| 232 | );\r |
| 233 | \r |
| 234 | VOID\r |
| 235 | EFIAPI\r |
| 236 | ArmInvalidateInstructionCache (\r |
| 237 | VOID\r |
| 238 | );\r |
| 239 | \r |
| 240 | VOID\r |
| 241 | EFIAPI\r |
| 242 | ArmInvalidateDataCacheEntryByMVA (\r |
| 243 | IN UINTN Address\r |
| 244 | );\r |
| 245 | \r |
| 246 | VOID\r |
| 247 | EFIAPI\r |
| 248 | ArmCleanDataCacheEntryByMVA (\r |
| 249 | IN UINTN Address\r |
| 250 | );\r |
| 251 | \r |
| 252 | VOID\r |
| 253 | EFIAPI\r |
| 254 | ArmCleanInvalidateDataCacheEntryByMVA (\r |
| 255 | IN UINTN Address\r |
| 256 | );\r |
| 257 | \r |
| 258 | VOID\r |
| 259 | EFIAPI\r |
| 260 | ArmEnableDataCache (\r |
| 261 | VOID\r |
| 262 | );\r |
| 263 | \r |
| 264 | VOID\r |
| 265 | EFIAPI\r |
| 266 | ArmDisableDataCache (\r |
| 267 | VOID\r |
| 268 | );\r |
| 269 | \r |
| 270 | VOID\r |
| 271 | EFIAPI\r |
| 272 | ArmEnableInstructionCache (\r |
| 273 | VOID\r |
| 274 | );\r |
| 275 | \r |
| 276 | VOID\r |
| 277 | EFIAPI\r |
| 278 | ArmDisableInstructionCache (\r |
| 279 | VOID\r |
| 280 | );\r |
| 281 | \r |
| 282 | VOID\r |
| 283 | EFIAPI\r |
| 284 | ArmEnableMmu (\r |
| 285 | VOID\r |
| 286 | );\r |
| 287 | \r |
| 288 | VOID\r |
| 289 | EFIAPI\r |
| 290 | ArmDisableMmu (\r |
| 291 | VOID\r |
| 292 | );\r |
| 293 | \r |
| 294 | VOID\r |
| 295 | EFIAPI\r |
| 296 | ArmDisableCachesAndMmu (\r |
| 297 | VOID\r |
| 298 | );\r |
| 299 | \r |
| 300 | VOID\r |
| 301 | EFIAPI\r |
| 302 | ArmInvalidateInstructionAndDataTlb (\r |
| 303 | VOID\r |
| 304 | );\r |
| 305 | \r |
| 306 | VOID\r |
| 307 | EFIAPI\r |
| 308 | ArmEnableInterrupts (\r |
| 309 | VOID\r |
| 310 | );\r |
| 311 | \r |
| 312 | UINTN\r |
| 313 | EFIAPI\r |
| 314 | ArmDisableInterrupts (\r |
| 315 | VOID\r |
| 316 | );\r |
| 317 | \r |
| 318 | BOOLEAN\r |
| 319 | EFIAPI\r |
| 320 | ArmGetInterruptState (\r |
| 321 | VOID\r |
| 322 | );\r |
| 323 | \r |
| 324 | VOID\r |
| 325 | EFIAPI\r |
| 326 | ArmEnableFiq (\r |
| 327 | VOID\r |
| 328 | );\r |
| 329 | \r |
| 330 | UINTN\r |
| 331 | EFIAPI\r |
| 332 | ArmDisableFiq (\r |
| 333 | VOID\r |
| 334 | );\r |
| 335 | \r |
| 336 | BOOLEAN\r |
| 337 | EFIAPI\r |
| 338 | ArmGetFiqState (\r |
| 339 | VOID\r |
| 340 | );\r |
| 341 | \r |
| 342 | VOID\r |
| 343 | EFIAPI\r |
| 344 | ArmInvalidateTlb (\r |
| 345 | VOID\r |
| 346 | );\r |
| 347 | \r |
| 348 | VOID\r |
| 349 | EFIAPI\r |
| 350 | ArmUpdateTranslationTableEntry (\r |
| 351 | IN VOID *TranslationTableEntry,\r |
| 352 | IN VOID *Mva\r |
| 353 | );\r |
| 354 | \r |
| 355 | VOID\r |
| 356 | EFIAPI\r |
| 357 | ArmSetDomainAccessControl (\r |
| 358 | IN UINT32 Domain\r |
| 359 | );\r |
| 360 | \r |
| 361 | VOID\r |
| 362 | EFIAPI\r |
| 363 | ArmSetTTBR0 (\r |
| 364 | IN VOID *TranslationTableBase\r |
| 365 | );\r |
| 366 | \r |
| 367 | VOID *\r |
| 368 | EFIAPI\r |
| 369 | ArmGetTTBR0BaseAddress (\r |
| 370 | VOID\r |
| 371 | );\r |
| 372 | \r |
| 373 | VOID\r |
| 374 | EFIAPI\r |
| 375 | ArmConfigureMmu (\r |
| 376 | IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,\r |
| 377 | OUT VOID **TranslationTableBase OPTIONAL,\r |
| 378 | OUT UINTN *TranslationTableSize OPTIONAL\r |
| 379 | );\r |
| 380 | \r |
| 381 | BOOLEAN\r |
| 382 | EFIAPI\r |
| 383 | ArmMmuEnabled (\r |
| 384 | VOID\r |
| 385 | );\r |
| 386 | \r |
| 387 | VOID\r |
| 388 | EFIAPI\r |
| 389 | ArmSwitchProcessorMode (\r |
| 390 | IN ARM_PROCESSOR_MODE Mode\r |
| 391 | );\r |
| 392 | \r |
| 393 | ARM_PROCESSOR_MODE\r |
| 394 | EFIAPI\r |
| 395 | ArmProcessorMode (\r |
| 396 | VOID\r |
| 397 | );\r |
| 398 | \r |
| 399 | VOID\r |
| 400 | EFIAPI\r |
| 401 | ArmEnableBranchPrediction (\r |
| 402 | VOID\r |
| 403 | );\r |
| 404 | \r |
| 405 | VOID\r |
| 406 | EFIAPI\r |
| 407 | ArmDisableBranchPrediction (\r |
| 408 | VOID\r |
| 409 | );\r |
| 410 | \r |
| 411 | VOID\r |
| 412 | EFIAPI\r |
| 413 | ArmSetLowVectors (\r |
| 414 | VOID\r |
| 415 | );\r |
| 416 | \r |
| 417 | VOID\r |
| 418 | EFIAPI\r |
| 419 | ArmSetHighVectors (\r |
| 420 | VOID\r |
| 421 | );\r |
| 422 | \r |
| 423 | VOID\r |
| 424 | EFIAPI\r |
| 425 | ArmDataMemoryBarrier (\r |
| 426 | VOID\r |
| 427 | );\r |
| 428 | \r |
| 429 | VOID\r |
| 430 | EFIAPI\r |
| 431 | ArmDataSyncronizationBarrier (\r |
| 432 | VOID\r |
| 433 | );\r |
| 434 | \r |
| 435 | VOID\r |
| 436 | EFIAPI\r |
| 437 | ArmInstructionSynchronizationBarrier (\r |
| 438 | VOID\r |
| 439 | );\r |
| 440 | \r |
| 441 | VOID\r |
| 442 | EFIAPI\r |
| 443 | ArmWriteVBar (\r |
| 444 | IN UINT32 VectorBase\r |
| 445 | );\r |
| 446 | \r |
| 447 | UINT32\r |
| 448 | EFIAPI\r |
| 449 | ArmReadVBar (\r |
| 450 | VOID\r |
| 451 | );\r |
| 452 | \r |
| 453 | VOID\r |
| 454 | EFIAPI\r |
| 455 | ArmWriteAuxCr (\r |
| 456 | IN UINT32 Bit\r |
| 457 | );\r |
| 458 | \r |
| 459 | UINT32\r |
| 460 | EFIAPI\r |
| 461 | ArmReadAuxCr (\r |
| 462 | VOID\r |
| 463 | );\r |
| 464 | \r |
| 465 | VOID\r |
| 466 | EFIAPI\r |
| 467 | ArmSetAuxCrBit (\r |
| 468 | IN UINT32 Bits\r |
| 469 | );\r |
| 470 | \r |
| 471 | VOID\r |
| 472 | EFIAPI\r |
| 473 | ArmUnsetAuxCrBit (\r |
| 474 | IN UINT32 Bits\r |
| 475 | );\r |
| 476 | \r |
| 477 | VOID\r |
| 478 | EFIAPI\r |
| 479 | ArmCallSEV (\r |
| 480 | VOID\r |
| 481 | );\r |
| 482 | \r |
| 483 | VOID\r |
| 484 | EFIAPI\r |
| 485 | ArmCallWFE (\r |
| 486 | VOID\r |
| 487 | );\r |
| 488 | \r |
| 489 | VOID\r |
| 490 | EFIAPI\r |
| 491 | ArmCallWFI (\r |
| 492 | VOID\r |
| 493 | );\r |
| 494 | \r |
| 495 | UINTN\r |
| 496 | EFIAPI\r |
| 497 | ArmReadMpidr (\r |
| 498 | VOID\r |
| 499 | );\r |
| 500 | \r |
| 501 | UINT32\r |
| 502 | EFIAPI\r |
| 503 | ArmReadCpacr (\r |
| 504 | VOID\r |
| 505 | );\r |
| 506 | \r |
| 507 | VOID\r |
| 508 | EFIAPI\r |
| 509 | ArmWriteCpacr (\r |
| 510 | IN UINT32 Access\r |
| 511 | );\r |
| 512 | \r |
| 513 | VOID\r |
| 514 | EFIAPI\r |
| 515 | ArmEnableVFP (\r |
| 516 | VOID\r |
| 517 | );\r |
| 518 | \r |
| 519 | UINT32\r |
| 520 | EFIAPI\r |
| 521 | ArmReadNsacr (\r |
| 522 | VOID\r |
| 523 | );\r |
| 524 | \r |
| 525 | VOID\r |
| 526 | EFIAPI\r |
| 527 | ArmWriteNsacr (\r |
| 528 | IN UINT32 SetWayFormat\r |
| 529 | );\r |
| 530 | \r |
| 531 | UINT32\r |
| 532 | EFIAPI\r |
| 533 | ArmReadScr (\r |
| 534 | VOID\r |
| 535 | );\r |
| 536 | \r |
| 537 | VOID\r |
| 538 | EFIAPI\r |
| 539 | ArmWriteScr (\r |
| 540 | IN UINT32 SetWayFormat\r |
| 541 | );\r |
| 542 | \r |
| 543 | UINT32\r |
| 544 | EFIAPI\r |
| 545 | ArmReadMVBar (\r |
| 546 | VOID\r |
| 547 | );\r |
| 548 | \r |
| 549 | VOID\r |
| 550 | EFIAPI\r |
| 551 | ArmWriteMVBar (\r |
| 552 | IN UINT32 VectorMonitorBase\r |
| 553 | );\r |
| 554 | \r |
| 555 | UINT32\r |
| 556 | EFIAPI\r |
| 557 | ArmReadSctlr (\r |
| 558 | VOID\r |
| 559 | );\r |
| 560 | \r |
| 561 | #endif // __ARM_LIB__\r |
projects / mirror_edk2.git / blame