projects / mirror_edk2.git / blame
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|---|---|---|
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1 | /** @file\r |
| 2 | \r | |
| 3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r | |
| 01674afd | 4 | Portions copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>\r |
| 25402f5d HL |
5 | \r |
| 6 | This program and the accompanying materials\r | |
| 7 | are licensed and made available under the terms and conditions of the BSD License\r | |
| 8 | which accompanies this distribution. The full text of the license may be found at\r | |
| 9 | http://opensource.org/licenses/bsd-license.php\r | |
| 10 | \r | |
| 11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 13 | \r | |
| 14 | **/\r | |
| 15 | \r | |
| 16 | #include <Uefi.h>\r | |
| 17 | #include <Chipset/AArch64.h>\r | |
| 18 | #include <Library/ArmLib.h>\r | |
| 19 | #include <Library/BaseLib.h>\r | |
| 20 | #include <Library/IoLib.h>\r | |
| 21 | #include "AArch64Lib.h"\r | |
| 22 | #include "ArmLibPrivate.h"\r | |
| 23 | \r | |
| 25402f5d HL |
24 | UINTN\r |
| 25 | EFIAPI\r | |
| 26 | ArmDataCacheLineLength (\r | |
| 27 | VOID\r | |
| 28 | )\r | |
| 29 | {\r | |
| 30 | UINT32 CCSIDR = ReadCCSIDR (0) & 7;\r | |
| 31 | \r | |
| 32 | // * 4 converts to bytes\r | |
| 33 | return (1 << (CCSIDR + 2)) * 4;\r | |
| 34 | }\r | |
| 35 | \r | |
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36 | UINTN\r |
| 37 | EFIAPI\r | |
| 38 | ArmInstructionCacheLineLength (\r | |
| 39 | VOID\r | |
| 40 | )\r | |
| 41 | {\r | |
| 42 | UINT32 CCSIDR = ReadCCSIDR (1) & 7;\r | |
| 43 | \r | |
| 44 | // * 4 converts to bytes\r | |
| 45 | return (1 << (CCSIDR + 2)) * 4;\r | |
| 46 | }\r | |
| 47 | \r | |
| 48 | \r | |
| 49 | VOID\r | |
| 50 | AArch64DataCacheOperation (\r | |
| 51 | IN AARCH64_CACHE_OPERATION DataCacheOperation\r | |
| 52 | )\r | |
| 53 | {\r | |
| 54 | UINTN SavedInterruptState;\r | |
| 55 | \r | |
| 56 | SavedInterruptState = ArmGetInterruptState ();\r | |
| 57 | ArmDisableInterrupts();\r | |
| 58 | \r | |
| 59 | AArch64AllDataCachesOperation (DataCacheOperation);\r | |
| 60 | \r | |
| 61 | ArmDrainWriteBuffer ();\r | |
| 62 | \r | |
| 63 | if (SavedInterruptState) {\r | |
| 64 | ArmEnableInterrupts ();\r | |
| 65 | }\r | |
| 66 | }\r | |
| 67 | \r | |
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68 | VOID\r |
| 69 | EFIAPI\r | |
| 70 | ArmInvalidateDataCache (\r | |
| 71 | VOID\r | |
| 72 | )\r | |
| 73 | {\r | |
| 01674afd | 74 | ArmDrainWriteBuffer ();\r |
| 25402f5d HL |
75 | AArch64DataCacheOperation (ArmInvalidateDataCacheEntryBySetWay);\r |
| 76 | }\r | |
| 77 | \r | |
| 78 | VOID\r | |
| 79 | EFIAPI\r | |
| 80 | ArmCleanInvalidateDataCache (\r | |
| 81 | VOID\r | |
| 82 | )\r | |
| 83 | {\r | |
| 01674afd | 84 | ArmDrainWriteBuffer ();\r |
| 25402f5d HL |
85 | AArch64DataCacheOperation (ArmCleanInvalidateDataCacheEntryBySetWay);\r |
| 86 | }\r | |
| 87 | \r | |
| 88 | VOID\r | |
| 89 | EFIAPI\r | |
| 90 | ArmCleanDataCache (\r | |
| 91 | VOID\r | |
| 92 | )\r | |
| 93 | {\r | |
| 01674afd | 94 | ArmDrainWriteBuffer ();\r |
| 25402f5d HL |
95 | AArch64DataCacheOperation (ArmCleanDataCacheEntryBySetWay);\r |
| 96 | }\r |