ArmPkg/ArmLib: don't invalidate entire I-cache on range operation

[mirror_edk2.git] / ArmPkg / Library / ArmLib / AArch64 / AArch64Support.S

#------------------------------------------------------------------------------\r
#\r
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
# which accompanies this distribution.  The full text of the license may be found at\r
# http://opensource.org/licenses/bsd-license.php\r
#\r
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
#\r
#------------------------------------------------------------------------------\r
\r
#include <Chipset/AArch64.h>\r
#include <AsmMacroIoLibV8.h>\r
\r
.text\r
.align 3\r
\r
GCC_ASM_EXPORT (ArmInvalidateInstructionCache)\r
GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA)\r
GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA)\r
GCC_ASM_EXPORT (ArmCleanDataCacheEntryToPoUByMVA)\r
GCC_ASM_EXPORT (ArmInvalidateInstructionCacheEntryToPoUByMVA)\r
GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA)\r
GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay)\r
GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay)\r
GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryBySetWay)\r
GCC_ASM_EXPORT (ArmEnableMmu)\r
GCC_ASM_EXPORT (ArmDisableMmu)\r
GCC_ASM_EXPORT (ArmDisableCachesAndMmu)\r
GCC_ASM_EXPORT (ArmMmuEnabled)\r
GCC_ASM_EXPORT (ArmEnableDataCache)\r
GCC_ASM_EXPORT (ArmDisableDataCache)\r
GCC_ASM_EXPORT (ArmEnableInstructionCache)\r
GCC_ASM_EXPORT (ArmDisableInstructionCache)\r
GCC_ASM_EXPORT (ArmDisableAlignmentCheck)\r
GCC_ASM_EXPORT (ArmEnableAlignmentCheck)\r
GCC_ASM_EXPORT (ArmEnableBranchPrediction)\r
GCC_ASM_EXPORT (ArmDisableBranchPrediction)\r
GCC_ASM_EXPORT (AArch64AllDataCachesOperation)\r
GCC_ASM_EXPORT (ArmDataMemoryBarrier)\r
GCC_ASM_EXPORT (ArmDataSynchronizationBarrier)\r
GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)\r
GCC_ASM_EXPORT (ArmWriteVBar)\r
GCC_ASM_EXPORT (ArmReadVBar)\r
GCC_ASM_EXPORT (ArmEnableVFP)\r
GCC_ASM_EXPORT (ArmCallWFI)\r
GCC_ASM_EXPORT (ArmReadMpidr)\r
GCC_ASM_EXPORT (ArmReadTpidrurw)\r
GCC_ASM_EXPORT (ArmWriteTpidrurw)\r
GCC_ASM_EXPORT (ArmIsArchTimerImplemented)\r
GCC_ASM_EXPORT (ArmReadIdPfr0)\r
GCC_ASM_EXPORT (ArmReadIdPfr1)\r
GCC_ASM_EXPORT (ArmWriteHcr)\r
GCC_ASM_EXPORT (ArmReadHcr)\r
GCC_ASM_EXPORT (ArmReadCurrentEL)\r
GCC_ASM_EXPORT (ArmReplaceLiveTranslationEntry)\r
GCC_ASM_EXPORT (ArmReplaceLiveTranslationEntrySize)\r
\r
.set CTRL_M_BIT,      (1 << 0)\r
.set CTRL_A_BIT,      (1 << 1)\r
.set CTRL_C_BIT,      (1 << 2)\r
.set CTRL_I_BIT,      (1 << 12)\r
.set CTRL_V_BIT,      (1 << 12)\r
.set CPACR_VFP_BITS,  (3 << 20)\r
\r
ASM_PFX(ArmInvalidateDataCacheEntryByMVA):\r
  dc      ivac, x0    // Invalidate single data cache line\r
  ret\r
\r
\r
ASM_PFX(ArmCleanDataCacheEntryByMVA):\r
  dc      cvac, x0    // Clean single data cache line\r
  ret\r
\r
\r
ASM_PFX(ArmCleanDataCacheEntryToPoUByMVA):\r
  dc      cvau, x0    // Clean single data cache line to PoU\r
  ret\r
\r
ASM_PFX(ArmInvalidateInstructionCacheEntryToPoUByMVA):\r
  ic      ivau, x0    // Invalidate single instruction cache line to PoU\r
  ret\r
\r
\r
ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):\r
  dc      civac, x0   // Clean and invalidate single data cache line\r
  ret\r
\r
\r
ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):\r
  dc      isw, x0     // Invalidate this line\r
  ret\r
\r
\r
ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):\r
  dc      cisw, x0    // Clean and Invalidate this line\r
  ret\r
\r
\r
ASM_PFX(ArmCleanDataCacheEntryBySetWay):\r
  dc      csw, x0     // Clean this line\r
  ret\r
\r
\r
ASM_PFX(ArmInvalidateInstructionCache):\r
  ic      iallu       // Invalidate entire instruction cache\r
  dsb     sy\r
  isb\r
  ret\r
\r
\r
ASM_PFX(ArmEnableMmu):\r
   EL1_OR_EL2_OR_EL3(x1)\r
1: mrs     x0, sctlr_el1       // Read System control register EL1\r
   b       4f\r
2: mrs     x0, sctlr_el2       // Read System control register EL2\r
   b       4f\r
3: mrs     x0, sctlr_el3       // Read System control register EL3\r
4: orr     x0, x0, #CTRL_M_BIT // Set MMU enable bit\r
   EL1_OR_EL2_OR_EL3(x1)\r
1: tlbi    vmalle1\r
   dsb     nsh\r
   isb\r
   msr     sctlr_el1, x0       // Write back\r
   b       4f\r
2: tlbi    alle2\r
   dsb     nsh\r
   isb\r
   msr     sctlr_el2, x0       // Write back\r
   b       4f\r
3: tlbi    alle3\r
   dsb     nsh\r
   isb\r
   msr     sctlr_el3, x0       // Write back\r
4: isb\r
   ret\r
\r
\r
ASM_PFX(ArmDisableMmu):\r
   EL1_OR_EL2_OR_EL3(x1)\r
1: mrs     x0, sctlr_el1        // Read System Control Register EL1\r
   b       4f\r
2: mrs     x0, sctlr_el2        // Read System Control Register EL2\r
   b       4f\r
3: mrs     x0, sctlr_el3        // Read System Control Register EL3\r
4: and     x0, x0, #~CTRL_M_BIT  // Clear MMU enable bit\r
   EL1_OR_EL2_OR_EL3(x1)\r
1: msr     sctlr_el1, x0        // Write back\r
   tlbi    vmalle1\r
   b       4f\r
2: msr     sctlr_el2, x0        // Write back\r
   tlbi    alle2\r
   b       4f\r
3: msr     sctlr_el3, x0        // Write back\r
   tlbi    alle3\r
4: dsb     sy\r
   isb\r
   ret\r
\r
\r
ASM_PFX(ArmDisableCachesAndMmu):\r
   EL1_OR_EL2_OR_EL3(x1)\r
1: mrs     x0, sctlr_el1        // Get control register EL1\r
   b       4f\r
2: mrs     x0, sctlr_el2        // Get control register EL2\r
   b       4f\r
3: mrs     x0, sctlr_el3        // Get control register EL3\r
4: mov     x1, #~(CTRL_M_BIT | CTRL_C_BIT | CTRL_I_BIT)  // Disable MMU, D & I caches\r
   and     x0, x0, x1\r
   EL1_OR_EL2_OR_EL3(x1)\r
1: msr     sctlr_el1, x0        // Write back control register\r
   b       4f\r
2: msr     sctlr_el2, x0        // Write back control register\r
   b       4f\r
3: msr     sctlr_el3, x0        // Write back control register\r
4: dsb     sy\r
   isb\r
   ret\r
\r
\r
ASM_PFX(ArmMmuEnabled):\r
   EL1_OR_EL2_OR_EL3(x1)\r
1: mrs     x0, sctlr_el1        // Get control register EL1\r
   b       4f\r
2: mrs     x0, sctlr_el2        // Get control register EL2\r
   b       4f\r
3: mrs     x0, sctlr_el3        // Get control register EL3\r
4: and     x0, x0, #CTRL_M_BIT\r
   ret\r
\r
\r
ASM_PFX(ArmEnableDataCache):\r
   EL1_OR_EL2_OR_EL3(x1)\r
1: mrs     x0, sctlr_el1        // Get control register EL1\r
   b       4f\r
2: mrs     x0, sctlr_el2        // Get control register EL2\r
   b       4f\r
3: mrs     x0, sctlr_el3        // Get control register EL3\r
4: orr     x0, x0, #CTRL_C_BIT  // Set C bit\r
   EL1_OR_EL2_OR_EL3(x1)\r
1: msr     sctlr_el1, x0        // Write back control register\r
   b       4f\r
2: msr     sctlr_el2, x0        // Write back control register\r
   b       4f\r
3: msr     sctlr_el3, x0        // Write back control register\r
4: dsb     sy\r
   isb\r
   ret\r
\r
\r
ASM_PFX(ArmDisableDataCache):\r
   EL1_OR_EL2_OR_EL3(x1)\r
1: mrs     x0, sctlr_el1        // Get control register EL1\r
   b       4f\r
2: mrs     x0, sctlr_el2        // Get control register EL2\r
   b       4f\r
3: mrs     x0, sctlr_el3        // Get control register EL3\r
4: and     x0, x0, #~CTRL_C_BIT  // Clear C bit\r
   EL1_OR_EL2_OR_EL3(x1)\r
1: msr     sctlr_el1, x0        // Write back control register\r
   b       4f\r
2: msr     sctlr_el2, x0        // Write back control register\r
   b       4f\r
3: msr     sctlr_el3, x0        // Write back control register\r
4: dsb     sy\r
   isb\r
   ret\r
\r
\r
ASM_PFX(ArmEnableInstructionCache):\r
   EL1_OR_EL2_OR_EL3(x1)\r
1: mrs     x0, sctlr_el1        // Get control register EL1\r
   b       4f\r
2: mrs     x0, sctlr_el2        // Get control register EL2\r
   b       4f\r
3: mrs     x0, sctlr_el3        // Get control register EL3\r
4: orr     x0, x0, #CTRL_I_BIT  // Set I bit\r
   EL1_OR_EL2_OR_EL3(x1)\r
1: msr     sctlr_el1, x0        // Write back control register\r
   b       4f\r
2: msr     sctlr_el2, x0        // Write back control register\r
   b       4f\r
3: msr     sctlr_el3, x0        // Write back control register\r
4: dsb     sy\r
   isb\r
   ret\r
\r
\r
ASM_PFX(ArmDisableInstructionCache):\r
   EL1_OR_EL2_OR_EL3(x1)\r
1: mrs     x0, sctlr_el1        // Get control register EL1\r
   b       4f\r
2: mrs     x0, sctlr_el2        // Get control register EL2\r
   b       4f\r
3: mrs     x0, sctlr_el3        // Get control register EL3\r
4: and     x0, x0, #~CTRL_I_BIT  // Clear I bit\r
   EL1_OR_EL2_OR_EL3(x1)\r
1: msr     sctlr_el1, x0        // Write back control register\r
   b       4f\r
2: msr     sctlr_el2, x0        // Write back control register\r
   b       4f\r
3: msr     sctlr_el3, x0        // Write back control register\r
4: dsb     sy\r
   isb\r
   ret\r
\r
\r
ASM_PFX(ArmEnableAlignmentCheck):\r
   EL1_OR_EL2(x1)\r
1: mrs     x0, sctlr_el1        // Get control register EL1\r
   b       3f\r
2: mrs     x0, sctlr_el2        // Get control register EL2\r
3: orr     x0, x0, #CTRL_A_BIT  // Set A (alignment check) bit\r
   EL1_OR_EL2(x1)\r
1: msr     sctlr_el1, x0        // Write back control register\r
   b       3f\r
2: msr     sctlr_el2, x0        // Write back control register\r
3: dsb     sy\r
   isb\r
   ret\r
\r
\r
ASM_PFX(ArmDisableAlignmentCheck):\r
   EL1_OR_EL2_OR_EL3(x1)\r
1: mrs     x0, sctlr_el1        // Get control register EL1\r
   b       4f\r
2: mrs     x0, sctlr_el2        // Get control register EL2\r
   b       4f\r
3: mrs     x0, sctlr_el3        // Get control register EL3\r
4: and     x0, x0, #~CTRL_A_BIT  // Clear A (alignment check) bit\r
   EL1_OR_EL2_OR_EL3(x1)\r
1: msr     sctlr_el1, x0        // Write back control register\r
   b       4f\r
2: msr     sctlr_el2, x0        // Write back control register\r
   b       4f\r
3: msr     sctlr_el3, x0        // Write back control register\r
4: dsb     sy\r
   isb\r
   ret\r
\r
\r
// Always turned on in AArch64. Else implementation specific. Leave in for C compatibility for now\r
ASM_PFX(ArmEnableBranchPrediction):\r
  ret\r
\r
\r
// Always turned on in AArch64. Else implementation specific. Leave in for C compatibility for now.\r
ASM_PFX(ArmDisableBranchPrediction):\r
  ret\r
\r
\r
ASM_PFX(AArch64AllDataCachesOperation):\r
// We can use regs 0-7 and 9-15 without having to save/restore.\r
// Save our link register on the stack. - The stack must always be quad-word aligned\r
  str   x30, [sp, #-16]!\r
  mov   x1, x0                  // Save Function call in x1\r
  mrs   x6, clidr_el1           // Read EL1 CLIDR\r
  and   x3, x6, #0x7000000      // Mask out all but Level of Coherency (LoC)\r
  lsr   x3, x3, #23             // Left align cache level value - the level is shifted by 1 to the\r
                                // right to ease the access to CSSELR and the Set/Way operation.\r
  cbz   x3, L_Finished          // No need to clean if LoC is 0\r
  mov   x10, #0                 // Start clean at cache level 0\r
\r
Loop1:\r
  add   x2, x10, x10, lsr #1    // Work out 3x cachelevel for cache info\r
  lsr   x12, x6, x2             // bottom 3 bits are the Cache type for this level\r
  and   x12, x12, #7            // get those 3 bits alone\r
  cmp   x12, #2                 // what cache at this level?\r
  b.lt  L_Skip                  // no cache or only instruction cache at this level\r
  msr   csselr_el1, x10         // write the Cache Size selection register with current level (CSSELR)\r
  isb                           // isb to sync the change to the CacheSizeID reg\r
  mrs   x12, ccsidr_el1         // reads current Cache Size ID register (CCSIDR)\r
  and   x2, x12, #0x7           // extract the line length field\r
  add   x2, x2, #4              // add 4 for the line length offset (log2 16 bytes)\r
  mov   x4, #0x400\r
  sub   x4, x4, #1\r
  and   x4, x4, x12, lsr #3     // x4 is the max number on the way size (right aligned)\r
  clz   w5, w4                  // w5 is the bit position of the way size increment\r
  mov   x7, #0x00008000\r
  sub   x7, x7, #1\r
  and   x7, x7, x12, lsr #13    // x7 is the max number of the index size (right aligned)\r
\r
Loop2:\r
  mov   x9, x4                  // x9 working copy of the max way size (right aligned)\r
\r
Loop3:\r
  lsl   x11, x9, x5\r
  orr   x0, x10, x11            // factor in the way number and cache number\r
  lsl   x11, x7, x2\r
  orr   x0, x0, x11             // factor in the index number\r
\r
  blr   x1                      // Goto requested cache operation\r
\r
  subs  x9, x9, #1              // decrement the way number\r
  b.ge  Loop3\r
  subs  x7, x7, #1              // decrement the index\r
  b.ge  Loop2\r
L_Skip:\r
  add   x10, x10, #2            // increment the cache number\r
  cmp   x3, x10\r
  b.gt  Loop1\r
\r
L_Finished:\r
  dsb   sy\r
  isb\r
  ldr   x30, [sp], #0x10\r
  ret\r
\r
\r
ASM_PFX(ArmDataMemoryBarrier):\r
  dmb   sy\r
  ret\r
\r
\r
ASM_PFX(ArmDataSynchronizationBarrier):\r
  dsb   sy\r
  ret\r
\r
\r
ASM_PFX(ArmInstructionSynchronizationBarrier):\r
  isb\r
  ret\r
\r
\r
ASM_PFX(ArmWriteVBar):\r
   EL1_OR_EL2_OR_EL3(x1)\r
1: msr   vbar_el1, x0            // Set the Address of the EL1 Vector Table in the VBAR register\r
   b     4f\r
2: msr   vbar_el2, x0            // Set the Address of the EL2 Vector Table in the VBAR register\r
   b     4f\r
3: msr   vbar_el3, x0            // Set the Address of the EL3 Vector Table in the VBAR register\r
4: isb\r
   ret\r
\r
ASM_PFX(ArmReadVBar):\r
   EL1_OR_EL2_OR_EL3(x1)\r
1: mrs   x0, vbar_el1            // Set the Address of the EL1 Vector Table in the VBAR register\r
   ret\r
2: mrs   x0, vbar_el2            // Set the Address of the EL2 Vector Table in the VBAR register\r
   ret\r
3: mrs   x0, vbar_el3            // Set the Address of the EL3 Vector Table in the VBAR register\r
   ret\r
\r
\r
ASM_PFX(ArmEnableVFP):\r
  // Check whether floating-point is implemented in the processor.\r
  mov   x1, x30                 // Save LR\r
  bl    ArmReadIdPfr0           // Read EL1 Processor Feature Register (PFR0)\r
  mov   x30, x1                 // Restore LR\r
  ands  x0, x0, #AARCH64_PFR0_FP// Extract bits indicating VFP implementation\r
  cmp   x0, #0                  // VFP is implemented if '0'.\r
  b.ne  4f                      // Exit if VFP not implemented.\r
  // FVP is implemented.\r
  // Make sure VFP exceptions are not trapped (to any exception level).\r
  mrs   x0, cpacr_el1           // Read EL1 Coprocessor Access Control Register (CPACR)\r
  orr   x0, x0, #CPACR_VFP_BITS // Disable FVP traps to EL1\r
  msr   cpacr_el1, x0           // Write back EL1 Coprocessor Access Control Register (CPACR)\r
  mov   x1, #AARCH64_CPTR_TFP   // TFP Bit for trapping VFP Exceptions\r
  EL1_OR_EL2_OR_EL3(x2)\r
1:ret                           // Not configurable in EL1\r
2:mrs   x0, cptr_el2            // Disable VFP traps to EL2\r
  bic   x0, x0, x1\r
  msr   cptr_el2, x0\r
  ret\r
3:mrs   x0, cptr_el3            // Disable VFP traps to EL3\r
  bic   x0, x0, x1\r
  msr   cptr_el3, x0\r
4:ret\r
\r
\r
ASM_PFX(ArmCallWFI):\r
  wfi\r
  ret\r
\r
\r
ASM_PFX(ArmReadMpidr):\r
  mrs   x0, mpidr_el1           // read EL1 MPIDR\r
  ret\r
\r
\r
// Keep old function names for C compatibilty for now. Change later?\r
ASM_PFX(ArmReadTpidrurw):\r
  mrs   x0, tpidr_el0           // read tpidr_el0 (v7 TPIDRURW) -> (v8 TPIDR_EL0)\r
  ret\r
\r
\r
// Keep old function names for C compatibilty for now. Change later?\r
ASM_PFX(ArmWriteTpidrurw):\r
  msr   tpidr_el0, x0           // write tpidr_el0 (v7 TPIDRURW) -> (v8 TPIDR_EL0)\r
  ret\r
\r
\r
// Arch timers are mandatory on AArch64\r
ASM_PFX(ArmIsArchTimerImplemented):\r
  mov   x0, #1\r
  ret\r
\r
\r
ASM_PFX(ArmReadIdPfr0):\r
  mrs   x0, id_aa64pfr0_el1   // Read ID_AA64PFR0 Register\r
  ret\r
\r
\r
// Q: id_aa64pfr1_el1 not defined yet. What does this funtion want to access?\r
// A: used to setup arch timer. Check if we have security extensions, permissions to set stuff.\r
//    See: ArmPkg/Library/ArmArchTimerLib/AArch64/ArmArchTimerLib.c\r
//    Not defined yet, but stick in here for now, should read all zeros.\r
ASM_PFX(ArmReadIdPfr1):\r
  mrs   x0, id_aa64pfr1_el1   // Read ID_PFR1 Register\r
  ret\r
\r
// VOID ArmWriteHcr(UINTN Hcr)\r
ASM_PFX(ArmWriteHcr):\r
  msr   hcr_el2, x0        // Write the passed HCR value\r
  ret\r
\r
// UINTN ArmReadHcr(VOID)\r
ASM_PFX(ArmReadHcr):\r
  mrs   x0, hcr_el2\r
  ret\r
\r
// UINTN ArmReadCurrentEL(VOID)\r
ASM_PFX(ArmReadCurrentEL):\r
  mrs   x0, CurrentEL\r
  ret\r
\r
\r
  .macro __replace_entry, el\r
\r
  // disable the MMU\r
  mrs   x8, sctlr_el\el\r
  bic   x9, x8, #CTRL_M_BIT\r
  msr   sctlr_el\el, x9\r
  isb\r
\r
  // write updated entry\r
  str   x1, [x0]\r
\r
  // invalidate again to get rid of stale clean cachelines that may\r
  // have been filled speculatively since the last invalidate\r
  dmb   sy\r
  dc    ivac, x0\r
\r
  // flush the TLBs\r
  .if   \el == 1\r
  tlbi  vmalle1\r
  .else\r
  tlbi  alle\el\r
  .endif\r
  dsb   sy\r
\r
  // re-enable the MMU\r
  msr   sctlr_el\el, x8\r
  isb\r
  .endm\r
\r
//VOID\r
//ArmReplaceLiveTranslationEntry (\r
//  IN  UINT64  *Entry,\r
//  IN  UINT64  Value\r
//  )\r
ASM_PFX(ArmReplaceLiveTranslationEntry):\r
\r
  // disable interrupts\r
  mrs   x2, daif\r
  msr   daifset, #0xf\r
  isb\r
\r
  // clean and invalidate first so that we don't clobber\r
  // adjacent entries that are dirty in the caches\r
  dc    civac, x0\r
  dsb   ish\r
\r
  EL1_OR_EL2_OR_EL3(x3)\r
1:__replace_entry 1\r
  b     4f\r
2:__replace_entry 2\r
  b     4f\r
3:__replace_entry 3\r
\r
4:msr   daif, x2\r
  ret\r
\r
ASM_PFX(ArmReplaceLiveTranslationEntrySize):\r
  .long   . - ArmReplaceLiveTranslationEntry\r
\r
ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r