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Commit | Line | Data |
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93deac7e HL |
1 | #------------------------------------------------------------------------------\r |
2 | #\r | |
3 | # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r | |
07783fdd | 4 | # Copyright (c) 2011 - 2016, ARM Limited. All rights reserved.\r |
0efaa42f | 5 | # Copyright (c) 2016, Linaro Limited. All rights reserved.\r |
93deac7e | 6 | #\r |
4059386c | 7 | # SPDX-License-Identifier: BSD-2-Clause-Patent\r |
93deac7e HL |
8 | #\r |
9 | #------------------------------------------------------------------------------\r | |
10 | \r | |
11 | #include <AsmMacroIoLibV8.h>\r | |
12 | \r | |
4af3dd80 EC |
13 | .set DAIF_RD_FIQ_BIT, (1 << 6)\r |
14 | .set DAIF_RD_IRQ_BIT, (1 << 7)\r | |
93deac7e | 15 | \r |
0efaa42f | 16 | ASM_FUNC(ArmReadMidr)\r |
93deac7e HL |
17 | mrs x0, midr_el1 // Read from Main ID Register (MIDR)\r |
18 | ret\r | |
19 | \r | |
0efaa42f | 20 | ASM_FUNC(ArmCacheInfo)\r |
93deac7e HL |
21 | mrs x0, ctr_el0 // Read from Cache Type Regiter (CTR)\r |
22 | ret\r | |
23 | \r | |
0efaa42f | 24 | ASM_FUNC(ArmGetInterruptState)\r |
93deac7e | 25 | mrs x0, daif\r |
4af3dd80 EC |
26 | tst w0, #DAIF_RD_IRQ_BIT // Check if IRQ is enabled. Enabled if 0 (Z=1)\r |
27 | cset w0, eq // if Z=1 return 1, else 0\r | |
93deac7e HL |
28 | ret\r |
29 | \r | |
0efaa42f | 30 | ASM_FUNC(ArmGetFiqState)\r |
93deac7e | 31 | mrs x0, daif\r |
4af3dd80 EC |
32 | tst w0, #DAIF_RD_FIQ_BIT // Check if FIQ is enabled. Enabled if 0 (Z=1)\r |
33 | cset w0, eq // if Z=1 return 1, else 0\r | |
93deac7e HL |
34 | ret\r |
35 | \r | |
0efaa42f | 36 | ASM_FUNC(ArmWriteCpacr)\r |
93deac7e HL |
37 | msr cpacr_el1, x0 // Coprocessor Access Control Reg (CPACR)\r |
38 | ret\r | |
39 | \r | |
0efaa42f | 40 | ASM_FUNC(ArmWriteAuxCr)\r |
93deac7e HL |
41 | EL1_OR_EL2(x1)\r |
42 | 1:msr actlr_el1, x0 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3\r | |
27995cd5 | 43 | ret\r |
93deac7e | 44 | 2:msr actlr_el2, x0 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3\r |
27995cd5 | 45 | ret\r |
93deac7e | 46 | \r |
0efaa42f | 47 | ASM_FUNC(ArmReadAuxCr)\r |
93deac7e HL |
48 | EL1_OR_EL2(x1)\r |
49 | 1:mrs x0, actlr_el1 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3\r | |
27995cd5 | 50 | ret\r |
93deac7e | 51 | 2:mrs x0, actlr_el2 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3\r |
27995cd5 | 52 | ret\r |
93deac7e | 53 | \r |
0efaa42f | 54 | ASM_FUNC(ArmSetTTBR0)\r |
93deac7e HL |
55 | EL1_OR_EL2_OR_EL3(x1)\r |
56 | 1:msr ttbr0_el1, x0 // Translation Table Base Reg 0 (TTBR0)\r | |
57 | b 4f\r | |
58 | 2:msr ttbr0_el2, x0 // Translation Table Base Reg 0 (TTBR0)\r | |
59 | b 4f\r | |
60 | 3:msr ttbr0_el3, x0 // Translation Table Base Reg 0 (TTBR0)\r | |
61 | 4:isb\r | |
62 | ret\r | |
63 | \r | |
0efaa42f | 64 | ASM_FUNC(ArmGetTTBR0BaseAddress)\r |
93deac7e HL |
65 | EL1_OR_EL2(x1)\r |
66 | 1:mrs x0, ttbr0_el1\r | |
67 | b 3f\r | |
68 | 2:mrs x0, ttbr0_el2\r | |
0efaa42f | 69 | 3:and x0, x0, 0xFFFFFFFFFFFF /* Look at bottom 48 bits */\r |
93deac7e HL |
70 | isb\r |
71 | ret\r | |
72 | \r | |
0efaa42f | 73 | ASM_FUNC(ArmGetTCR)\r |
93deac7e HL |
74 | EL1_OR_EL2_OR_EL3(x1)\r |
75 | 1:mrs x0, tcr_el1\r | |
76 | b 4f\r | |
77 | 2:mrs x0, tcr_el2\r | |
78 | b 4f\r | |
79 | 3:mrs x0, tcr_el3\r | |
80 | 4:isb\r | |
81 | ret\r | |
82 | \r | |
0efaa42f | 83 | ASM_FUNC(ArmSetTCR)\r |
93deac7e HL |
84 | EL1_OR_EL2_OR_EL3(x1)\r |
85 | 1:msr tcr_el1, x0\r | |
86 | b 4f\r | |
87 | 2:msr tcr_el2, x0\r | |
88 | b 4f\r | |
89 | 3:msr tcr_el3, x0\r | |
90 | 4:isb\r | |
91 | ret\r | |
92 | \r | |
0efaa42f | 93 | ASM_FUNC(ArmGetMAIR)\r |
93deac7e HL |
94 | EL1_OR_EL2_OR_EL3(x1)\r |
95 | 1:mrs x0, mair_el1\r | |
96 | b 4f\r | |
97 | 2:mrs x0, mair_el2\r | |
98 | b 4f\r | |
99 | 3:mrs x0, mair_el3\r | |
100 | 4:isb\r | |
101 | ret\r | |
102 | \r | |
0efaa42f | 103 | ASM_FUNC(ArmSetMAIR)\r |
93deac7e HL |
104 | EL1_OR_EL2_OR_EL3(x1)\r |
105 | 1:msr mair_el1, x0\r | |
106 | b 4f\r | |
107 | 2:msr mair_el2, x0\r | |
108 | b 4f\r | |
109 | 3:msr mair_el3, x0\r | |
110 | 4:isb\r | |
111 | ret\r | |
112 | \r | |
113 | \r | |
114 | //\r | |
115 | //VOID\r | |
116 | //ArmUpdateTranslationTableEntry (\r | |
117 | // IN VOID *TranslationTableEntry // X0\r | |
118 | // IN VOID *MVA // X1\r | |
119 | // );\r | |
0efaa42f | 120 | ASM_FUNC(ArmUpdateTranslationTableEntry)\r |
d5788777 AB |
121 | dsb nshst\r |
122 | lsr x1, x1, #12\r | |
93deac7e HL |
123 | EL1_OR_EL2_OR_EL3(x0)\r |
124 | 1: tlbi vaae1, x1 // TLB Invalidate VA , EL1\r | |
125 | b 4f\r | |
126 | 2: tlbi vae2, x1 // TLB Invalidate VA , EL2\r | |
127 | b 4f\r | |
128 | 3: tlbi vae3, x1 // TLB Invalidate VA , EL3\r | |
d5788777 | 129 | 4: dsb nsh\r |
93deac7e HL |
130 | isb\r |
131 | ret\r | |
132 | \r | |
0efaa42f | 133 | ASM_FUNC(ArmInvalidateTlb)\r |
93deac7e | 134 | EL1_OR_EL2_OR_EL3(x0)\r |
70f89c0b | 135 | 1: tlbi vmalle1\r |
93deac7e HL |
136 | b 4f\r |
137 | 2: tlbi alle2\r | |
138 | b 4f\r | |
139 | 3: tlbi alle3\r | |
140 | 4: dsb sy\r | |
141 | isb\r | |
142 | ret\r | |
143 | \r | |
0efaa42f | 144 | ASM_FUNC(ArmWriteCptr)\r |
93deac7e | 145 | msr cptr_el3, x0 // EL3 Coprocessor Trap Reg (CPTR)\r |
d6dc67ba | 146 | ret\r |
93deac7e | 147 | \r |
0efaa42f | 148 | ASM_FUNC(ArmWriteScr)\r |
93deac7e | 149 | msr scr_el3, x0 // Secure configuration register EL3\r |
b2d0e0c5 | 150 | isb\r |
93deac7e HL |
151 | ret\r |
152 | \r | |
0efaa42f | 153 | ASM_FUNC(ArmWriteMVBar)\r |
27995cd5 | 154 | msr vbar_el3, x0 // Exception Vector Base address for Monitor on EL3\r |
93deac7e HL |
155 | ret\r |
156 | \r | |
0efaa42f | 157 | ASM_FUNC(ArmCallWFE)\r |
93deac7e HL |
158 | wfe\r |
159 | ret\r | |
160 | \r | |
0efaa42f | 161 | ASM_FUNC(ArmCallSEV)\r |
93deac7e HL |
162 | sev\r |
163 | ret\r | |
164 | \r | |
0efaa42f | 165 | ASM_FUNC(ArmReadCpuActlr)\r |
52d44f77 OM |
166 | mrs x0, S3_1_c15_c2_0\r |
167 | ret\r | |
168 | \r | |
0efaa42f | 169 | ASM_FUNC(ArmWriteCpuActlr)\r |
52d44f77 OM |
170 | msr S3_1_c15_c2_0, x0\r |
171 | dsb sy\r | |
172 | isb\r | |
173 | ret\r | |
93deac7e | 174 | \r |
0efaa42f | 175 | ASM_FUNC(ArmReadSctlr)\r |
07783fdd SV |
176 | EL1_OR_EL2_OR_EL3(x1)\r |
177 | 1:mrs x0, sctlr_el1\r | |
178 | ret\r | |
179 | 2:mrs x0, sctlr_el2\r | |
180 | ret\r | |
181 | 3:mrs x0, sctlr_el3\r | |
182 | 4:ret\r | |
183 | \r | |
1e1d1697 MZ |
184 | ASM_FUNC(ArmWriteSctlr)\r |
185 | EL1_OR_EL2_OR_EL3(x1)\r | |
186 | 1:msr sctlr_el1, x0\r | |
187 | ret\r | |
188 | 2:msr sctlr_el2, x0\r | |
189 | ret\r | |
190 | 3:msr sctlr_el3, x0\r | |
191 | 4:ret\r | |
192 | \r | |
95d04ebc AB |
193 | ASM_FUNC(ArmGetPhysicalAddressBits)\r |
194 | mrs x0, id_aa64mmfr0_el1\r | |
195 | adr x1, .LPARanges\r | |
196 | and x0, x0, #0xf\r | |
197 | ldrb w0, [x1, x0]\r | |
198 | ret\r | |
199 | \r | |
200 | //\r | |
201 | // Bits 0..3 of the AA64MFR0_EL1 system register encode the size of the\r | |
202 | // physical address space support on this CPU:\r | |
203 | // 0 == 32 bits, 1 == 36 bits, etc etc\r | |
204 | // 7 and up are reserved\r | |
205 | //\r | |
206 | .LPARanges:\r | |
207 | .byte 32, 36, 40, 42, 44, 48, 52, 0\r | |
208 | .byte 0, 0, 0, 0, 0, 0, 0, 0\r | |
209 | \r | |
93deac7e | 210 | ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r |