projects / mirror_edk2.git / blame
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1 | #------------------------------------------------------------------------------\r |
| 2 | #\r | |
| 3 | # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r | |
| 4 | # Copyright (c) 2011 - 2013, ARM Limited. All rights reserved.\r | |
| 5 | #\r | |
| 6 | # This program and the accompanying materials\r | |
| 7 | # are licensed and made available under the terms and conditions of the BSD License\r | |
| 8 | # which accompanies this distribution. The full text of the license may be found at\r | |
| 9 | # http://opensource.org/licenses/bsd-license.php\r | |
| 10 | #\r | |
| 11 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 12 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 13 | #\r | |
| 14 | #------------------------------------------------------------------------------\r | |
| 15 | \r | |
| 16 | #include <AsmMacroIoLib.h>\r | |
| 17 | \r | |
| 18 | .text\r | |
| 19 | .align 3\r | |
| 20 | \r | |
| 21 | GCC_ASM_EXPORT (ArmIsMpCore)\r | |
| 22 | GCC_ASM_EXPORT (ArmEnableAsynchronousAbort)\r | |
| 23 | GCC_ASM_EXPORT (ArmDisableAsynchronousAbort)\r | |
| 24 | GCC_ASM_EXPORT (ArmEnableIrq)\r | |
| 25 | GCC_ASM_EXPORT (ArmDisableIrq)\r | |
| 26 | GCC_ASM_EXPORT (ArmEnableFiq)\r | |
| 27 | GCC_ASM_EXPORT (ArmDisableFiq)\r | |
| 28 | GCC_ASM_EXPORT (ArmEnableInterrupts)\r | |
| 29 | GCC_ASM_EXPORT (ArmDisableInterrupts)\r | |
| 30 | GCC_ASM_EXPORT (ArmDisableAllExceptions)\r | |
| 31 | GCC_ASM_EXPORT (ReadCCSIDR)\r | |
| 32 | GCC_ASM_EXPORT (ReadCLIDR)\r | |
| 33 | \r | |
| 34 | #------------------------------------------------------------------------------\r | |
| 35 | \r | |
| 36 | .set MPIDR_U_BIT, (30)\r | |
| 37 | .set MPIDR_U_MASK, (1 << MPIDR_U_BIT)\r | |
| 38 | .set DAIF_FIQ_BIT, (1 << 0)\r | |
| 39 | .set DAIF_IRQ_BIT, (1 << 1)\r | |
| 40 | .set DAIF_ABORT_BIT, (1 << 2)\r | |
| 41 | .set DAIF_DEBUG_BIT, (1 << 3)\r | |
| 42 | .set DAIF_INT_BITS, (DAIF_FIQ_BIT | DAIF_IRQ_BIT)\r | |
| 43 | .set DAIF_ALL, (DAIF_DEBUG_BIT | DAIF_ABORT_BIT | DAIF_INT_BITS)\r | |
| 44 | \r | |
| 45 | \r | |
| 46 | ASM_PFX(ArmIsMpCore):\r | |
| 47 | mrs x0, mpidr_el1 // Read EL1 Mutliprocessor Affinty Reg (MPIDR)\r | |
| 48 | and x0, x0, #MPIDR_U_MASK // U Bit clear, the processor is part of a multiprocessor system\r | |
| 49 | lsr x0, x0, #MPIDR_U_BIT\r | |
| 50 | eor x0, x0, #1\r | |
| 51 | ret\r | |
| 52 | \r | |
| 53 | \r | |
| 54 | ASM_PFX(ArmEnableAsynchronousAbort):\r | |
| 55 | msr daifclr, #DAIF_ABORT_BIT\r | |
| 56 | isb\r | |
| 57 | ret\r | |
| 58 | \r | |
| 59 | \r | |
| 60 | ASM_PFX(ArmDisableAsynchronousAbort):\r | |
| 61 | msr daifset, #DAIF_ABORT_BIT\r | |
| 62 | isb\r | |
| 63 | ret\r | |
| 64 | \r | |
| 65 | \r | |
| 66 | ASM_PFX(ArmEnableIrq):\r | |
| 67 | msr daifclr, #DAIF_IRQ_BIT\r | |
| 68 | isb\r | |
| 69 | ret\r | |
| 70 | \r | |
| 71 | \r | |
| 72 | ASM_PFX(ArmDisableIrq):\r | |
| 73 | msr daifset, #DAIF_IRQ_BIT\r | |
| 74 | isb\r | |
| 75 | ret\r | |
| 76 | \r | |
| 77 | \r | |
| 78 | ASM_PFX(ArmEnableFiq):\r | |
| 79 | msr daifclr, #DAIF_FIQ_BIT\r | |
| 80 | isb\r | |
| 81 | ret\r | |
| 82 | \r | |
| 83 | \r | |
| 84 | ASM_PFX(ArmDisableFiq):\r | |
| 85 | msr daifset, #DAIF_FIQ_BIT\r | |
| 86 | isb\r | |
| 87 | ret\r | |
| 88 | \r | |
| 89 | \r | |
| 90 | ASM_PFX(ArmEnableInterrupts):\r | |
| 91 | msr daifclr, #DAIF_INT_BITS\r | |
| 92 | isb\r | |
| 93 | ret\r | |
| 94 | \r | |
| 95 | \r | |
| 96 | ASM_PFX(ArmDisableInterrupts):\r | |
| 97 | msr daifset, #DAIF_INT_BITS\r | |
| 98 | isb\r | |
| 99 | ret\r | |
| 100 | \r | |
| 101 | \r | |
| 102 | ASM_PFX(ArmDisableAllExceptions):\r | |
| 103 | msr daifset, #DAIF_ALL\r | |
| 104 | isb\r | |
| 105 | ret\r | |
| 106 | \r | |
| 107 | \r | |
| 108 | // UINT32\r | |
| 109 | // ReadCCSIDR (\r | |
| 110 | // IN UINT32 CSSELR\r | |
| 111 | // )\r | |
| 112 | ASM_PFX(ReadCCSIDR):\r | |
| 113 | msr csselr_el1, x0 // Write Cache Size Selection Register (CSSELR)\r | |
| 114 | isb\r | |
| 115 | mrs x0, ccsidr_el1 // Read current Cache Size ID Register (CCSIDR)\r | |
| 116 | ret\r | |
| 117 | \r | |
| 118 | \r | |
| 119 | // UINT32\r | |
| 120 | // ReadCLIDR (\r | |
| 121 | // IN UINT32 CSSELR\r | |
| 122 | // )\r | |
| 123 | ASM_PFX(ReadCLIDR):\r | |
| 124 | mrs x0, clidr_el1 // Read Cache Level ID Register\r | |
| 125 | ret\r | |
| 126 | \r | |
| 127 | ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r |