ArmPkg: Made ArmConfigureMmu() returns a status code

[mirror_edk2.git] / ArmPkg / Library / ArmLib / Arm11 / Arm11LibMem.c

/** @file\r
\r
  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
  Copyright (c) 2011 - 2013, ARM Limited. All rights reserved.\r
  \r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#include <Chipset/ARM1176JZ-S.h>\r
#include <Library/ArmLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
\r
VOID\r
FillTranslationTable (\r
  IN  UINT32                        *TranslationTable,\r
  IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryRegion\r
  )\r
{\r
  UINT32  *Entry;\r
  UINTN   Sections;\r
  UINTN   Index;\r
  UINT32  Attributes;\r
  UINT32  PhysicalBase = MemoryRegion->PhysicalBase;\r
  \r
  switch (MemoryRegion->Attributes) {\r
    case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:\r
      Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(0);\r
      break;\r
    case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:\r
      Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0);\r
      break;\r
    case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:\r
      Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);\r
      break;\r
    case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:\r
      Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(1);\r
      break;\r
    case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:\r
      Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(1);\r
      break;\r
    case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:\r
      Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(1);\r
      break;\r
    default:\r
      Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);\r
      break;\r
  }\r
  \r
  Entry    = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);\r
  Sections = ((( MemoryRegion->Length - 1 ) / TT_DESCRIPTOR_SECTION_SIZE ) + 1 );\r
  \r
  for (Index = 0; Index < Sections; Index++)\r
  {\r
    *Entry++     =  TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;\r
    PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;\r
  }\r
}\r
\r
RETURN_STATUS\r
EFIAPI\r
ArmConfigureMmu (\r
  IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryTable,\r
  OUT VOID                         **TranslationTableBase OPTIONAL,\r
  OUT UINTN                         *TranslationTableSize OPTIONAL\r
  )\r
{\r
  VOID  *TranslationTable;\r
\r
  // Allocate pages for translation table.\r
  TranslationTable = AllocatePages (EFI_SIZE_TO_PAGES (TRANSLATION_TABLE_SIZE + TRANSLATION_TABLE_ALIGNMENT));\r
  if (TranslationTable == NULL) {\r
    return RETURN_OUT_OF_RESOURCES;\r
  }\r
  TranslationTable = (VOID *)(((UINTN)TranslationTable + TRANSLATION_TABLE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_ALIGNMENT_MASK);\r
\r
  if (TranslationTableBase != NULL) {\r
    *TranslationTableBase = TranslationTable;\r
  }\r
  \r
  if (TranslationTableBase != NULL) {\r
    *TranslationTableSize = TRANSLATION_TABLE_SIZE;\r
  }\r
\r
  ZeroMem(TranslationTable, TRANSLATION_TABLE_SIZE);\r
\r
  ArmCleanInvalidateDataCache();\r
  ArmInvalidateInstructionCache();\r
  ArmInvalidateTlb();\r
\r
  ArmDisableDataCache();\r
  ArmDisableInstructionCache();\r
  ArmDisableMmu();\r
\r
  // Make sure nothing sneaked into the cache\r
  ArmCleanInvalidateDataCache();\r
  ArmInvalidateInstructionCache();\r
\r
  while (MemoryTable->Length != 0) {\r
    FillTranslationTable(TranslationTable, MemoryTable);\r
    MemoryTable++;\r
  }\r
\r
  ArmSetTTBR0(TranslationTable);\r
    \r
  ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) |\r
                            DOMAIN_ACCESS_CONTROL_NONE(14) |\r
                            DOMAIN_ACCESS_CONTROL_NONE(13) |\r
                            DOMAIN_ACCESS_CONTROL_NONE(12) |\r
                            DOMAIN_ACCESS_CONTROL_NONE(11) |\r
                            DOMAIN_ACCESS_CONTROL_NONE(10) |\r
                            DOMAIN_ACCESS_CONTROL_NONE( 9) |\r
                            DOMAIN_ACCESS_CONTROL_NONE( 8) |\r
                            DOMAIN_ACCESS_CONTROL_NONE( 7) |\r
                            DOMAIN_ACCESS_CONTROL_NONE( 6) |\r
                            DOMAIN_ACCESS_CONTROL_NONE( 5) |\r
                            DOMAIN_ACCESS_CONTROL_NONE( 4) |\r
                            DOMAIN_ACCESS_CONTROL_NONE( 3) |\r
                            DOMAIN_ACCESS_CONTROL_NONE( 2) |\r
                            DOMAIN_ACCESS_CONTROL_NONE( 1) |\r
                            DOMAIN_ACCESS_CONTROL_MANAGER(0));\r
    \r
  ArmEnableInstructionCache();\r
  ArmEnableDataCache();\r
  ArmEnableMmu();\r
\r
  return RETURN_SUCCESS;\r
}\r