[mirror_edk2.git] / ArmPkg / Library / ArmLib / Arm9 / Arm9Support.asm

//------------------------------------------------------------------------------\r
//\r
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
//\r
// This program and the accompanying materials\r
// are licensed and made available under the terms and conditions of the BSD License\r
// which accompanies this distribution.  The full text of the license may be found at\r
// http://opensource.org/licenses/bsd-license.php\r
//\r
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
//\r
//------------------------------------------------------------------------------\r
\r
    EXPORT  ArmCleanInvalidateDataCache\r
    EXPORT  ArmCleanDataCache\r
    EXPORT  ArmInvalidateDataCache\r
    EXPORT  ArmInvalidateInstructionCache\r
    EXPORT  ArmInvalidateDataCacheEntryByMVA\r
    EXPORT  ArmCleanDataCacheEntryByMVA\r
    EXPORT  ArmCleanInvalidateDataCacheEntryByMVA\r
    EXPORT  ArmEnableMmu\r
    EXPORT  ArmDisableMmu\r
    EXPORT  ArmMmuEnabled\r
    EXPORT  ArmEnableDataCache\r
    EXPORT  ArmDisableDataCache\r
    EXPORT  ArmEnableInstructionCache\r
    EXPORT  ArmDisableInstructionCache\r
    EXPORT  ArmEnableBranchPrediction\r
    EXPORT  ArmDisableBranchPrediction\r
    EXPORT  ArmDataMemoryBarrier\r
    EXPORT  ArmDataSyncronizationBarrier\r
    EXPORT  ArmInstructionSynchronizationBarrier\r
\r
\r
DC_ON       EQU     ( 0x1:SHL:2 )\r
IC_ON       EQU     ( 0x1:SHL:12 )\r
\r
    AREA    ArmCacheLib, CODE, READONLY\r
    PRESERVE8\r
\r
\r
ArmInvalidateDataCacheEntryByMVA\r
  MCR     p15, 0, r0, c7, c6, 1   ; invalidate single data cache line\r
  BX      lr\r
\r
\r
ArmCleanDataCacheEntryByMVA\r
  MCR     p15, 0, r0, c7, c10, 1  ; clean single data cache line\r
  BX      lr\r
\r
\r
ArmCleanInvalidateDataCacheEntryByMVA\r
  MCR     p15, 0, r0, c7, c14, 1  ; clean and invalidate single data cache line\r
  BX      lr\r
\r
ArmEnableInstructionCache\r
  LDR     R1,=IC_ON\r
  MRC     p15,0,R0,c1,c0,0     ;Read control register configuration data\r
  ORR     R0,R0,R1             ;Set I bit\r
  MCR     p15,0,r0,c1,c0,0     ;Write control register configuration data\r
  BX      LR\r
\r
ArmDisableInstructionCache\r
  LDR     R1,=IC_ON\r
  MRC     p15,0,R0,c1,c0,0     ;Read control register configuration data\r
  BIC     R0,R0,R1             ;Clear I bit.\r
  MCR     p15,0,r0,c1,c0,0     ;Write control register configuration data\r
  BX      LR\r
\r
ArmInvalidateInstructionCache\r
  MOV     R0,#0\r
  MCR     p15,0,R0,c7,c5,0      ;Invalidate entire instruction cache\r
  MOV     R0,#0\r
  MCR     p15,0,R0,c7,c10,4     ;Drain write buffer\r
  BX      LR\r
\r
ArmEnableMmu\r
  mrc     p15,0,R0,c1,c0,0\r
  orr     R0,R0,#1\r
  mcr     p15,0,R0,c1,c0,0\r
  bx      LR\r
\r
ArmMmuEnabled\r
  mrc     p15,0,R0,c1,c0,0\r
  and     R0,R0,#1\r
  bx      LR\r
\r
ArmDisableMmu\r
  mrc     p15,0,R0,c1,c0,0\r
  bic     R0,R0,#1\r
  mcr     p15,0,R0,c1,c0,0\r
  mov     R0,#0\r
  mcr     p15,0,R0,c7,c10,4     ;Drain write buffer\r
  bx      LR\r
\r
ArmEnableDataCache\r
  LDR     R1,=DC_ON\r
  MRC     p15,0,R0,c1,c0,0      ;Read control register configuration data\r
  ORR     R0,R0,R1              ;Set C bit\r
  MCR     p15,0,r0,c1,c0,0      ;Write control register configuration data\r
  BX      LR\r
\r
ArmDisableDataCache\r
  LDR     R1,=DC_ON\r
  MRC     p15,0,R0,c1,c0,0      ;Read control register configuration data\r
  BIC     R0,R0,R1              ;Clear C bit\r
  MCR     p15,0,r0,c1,c0,0      ;Write control register configuration data\r
  BX      LR\r
\r
ArmCleanDataCache\r
  MRC     p15,0,r15,c7,c10,3\r
  BNE     ArmCleanDataCache\r
  MOV     R0,#0\r
  MCR     p15,0,R0,c7,c10,4      ;Drain write buffer\r
  BX      LR\r
\r
ArmInvalidateDataCache\r
  MOV     R0,#0\r
  MCR     p15,0,R0,c7,c6,0      ;Invalidate entire data cache\r
  MOV     R0,#0\r
  MCR     p15,0,R0,c7,c10,4     ;Drain write buffer\r
  BX      LR\r
\r
ArmCleanInvalidateDataCache\r
  MRC     p15,0,r15,c7,c14,3\r
  BNE     ArmCleanInvalidateDataCache\r
  MOV     R0,#0\r
  MCR     p15,0,R0,c7,c10,4      ;Drain write buffer\r
  BX      LR\r
\r
ArmEnableBranchPrediction\r
  bx      LR                    ;Branch prediction is not supported.\r
\r
ArmDisableBranchPrediction\r
  bx      LR                    ;Branch prediction is not supported.\r
\r
ASM_PFX(ArmDataMemoryBarrier):\r
  mov R0, #0\r
  mcr P15, #0, R0, C7, C10, #5  ; Check to see if this is correct\r
  bx      LR\r
\r
ASM_PFX(ArmDataSyncronizationBarrier):\r
  mov R0, #0\r
  mcr P15, #0, R0, C7, C10, #4 ; Check to see if this is correct\r
  bx      LR\r
\r
ASM_PFX(ArmInstructionSynchronizationBarrier):\r
  MOV R0, #0\r
  MCR P15, #0, R0, C7, C5, #4 ; Check to see if this is correct\r
  bx      LR\r
\r
    END\r
Commit	Line	Data
3402aac7	1	//------------------------------------------------------------------------------\r
1e57a462	2	//\r
	3	// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
	4	//\r
	5	// This program and the accompanying materials\r
	6	// are licensed and made available under the terms and conditions of the BSD License\r
	7	// which accompanies this distribution. The full text of the license may be found at\r
	8	// http://opensource.org/licenses/bsd-license.php\r
	9	//\r
	10	// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	11	// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	12	//\r
	13	//------------------------------------------------------------------------------\r
	14	\r
	15	EXPORT ArmCleanInvalidateDataCache\r
	16	EXPORT ArmCleanDataCache\r
	17	EXPORT ArmInvalidateDataCache\r
	18	EXPORT ArmInvalidateInstructionCache\r
	19	EXPORT ArmInvalidateDataCacheEntryByMVA\r
	20	EXPORT ArmCleanDataCacheEntryByMVA\r
	21	EXPORT ArmCleanInvalidateDataCacheEntryByMVA\r
	22	EXPORT ArmEnableMmu\r
	23	EXPORT ArmDisableMmu\r
	24	EXPORT ArmMmuEnabled\r
	25	EXPORT ArmEnableDataCache\r
	26	EXPORT ArmDisableDataCache\r
	27	EXPORT ArmEnableInstructionCache\r
	28	EXPORT ArmDisableInstructionCache\r
	29	EXPORT ArmEnableBranchPrediction\r
	30	EXPORT ArmDisableBranchPrediction\r
	31	EXPORT ArmDataMemoryBarrier\r
	32	EXPORT ArmDataSyncronizationBarrier\r
	33	EXPORT ArmInstructionSynchronizationBarrier\r
	34	\r
	35	\r
	36	DC_ON EQU ( 0x1:SHL:2 )\r
	37	IC_ON EQU ( 0x1:SHL:12 )\r
	38	\r
	39	AREA ArmCacheLib, CODE, READONLY\r
	40	PRESERVE8\r
	41	\r
	42	\r
	43	ArmInvalidateDataCacheEntryByMVA\r
3402aac7	44	MCR p15, 0, r0, c7, c6, 1 ; invalidate single data cache line\r
1e57a462	45	BX lr\r
	46	\r
	47	\r
	48	ArmCleanDataCacheEntryByMVA\r
3402aac7	49	MCR p15, 0, r0, c7, c10, 1 ; clean single data cache line\r
1e57a462	50	BX lr\r
	51	\r
	52	\r
	53	ArmCleanInvalidateDataCacheEntryByMVA\r
	54	MCR p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line\r
	55	BX lr\r
	56	\r
	57	ArmEnableInstructionCache\r
	58	LDR R1,=IC_ON\r
	59	MRC p15,0,R0,c1,c0,0 ;Read control register configuration data\r
	60	ORR R0,R0,R1 ;Set I bit\r
	61	MCR p15,0,r0,c1,c0,0 ;Write control register configuration data\r
	62	BX LR\r
3402aac7	63	\r
1e57a462	64	ArmDisableInstructionCache\r
	65	LDR R1,=IC_ON\r
	66	MRC p15,0,R0,c1,c0,0 ;Read control register configuration data\r
	67	BIC R0,R0,R1 ;Clear I bit.\r
	68	MCR p15,0,r0,c1,c0,0 ;Write control register configuration data\r
	69	BX LR\r
	70	\r
	71	ArmInvalidateInstructionCache\r
	72	MOV R0,#0\r
	73	MCR p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache\r
	74	MOV R0,#0\r
	75	MCR p15,0,R0,c7,c10,4 ;Drain write buffer\r
	76	BX LR\r
	77	\r
	78	ArmEnableMmu\r
	79	mrc p15,0,R0,c1,c0,0\r
	80	orr R0,R0,#1\r
	81	mcr p15,0,R0,c1,c0,0\r
	82	bx LR\r
	83	\r
	84	ArmMmuEnabled\r
	85	mrc p15,0,R0,c1,c0,0\r
	86	and R0,R0,#1\r
	87	bx LR\r
	88	\r
	89	ArmDisableMmu\r
	90	mrc p15,0,R0,c1,c0,0\r
	91	bic R0,R0,#1\r
	92	mcr p15,0,R0,c1,c0,0\r
	93	mov R0,#0\r
	94	mcr p15,0,R0,c7,c10,4 ;Drain write buffer\r
	95	bx LR\r
	96	\r
	97	ArmEnableDataCache\r
	98	LDR R1,=DC_ON\r
	99	MRC p15,0,R0,c1,c0,0 ;Read control register configuration data\r
	100	ORR R0,R0,R1 ;Set C bit\r
	101	MCR p15,0,r0,c1,c0,0 ;Write control register configuration data\r
	102	BX LR\r
3402aac7	103	\r
1e57a462	104	ArmDisableDataCache\r
	105	LDR R1,=DC_ON\r
	106	MRC p15,0,R0,c1,c0,0 ;Read control register configuration data\r
	107	BIC R0,R0,R1 ;Clear C bit\r
	108	MCR p15,0,r0,c1,c0,0 ;Write control register configuration data\r
	109	BX LR\r
	110	\r
	111	ArmCleanDataCache\r
	112	MRC p15,0,r15,c7,c10,3\r
	113	BNE ArmCleanDataCache\r
	114	MOV R0,#0\r
	115	MCR p15,0,R0,c7,c10,4 ;Drain write buffer\r
	116	BX LR\r
	117	\r
	118	ArmInvalidateDataCache\r
	119	MOV R0,#0\r
	120	MCR p15,0,R0,c7,c6,0 ;Invalidate entire data cache\r
	121	MOV R0,#0\r
	122	MCR p15,0,R0,c7,c10,4 ;Drain write buffer\r
	123	BX LR\r
3402aac7	124	\r
1e57a462	125	ArmCleanInvalidateDataCache\r
	126	MRC p15,0,r15,c7,c14,3\r
	127	BNE ArmCleanInvalidateDataCache\r
	128	MOV R0,#0\r
	129	MCR p15,0,R0,c7,c10,4 ;Drain write buffer\r
	130	BX LR\r
	131	\r
	132	ArmEnableBranchPrediction\r
	133	bx LR ;Branch prediction is not supported.\r
	134	\r
	135	ArmDisableBranchPrediction\r
	136	bx LR ;Branch prediction is not supported.\r
	137	\r
	138	ASM_PFX(ArmDataMemoryBarrier):\r
	139	mov R0, #0\r
	140	mcr P15, #0, R0, C7, C10, #5 ; Check to see if this is correct\r
	141	bx LR\r
3402aac7	142	\r
1e57a462	143	ASM_PFX(ArmDataSyncronizationBarrier):\r
	144	mov R0, #0\r
	145	mcr P15, #0, R0, C7, C10, #4 ; Check to see if this is correct\r
	146	bx LR\r
3402aac7	147	\r
1e57a462	148	ASM_PFX(ArmInstructionSynchronizationBarrier):\r
	149	MOV R0, #0\r
	150	MCR P15, #0, R0, C7, C5, #4 ; Check to see if this is correct\r
	151	bx LR\r
	152	\r
	153	END\r