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1 | //------------------------------------------------------------------------------ |
2 | // | |
3 | // Copyright (c) 2008-2009 Apple Inc. All rights reserved. | |
4 | // | |
5 | // All rights reserved. This program and the accompanying materials | |
6 | // are licensed and made available under the terms and conditions of the BSD License | |
7 | // which accompanies this distribution. The full text of the license may be found at | |
8 | // http://opensource.org/licenses/bsd-license.php | |
9 | // | |
10 | // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, | |
11 | // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. | |
12 | // | |
13 | //------------------------------------------------------------------------------ | |
14 | ||
15 | EXPORT ArmInvalidateInstructionCache | |
16 | EXPORT ArmInvalidateDataCacheEntryByMVA | |
17 | EXPORT ArmCleanDataCacheEntryByMVA | |
18 | EXPORT ArmCleanInvalidateDataCacheEntryByMVA | |
19 | EXPORT ArmInvalidateDataCacheEntryBySetWay | |
20 | EXPORT ArmCleanDataCacheEntryBySetWay | |
21 | EXPORT ArmCleanInvalidateDataCacheEntryBySetWay | |
22 | EXPORT ArmDrainWriteBuffer | |
23 | EXPORT ArmEnableMmu | |
24 | EXPORT ArmDisableMmu | |
c2b5ca8b | 25 | EXPORT ArmMmuEnabled |
2ef2b01e A |
26 | EXPORT ArmEnableDataCache |
27 | EXPORT ArmDisableDataCache | |
28 | EXPORT ArmEnableInstructionCache | |
29 | EXPORT ArmDisableInstructionCache | |
30 | EXPORT ArmEnableBranchPrediction | |
31 | EXPORT ArmDisableBranchPrediction | |
32 | ||
33 | DC_ON EQU ( 0x1:SHL:2 ) | |
34 | IC_ON EQU ( 0x1:SHL:12 ) | |
35 | XP_ON EQU ( 0x1:SHL:23 ) | |
36 | ||
37 | ||
38 | AREA ArmCacheLib, CODE, READONLY | |
39 | PRESERVE8 | |
40 | ||
41 | ||
42 | ArmInvalidateDataCacheEntryByMVA | |
43 | MCR p15, 0, r0, c7, c6, 1 ; invalidate single data cache line | |
44 | BX lr | |
45 | ||
46 | ||
47 | ArmCleanDataCacheEntryByMVA | |
48 | MCR p15, 0, r0, c7, c10, 1 ; clean single data cache line | |
49 | BX lr | |
50 | ||
51 | ||
52 | ArmCleanInvalidateDataCacheEntryByMVA | |
53 | MCR p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line | |
54 | BX lr | |
55 | ||
56 | ||
57 | ArmInvalidateDataCacheEntryBySetWay | |
58 | mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line | |
59 | bx lr | |
60 | ||
61 | ||
62 | ArmCleanInvalidateDataCacheEntryBySetWay | |
63 | mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line | |
64 | bx lr | |
65 | ||
66 | ||
67 | ArmCleanDataCacheEntryBySetWay | |
68 | mcr p15, 0, r0, c7, c10, 2 ; Clean this line | |
69 | bx lr | |
70 | ||
71 | ||
72 | ArmDrainWriteBuffer | |
73 | mcr p15, 0, r0, c7, c10, 4 ; Drain write buffer for sync | |
74 | bx lr | |
75 | ||
76 | ||
77 | ArmInvalidateInstructionCache | |
78 | MOV R0,#0 | |
79 | MCR p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache | |
80 | MOV R0,#0 | |
81 | MCR p15,0,R0,c7,c5,4 ;Instruction synchronization barrier | |
82 | BX LR | |
83 | ||
84 | ArmEnableMmu | |
85 | mrc p15,0,R0,c1,c0,0 | |
86 | orr R0,R0,#1 | |
87 | mcr p15,0,R0,c1,c0,0 | |
88 | bx LR | |
89 | ||
c2b5ca8b A |
90 | ArmMmuEnabled |
91 | mrc p15,0,R0,c1,c0,0 | |
92 | and R0,R0,#1 | |
93 | bx LR | |
94 | ||
2ef2b01e A |
95 | ArmDisableMmu |
96 | mov R0,#0 | |
97 | mcr p15,0,R0,c13,c0,0 ;FCSE PID register must be cleared before disabling MMU | |
98 | mrc p15,0,R0,c1,c0,0 | |
99 | bic R0,R0,#1 | |
100 | mcr p15,0,R0,c1,c0,0 ;Disable MMU | |
101 | mov R0,#0 | |
102 | mcr p15,0,R0,c7,c10,4 ;Data synchronization barrier | |
103 | mov R0,#0 | |
104 | mcr p15,0,R0,c7,c5,4 ;Instruction synchronization barrier | |
105 | bx LR | |
106 | ||
107 | ArmEnableDataCache | |
108 | LDR R1,=DC_ON | |
109 | MRC p15,0,R0,c1,c0,0 ;Read control register configuration data | |
110 | ORR R0,R0,R1 ;Set C bit | |
111 | MCR p15,0,r0,c1,c0,0 ;Write control register configuration data | |
112 | BX LR | |
113 | ||
114 | ArmDisableDataCache | |
115 | LDR R1,=DC_ON | |
116 | MRC p15,0,R0,c1,c0,0 ;Read control register configuration data | |
117 | BIC R0,R0,R1 ;Clear C bit | |
118 | MCR p15,0,r0,c1,c0,0 ;Write control register configuration data | |
119 | BX LR | |
120 | ||
121 | ArmEnableInstructionCache | |
122 | LDR R1,=IC_ON | |
123 | MRC p15,0,R0,c1,c0,0 ;Read control register configuration data | |
124 | ORR R0,R0,R1 ;Set I bit | |
125 | MCR p15,0,r0,c1,c0,0 ;Write control register configuration data | |
126 | BX LR | |
127 | ||
128 | ArmDisableInstructionCache | |
129 | LDR R1,=IC_ON | |
130 | MRC p15,0,R0,c1,c0,0 ;Read control register configuration data | |
131 | BIC R0,R0,R1 ;Clear I bit. | |
132 | MCR p15,0,r0,c1,c0,0 ;Write control register configuration data | |
133 | BX LR | |
134 | ||
135 | ArmEnableBranchPrediction | |
136 | mrc p15, 0, r0, c1, c0, 0 | |
137 | orr r0, r0, #0x00000800 | |
138 | mcr p15, 0, r0, c1, c0, 0 | |
139 | bx LR | |
140 | ||
141 | ArmDisableBranchPrediction | |
142 | mrc p15, 0, r0, c1, c0, 0 | |
143 | bic r0, r0, #0x00000800 | |
144 | mcr p15, 0, r0, c1, c0, 0 | |
145 | bx LR | |
146 | ||
147 | END |