projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 3402aac7 | 1 | #------------------------------------------------------------------------------\r |
| bd6b9799 | 2 | #\r |
| 3 | # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r | |
| d6dc67ba | 4 | # Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r |
| bd6b9799 | 5 | #\r |
| 6 | # This program and the accompanying materials\r | |
| 7 | # are licensed and made available under the terms and conditions of the BSD License\r | |
| 8 | # which accompanies this distribution. The full text of the license may be found at\r | |
| 9 | # http://opensource.org/licenses/bsd-license.php\r | |
| 10 | #\r | |
| 11 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 12 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 13 | #\r | |
| 14 | #------------------------------------------------------------------------------\r | |
| 15 | \r | |
| 16 | #include <AsmMacroIoLib.h>\r | |
| 17 | \r | |
| 18 | .text\r | |
| 19 | .align 2\r | |
| 20 | \r | |
| 21 | GCC_ASM_EXPORT(ArmIsMpCore)\r | |
| 22 | GCC_ASM_EXPORT(ArmEnableAsynchronousAbort)\r | |
| 23 | GCC_ASM_EXPORT(ArmDisableAsynchronousAbort)\r | |
| 24 | GCC_ASM_EXPORT(ArmEnableIrq)\r | |
| 25 | GCC_ASM_EXPORT(ArmDisableIrq)\r | |
| 26 | GCC_ASM_EXPORT(ArmEnableFiq)\r | |
| 27 | GCC_ASM_EXPORT(ArmDisableFiq)\r | |
| 28 | GCC_ASM_EXPORT(ArmEnableInterrupts)\r | |
| 29 | GCC_ASM_EXPORT(ArmDisableInterrupts)\r | |
| 30 | GCC_ASM_EXPORT(ReadCCSIDR)\r | |
| 31 | GCC_ASM_EXPORT(ReadCLIDR)\r | |
| d6dc67ba OM |
32 | GCC_ASM_EXPORT(ArmReadNsacr)\r |
| 33 | GCC_ASM_EXPORT(ArmWriteNsacr)\r | |
| bd6b9799 | 34 | \r |
| 35 | #------------------------------------------------------------------------------\r | |
| 36 | \r | |
| 37 | ASM_PFX(ArmIsMpCore):\r | |
| 38 | mrc p15,0,R0,c0,c0,5\r | |
| 39 | // Get Multiprocessing extension (bit31) & U bit (bit30)\r | |
| 40 | and R0, R0, #0xC0000000\r | |
| 41 | // if bit30 == 0 then the processor is part of a multiprocessor system)\r | |
| 42 | and R0, R0, #0x80000000\r | |
| 43 | bx LR\r | |
| 44 | \r | |
| 45 | ASM_PFX(ArmEnableAsynchronousAbort):\r | |
| 46 | cpsie a\r | |
| 47 | isb\r | |
| 48 | bx LR\r | |
| 49 | \r | |
| 50 | ASM_PFX(ArmDisableAsynchronousAbort):\r | |
| 51 | cpsid a\r | |
| 52 | isb\r | |
| 53 | bx LR\r | |
| 54 | \r | |
| 55 | ASM_PFX(ArmEnableIrq):\r | |
| 56 | cpsie i\r | |
| 57 | isb\r | |
| 58 | bx LR\r | |
| 59 | \r | |
| 60 | ASM_PFX(ArmDisableIrq):\r | |
| 61 | cpsid i\r | |
| 62 | isb\r | |
| 63 | bx LR\r | |
| 64 | \r | |
| 65 | ASM_PFX(ArmEnableFiq):\r | |
| 66 | cpsie f\r | |
| 67 | isb\r | |
| 68 | bx LR\r | |
| 69 | \r | |
| 70 | ASM_PFX(ArmDisableFiq):\r | |
| 71 | cpsid f\r | |
| 72 | isb\r | |
| 73 | bx LR\r | |
| 74 | \r | |
| 75 | ASM_PFX(ArmEnableInterrupts):\r | |
| 76 | cpsie if\r | |
| 77 | isb\r | |
| 78 | bx LR\r | |
| 79 | \r | |
| 80 | ASM_PFX(ArmDisableInterrupts):\r | |
| 81 | cpsid if\r | |
| 82 | isb\r | |
| 83 | bx LR\r | |
| 3402aac7 RC |
84 | \r |
| 85 | // UINT32\r | |
| bd6b9799 | 86 | // ReadCCSIDR (\r |
| 87 | // IN UINT32 CSSELR\r | |
| 3402aac7 | 88 | // )\r |
| bd6b9799 | 89 | ASM_PFX(ReadCCSIDR):\r |
| 90 | mcr p15,2,r0,c0,c0,0 @ Write Cache Size Selection Register (CSSELR)\r | |
| 91 | isb\r | |
| 92 | mrc p15,1,r0,c0,c0,0 @ Read current CP15 Cache Size ID Register (CCSIDR)\r | |
| 93 | bx lr\r | |
| 3402aac7 RC |
94 | \r |
| 95 | // UINT32\r | |
| bd6b9799 | 96 | // ReadCLIDR (\r |
| 97 | // IN UINT32 CSSELR\r | |
| 3402aac7 | 98 | // )\r |
| bd6b9799 | 99 | ASM_PFX(ReadCLIDR):\r |
| 100 | mrc p15,1,r0,c0,c0,1 @ Read CP15 Cache Level ID Register\r | |
| 101 | bx lr\r | |
| 102 | \r | |
| d6dc67ba OM |
103 | ASM_PFX(ArmReadNsacr):\r |
| 104 | mrc p15, 0, r0, c1, c1, 2\r | |
| 105 | bx lr\r | |
| 106 | \r | |
| 107 | ASM_PFX(ArmWriteNsacr):\r | |
| 108 | mcr p15, 0, r0, c1, c1, 2\r | |
| 109 | bx lr\r | |
| 110 | \r | |
| bd6b9799 | 111 | ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r |