projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 3402aac7 | 1 | //------------------------------------------------------------------------------\r |
| bd6b9799 | 2 | //\r |
| 3 | // Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r | |
| d6dc67ba | 4 | // Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r |
| bd6b9799 | 5 | //\r |
| 6 | // This program and the accompanying materials\r | |
| 7 | // are licensed and made available under the terms and conditions of the BSD License\r | |
| 8 | // which accompanies this distribution. The full text of the license may be found at\r | |
| 9 | // http://opensource.org/licenses/bsd-license.php\r | |
| 10 | //\r | |
| 11 | // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 12 | // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 13 | //\r | |
| 14 | //------------------------------------------------------------------------------\r | |
| 15 | \r | |
| 16 | \r | |
| efda1775 EC |
17 | \r |
| 18 | INCLUDE AsmMacroExport.inc\r | |
| bd6b9799 | 19 | \r |
| 20 | \r | |
| 21 | //------------------------------------------------------------------------------\r | |
| 22 | \r | |
| efda1775 | 23 | RVCT_ASM_EXPORT ArmIsMpCore\r |
| bd6b9799 | 24 | mrc p15,0,R0,c0,c0,5\r |
| 25 | // Get Multiprocessing extension (bit31) & U bit (bit30)\r | |
| 26 | and R0, R0, #0xC0000000\r | |
| 5a539eb5 OM |
27 | // if (bit31 == 1) && (bit30 == 0) then the processor is part of a multiprocessor system\r |
| 28 | cmp R0, #0x80000000\r | |
| 29 | moveq R0, #1\r | |
| 30 | movne R0, #0\r | |
| bd6b9799 | 31 | bx LR\r |
| 32 | \r | |
| efda1775 | 33 | RVCT_ASM_EXPORT ArmEnableAsynchronousAbort\r |
| bd6b9799 | 34 | cpsie a\r |
| 35 | isb\r | |
| 36 | bx LR\r | |
| 37 | \r | |
| efda1775 | 38 | RVCT_ASM_EXPORT ArmDisableAsynchronousAbort\r |
| bd6b9799 | 39 | cpsid a\r |
| 40 | isb\r | |
| 41 | bx LR\r | |
| 42 | \r | |
| efda1775 | 43 | RVCT_ASM_EXPORT ArmEnableIrq\r |
| bd6b9799 | 44 | cpsie i\r |
| 45 | isb\r | |
| 46 | bx LR\r | |
| 47 | \r | |
| efda1775 | 48 | RVCT_ASM_EXPORT ArmDisableIrq\r |
| bd6b9799 | 49 | cpsid i\r |
| 50 | isb\r | |
| 51 | bx LR\r | |
| 52 | \r | |
| efda1775 | 53 | RVCT_ASM_EXPORT ArmEnableFiq\r |
| bd6b9799 | 54 | cpsie f\r |
| 55 | isb\r | |
| 56 | bx LR\r | |
| 57 | \r | |
| efda1775 | 58 | RVCT_ASM_EXPORT ArmDisableFiq\r |
| bd6b9799 | 59 | cpsid f\r |
| 60 | isb\r | |
| 61 | bx LR\r | |
| 62 | \r | |
| efda1775 | 63 | RVCT_ASM_EXPORT ArmEnableInterrupts\r |
| bd6b9799 | 64 | cpsie if\r |
| 65 | isb\r | |
| 66 | bx LR\r | |
| 67 | \r | |
| efda1775 | 68 | RVCT_ASM_EXPORT ArmDisableInterrupts\r |
| bd6b9799 | 69 | cpsid if\r |
| 70 | isb\r | |
| 71 | bx LR\r | |
| 3402aac7 RC |
72 | \r |
| 73 | // UINT32\r | |
| bd6b9799 | 74 | // ReadCCSIDR (\r |
| 75 | // IN UINT32 CSSELR\r | |
| 3402aac7 | 76 | // )\r |
| efda1775 | 77 | RVCT_ASM_EXPORT ReadCCSIDR\r |
| bd6b9799 | 78 | mcr p15,2,r0,c0,c0,0 ; Write Cache Size Selection Register (CSSELR)\r |
| 79 | isb\r | |
| 80 | mrc p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)\r | |
| 81 | bx lr\r | |
| 3402aac7 RC |
82 | \r |
| 83 | // UINT32\r | |
| bd6b9799 | 84 | // ReadCLIDR (\r |
| 85 | // IN UINT32 CSSELR\r | |
| 3402aac7 | 86 | // )\r |
| efda1775 | 87 | RVCT_ASM_EXPORT ReadCLIDR\r |
| bd6b9799 | 88 | mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register\r |
| 89 | bx lr\r | |
| d6dc67ba | 90 | \r |
| efda1775 | 91 | RVCT_ASM_EXPORT ArmReadNsacr\r |
| d6dc67ba OM |
92 | mrc p15, 0, r0, c1, c1, 2\r |
| 93 | bx lr\r | |
| 94 | \r | |
| efda1775 | 95 | RVCT_ASM_EXPORT ArmWriteNsacr\r |
| d6dc67ba OM |
96 | mcr p15, 0, r0, c1, c1, 2\r |
| 97 | bx lr\r | |
| 98 | \r | |
| 2575b726 | 99 | END\r |