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1e57a462 | 1 | /** @file\r |
2 | \r | |
3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r | |
01674afd | 4 | Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r |
3402aac7 | 5 | \r |
1e57a462 | 6 | This program and the accompanying materials\r |
7 | are licensed and made available under the terms and conditions of the BSD License\r | |
8 | which accompanies this distribution. The full text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
14 | **/\r | |
15 | #include <Uefi.h>\r | |
16 | #include <Chipset/ArmV7.h>\r | |
17 | #include <Library/ArmLib.h>\r | |
18 | #include <Library/BaseLib.h>\r | |
19 | #include <Library/IoLib.h>\r | |
20 | #include "ArmV7Lib.h"\r | |
21 | #include "ArmLibPrivate.h"\r | |
22 | \r | |
23 | ARM_CACHE_TYPE\r | |
24 | EFIAPI\r | |
25 | ArmCacheType (\r | |
26 | VOID\r | |
27 | )\r | |
28 | {\r | |
29 | return ARM_CACHE_TYPE_WRITE_BACK;\r | |
30 | }\r | |
31 | \r | |
32 | ARM_CACHE_ARCHITECTURE\r | |
33 | EFIAPI\r | |
34 | ArmCacheArchitecture (\r | |
35 | VOID\r | |
36 | )\r | |
37 | {\r | |
38 | UINT32 CLIDR = ReadCLIDR ();\r | |
39 | \r | |
40 | return (ARM_CACHE_ARCHITECTURE)CLIDR; // BugBug Fix Me\r | |
41 | }\r | |
42 | \r | |
43 | BOOLEAN\r | |
44 | EFIAPI\r | |
45 | ArmDataCachePresent (\r | |
46 | VOID\r | |
47 | )\r | |
48 | {\r | |
49 | UINT32 CLIDR = ReadCLIDR ();\r | |
3402aac7 | 50 | \r |
1e57a462 | 51 | if ((CLIDR & 0x2) == 0x2) {\r |
52 | // Instruction cache exists\r | |
53 | return TRUE;\r | |
54 | }\r | |
55 | if ((CLIDR & 0x7) == 0x4) {\r | |
56 | // Unified cache\r | |
57 | return TRUE;\r | |
58 | }\r | |
3402aac7 | 59 | \r |
1e57a462 | 60 | return FALSE;\r |
61 | }\r | |
3402aac7 | 62 | \r |
1e57a462 | 63 | UINTN\r |
64 | EFIAPI\r | |
65 | ArmDataCacheSize (\r | |
66 | VOID\r | |
67 | )\r | |
68 | {\r | |
69 | UINT32 NumSets;\r | |
70 | UINT32 Associativity;\r | |
71 | UINT32 LineSize;\r | |
72 | UINT32 CCSIDR = ReadCCSIDR (0);\r | |
3402aac7 | 73 | \r |
1e57a462 | 74 | LineSize = (1 << ((CCSIDR & 0x7) + 2));\r |
75 | Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;\r | |
76 | NumSets = ((CCSIDR >> 13) & 0x7fff) + 1;\r | |
77 | \r | |
78 | // LineSize is in words (4 byte chunks)\r | |
3402aac7 | 79 | return NumSets * Associativity * LineSize * 4;\r |
1e57a462 | 80 | }\r |
3402aac7 | 81 | \r |
1e57a462 | 82 | UINTN\r |
83 | EFIAPI\r | |
84 | ArmDataCacheAssociativity (\r | |
85 | VOID\r | |
86 | )\r | |
87 | {\r | |
88 | UINT32 CCSIDR = ReadCCSIDR (0);\r | |
89 | \r | |
90 | return ((CCSIDR >> 3) & 0x3ff) + 1;\r | |
91 | }\r | |
3402aac7 | 92 | \r |
1e57a462 | 93 | UINTN\r |
94 | ArmDataCacheSets (\r | |
95 | VOID\r | |
96 | )\r | |
97 | {\r | |
98 | UINT32 CCSIDR = ReadCCSIDR (0);\r | |
3402aac7 | 99 | \r |
1e57a462 | 100 | return ((CCSIDR >> 13) & 0x7fff) + 1;\r |
101 | }\r | |
102 | \r | |
103 | UINTN\r | |
104 | EFIAPI\r | |
105 | ArmDataCacheLineLength (\r | |
106 | VOID\r | |
107 | )\r | |
108 | {\r | |
109 | UINT32 CCSIDR = ReadCCSIDR (0) & 7;\r | |
110 | \r | |
111 | // * 4 converts to bytes\r | |
112 | return (1 << (CCSIDR + 2)) * 4;\r | |
113 | }\r | |
3402aac7 | 114 | \r |
1e57a462 | 115 | BOOLEAN\r |
116 | EFIAPI\r | |
117 | ArmInstructionCachePresent (\r | |
118 | VOID\r | |
119 | )\r | |
120 | {\r | |
121 | UINT32 CLIDR = ReadCLIDR ();\r | |
3402aac7 | 122 | \r |
1e57a462 | 123 | if ((CLIDR & 1) == 1) {\r |
124 | // Instruction cache exists\r | |
125 | return TRUE;\r | |
126 | }\r | |
127 | if ((CLIDR & 0x7) == 0x4) {\r | |
128 | // Unified cache\r | |
129 | return TRUE;\r | |
130 | }\r | |
3402aac7 | 131 | \r |
1e57a462 | 132 | return FALSE;\r |
133 | }\r | |
3402aac7 | 134 | \r |
1e57a462 | 135 | UINTN\r |
136 | EFIAPI\r | |
137 | ArmInstructionCacheSize (\r | |
138 | VOID\r | |
139 | )\r | |
140 | {\r | |
141 | UINT32 NumSets;\r | |
142 | UINT32 Associativity;\r | |
143 | UINT32 LineSize;\r | |
144 | UINT32 CCSIDR = ReadCCSIDR (1);\r | |
3402aac7 | 145 | \r |
1e57a462 | 146 | LineSize = (1 << ((CCSIDR & 0x7) + 2));\r |
147 | Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;\r | |
148 | NumSets = ((CCSIDR >> 13) & 0x7fff) + 1;\r | |
149 | \r | |
150 | // LineSize is in words (4 byte chunks)\r | |
3402aac7 | 151 | return NumSets * Associativity * LineSize * 4;\r |
1e57a462 | 152 | }\r |
3402aac7 | 153 | \r |
1e57a462 | 154 | UINTN\r |
155 | EFIAPI\r | |
156 | ArmInstructionCacheAssociativity (\r | |
157 | VOID\r | |
158 | )\r | |
159 | {\r | |
160 | UINT32 CCSIDR = ReadCCSIDR (1);\r | |
161 | \r | |
162 | return ((CCSIDR >> 3) & 0x3ff) + 1;\r | |
163 | // return 4;\r | |
164 | }\r | |
3402aac7 | 165 | \r |
1e57a462 | 166 | UINTN\r |
167 | EFIAPI\r | |
168 | ArmInstructionCacheSets (\r | |
169 | VOID\r | |
170 | )\r | |
171 | {\r | |
172 | UINT32 CCSIDR = ReadCCSIDR (1);\r | |
3402aac7 | 173 | \r |
1e57a462 | 174 | return ((CCSIDR >> 13) & 0x7fff) + 1;\r |
175 | }\r | |
176 | \r | |
177 | UINTN\r | |
178 | EFIAPI\r | |
179 | ArmInstructionCacheLineLength (\r | |
180 | VOID\r | |
181 | )\r | |
182 | {\r | |
183 | UINT32 CCSIDR = ReadCCSIDR (1) & 7;\r | |
184 | \r | |
185 | // * 4 converts to bytes\r | |
186 | return (1 << (CCSIDR + 2)) * 4;\r | |
187 | \r | |
188 | // return 64;\r | |
189 | }\r | |
190 | \r | |
191 | \r | |
192 | VOID\r | |
193 | ArmV7DataCacheOperation (\r | |
194 | IN ARM_V7_CACHE_OPERATION DataCacheOperation\r | |
195 | )\r | |
196 | {\r | |
197 | UINTN SavedInterruptState;\r | |
198 | \r | |
199 | SavedInterruptState = ArmGetInterruptState ();\r | |
200 | ArmDisableInterrupts ();\r | |
3402aac7 | 201 | \r |
1e57a462 | 202 | ArmV7AllDataCachesOperation (DataCacheOperation);\r |
3402aac7 | 203 | \r |
1e57a462 | 204 | ArmDrainWriteBuffer ();\r |
3402aac7 | 205 | \r |
1e57a462 | 206 | if (SavedInterruptState) {\r |
207 | ArmEnableInterrupts ();\r | |
208 | }\r | |
209 | }\r | |
210 | \r | |
211 | \r | |
212 | VOID\r | |
213 | ArmV7PoUDataCacheOperation (\r | |
214 | IN ARM_V7_CACHE_OPERATION DataCacheOperation\r | |
215 | )\r | |
216 | {\r | |
217 | UINTN SavedInterruptState;\r | |
218 | \r | |
219 | SavedInterruptState = ArmGetInterruptState ();\r | |
220 | ArmDisableInterrupts ();\r | |
3402aac7 | 221 | \r |
1e57a462 | 222 | ArmV7PerformPoUDataCacheOperation (DataCacheOperation);\r |
3402aac7 | 223 | \r |
1e57a462 | 224 | ArmDrainWriteBuffer ();\r |
3402aac7 | 225 | \r |
1e57a462 | 226 | if (SavedInterruptState) {\r |
227 | ArmEnableInterrupts ();\r | |
228 | }\r | |
229 | }\r | |
230 | \r | |
231 | VOID\r | |
232 | EFIAPI\r | |
233 | ArmInvalidateDataCache (\r | |
234 | VOID\r | |
235 | )\r | |
236 | {\r | |
01674afd | 237 | ArmDrainWriteBuffer ();\r |
1e57a462 | 238 | ArmV7DataCacheOperation (ArmInvalidateDataCacheEntryBySetWay);\r |
239 | }\r | |
240 | \r | |
241 | VOID\r | |
242 | EFIAPI\r | |
243 | ArmCleanInvalidateDataCache (\r | |
244 | VOID\r | |
245 | )\r | |
246 | {\r | |
01674afd | 247 | ArmDrainWriteBuffer ();\r |
1e57a462 | 248 | ArmV7DataCacheOperation (ArmCleanInvalidateDataCacheEntryBySetWay);\r |
249 | }\r | |
250 | \r | |
251 | VOID\r | |
252 | EFIAPI\r | |
253 | ArmCleanDataCache (\r | |
254 | VOID\r | |
255 | )\r | |
256 | {\r | |
01674afd | 257 | ArmDrainWriteBuffer ();\r |
1e57a462 | 258 | ArmV7DataCacheOperation (ArmCleanDataCacheEntryBySetWay);\r |
259 | }\r | |
260 | \r | |
261 | VOID\r | |
262 | EFIAPI\r | |
263 | ArmCleanDataCacheToPoU (\r | |
264 | VOID\r | |
265 | )\r | |
266 | {\r | |
01674afd | 267 | ArmDrainWriteBuffer ();\r |
1e57a462 | 268 | ArmV7PoUDataCacheOperation (ArmCleanDataCacheEntryBySetWay);\r |
269 | }\r |