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2ef2b01e A |
1 | #------------------------------------------------------------------------------ |
2 | # | |
d6ebcab7 | 3 | # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> |
2ef2b01e | 4 | # |
d6ebcab7 | 5 | # This program and the accompanying materials |
2ef2b01e A |
6 | # are licensed and made available under the terms and conditions of the BSD License |
7 | # which accompanies this distribution. The full text of the license may be found at | |
8 | # http://opensource.org/licenses/bsd-license.php | |
9 | # | |
10 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, | |
11 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. | |
12 | # | |
13 | #------------------------------------------------------------------------------ | |
14 | ||
548af3e7 | 15 | .text |
16 | .align 2 | |
2ef2b01e | 17 | |
1bfda055 | 18 | GCC_ASM_EXPORT (ArmInvalidateInstructionCache) |
19 | GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA) | |
20 | GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA) | |
21 | GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA) | |
22 | GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay) | |
23 | GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay) | |
24 | GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryBySetWay) | |
25 | GCC_ASM_EXPORT (ArmDrainWriteBuffer) | |
26 | GCC_ASM_EXPORT (ArmEnableMmu) | |
27 | GCC_ASM_EXPORT (ArmDisableMmu) | |
28 | GCC_ASM_EXPORT (ArmDisableCachesAndMmu) | |
29 | GCC_ASM_EXPORT (ArmMmuEnabled) | |
30 | GCC_ASM_EXPORT (ArmEnableDataCache) | |
31 | GCC_ASM_EXPORT (ArmDisableDataCache) | |
32 | GCC_ASM_EXPORT (ArmEnableInstructionCache) | |
33 | GCC_ASM_EXPORT (ArmDisableInstructionCache) | |
34 | GCC_ASM_EXPORT (ArmEnableSWPInstruction) | |
35 | GCC_ASM_EXPORT (ArmEnableBranchPrediction) | |
36 | GCC_ASM_EXPORT (ArmDisableBranchPrediction) | |
f0fef790 | 37 | GCC_ASM_EXPORT (ArmSetLowVectors) |
38 | GCC_ASM_EXPORT (ArmSetHighVectors) | |
1bfda055 | 39 | GCC_ASM_EXPORT (ArmV7AllDataCachesOperation) |
40 | GCC_ASM_EXPORT (ArmDataMemoryBarrier) | |
41 | GCC_ASM_EXPORT (ArmDataSyncronizationBarrier) | |
42 | GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier) | |
43 | GCC_ASM_EXPORT (ArmWriteNsacr) | |
44 | GCC_ASM_EXPORT (ArmWriteScr) | |
45 | GCC_ASM_EXPORT (ArmWriteVMBar) | |
46 | GCC_ASM_EXPORT (ArmWriteVBar) | |
47 | GCC_ASM_EXPORT (ArmWriteCPACR) | |
48 | GCC_ASM_EXPORT (ArmEnableVFP) | |
49 | GCC_ASM_EXPORT (ArmCallWFI) | |
50 | GCC_ASM_EXPORT (ArmWriteAuxCr) | |
51 | GCC_ASM_EXPORT (ArmReadAuxCr) | |
52 | GCC_ASM_EXPORT (ArmReadCbar) | |
53 | GCC_ASM_EXPORT (ArmInvalidateInstructionAndDataTlb) | |
54 | GCC_ASM_EXPORT (ArmReadMpidr) | |
0530bfe3 | 55 | GCC_ASM_EXPORT (ArmReadTpidrurw) |
56 | GCC_ASM_EXPORT (ArmWriteTpidrurw) | |
1bfda055 | 57 | |
2ef2b01e A |
58 | .set DC_ON, (0x1<<2) |
59 | .set IC_ON, (0x1<<12) | |
1bfda055 | 60 | .set CTRL_M_BIT, (1 << 0) |
61 | .set CTRL_C_BIT, (1 << 2) | |
62 | .set CTRL_B_BIT, (1 << 7) | |
63 | .set CTRL_I_BIT, (1 << 12) | |
2ef2b01e | 64 | |
7800c283 | 65 | |
2ef2b01e | 66 | ASM_PFX(ArmInvalidateDataCacheEntryByMVA): |
98bc0c8c | 67 | mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line |
68 | dsb | |
69 | isb | |
2ef2b01e A |
70 | bx lr |
71 | ||
2ef2b01e A |
72 | ASM_PFX(ArmCleanDataCacheEntryByMVA): |
73 | mcr p15, 0, r0, c7, c10, 1 @clean single data cache line | |
98bc0c8c | 74 | dsb |
75 | isb | |
2ef2b01e A |
76 | bx lr |
77 | ||
78 | ||
79 | ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA): | |
80 | mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line | |
98bc0c8c | 81 | dsb |
82 | isb | |
2ef2b01e A |
83 | bx lr |
84 | ||
85 | ||
86 | ASM_PFX(ArmInvalidateDataCacheEntryBySetWay): | |
2ac288f9 | 87 | mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line |
98bc0c8c | 88 | dsb |
89 | isb | |
2ef2b01e A |
90 | bx lr |
91 | ||
92 | ||
93 | ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay): | |
2ac288f9 | 94 | mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line |
98bc0c8c | 95 | dsb |
96 | isb | |
2ef2b01e A |
97 | bx lr |
98 | ||
99 | ||
100 | ASM_PFX(ArmCleanDataCacheEntryBySetWay): | |
2ac288f9 | 101 | mcr p15, 0, r0, c7, c10, 2 @ Clean this line |
98bc0c8c | 102 | dsb |
103 | isb | |
2ef2b01e A |
104 | bx lr |
105 | ||
2ef2b01e | 106 | ASM_PFX(ArmInvalidateInstructionCache): |
2ef2b01e | 107 | mcr p15,0,R0,c7,c5,0 @Invalidate entire instruction cache |
98bc0c8c | 108 | dsb |
109 | isb | |
2ef2b01e A |
110 | bx LR |
111 | ||
112 | ASM_PFX(ArmEnableMmu): | |
113 | mrc p15,0,R0,c1,c0,0 | |
114 | orr R0,R0,#1 | |
115 | mcr p15,0,R0,c1,c0,0 | |
548af3e7 | 116 | dsb |
117 | isb | |
2ef2b01e A |
118 | bx LR |
119 | ||
c2b5ca8b | 120 | |
2ef2b01e | 121 | ASM_PFX(ArmDisableMmu): |
2ef2b01e A |
122 | mrc p15,0,R0,c1,c0,0 |
123 | bic R0,R0,#1 | |
124 | mcr p15,0,R0,c1,c0,0 @Disable MMU | |
7800c283 | 125 | |
2ac288f9 | 126 | mcr p15,0,R0,c8,c7,0 @Invalidate TLB |
7800c283 | 127 | mcr p15,0,R0,c7,c5,6 @Invalidate Branch predictor array |
98bc0c8c | 128 | dsb |
129 | isb | |
2ef2b01e A |
130 | bx LR |
131 | ||
1bfda055 | 132 | ASM_PFX(ArmDisableCachesAndMmu): |
133 | mrc p15, 0, r0, c1, c0, 0 @ Get control register | |
134 | bic r0, r0, #CTRL_M_BIT @ Disable MMU | |
135 | bic r0, r0, #CTRL_C_BIT @ Disable D Cache | |
136 | bic r0, r0, #CTRL_I_BIT @ Disable I Cache | |
137 | mcr p15, 0, r0, c1, c0, 0 @ Write control register | |
138 | dsb | |
139 | isb | |
140 | bx LR | |
141 | ||
142 | ASM_PFX(ArmMmuEnabled): | |
143 | mrc p15,0,R0,c1,c0,0 | |
144 | and R0,R0,#1 | |
145 | bx LR | |
146 | ||
2ef2b01e A |
147 | ASM_PFX(ArmEnableDataCache): |
148 | ldr R1,=DC_ON | |
149 | mrc p15,0,R0,c1,c0,0 @Read control register configuration data | |
150 | orr R0,R0,R1 @Set C bit | |
151 | mcr p15,0,r0,c1,c0,0 @Write control register configuration data | |
98bc0c8c | 152 | dsb |
153 | isb | |
2ef2b01e A |
154 | bx LR |
155 | ||
156 | ASM_PFX(ArmDisableDataCache): | |
157 | ldr R1,=DC_ON | |
158 | mrc p15,0,R0,c1,c0,0 @Read control register configuration data | |
159 | bic R0,R0,R1 @Clear C bit | |
160 | mcr p15,0,r0,c1,c0,0 @Write control register configuration data | |
98bc0c8c | 161 | dsb |
162 | isb | |
2ef2b01e A |
163 | bx LR |
164 | ||
165 | ASM_PFX(ArmEnableInstructionCache): | |
166 | ldr R1,=IC_ON | |
167 | mrc p15,0,R0,c1,c0,0 @Read control register configuration data | |
168 | orr R0,R0,R1 @Set I bit | |
169 | mcr p15,0,r0,c1,c0,0 @Write control register configuration data | |
98bc0c8c | 170 | dsb |
171 | isb | |
2ef2b01e A |
172 | bx LR |
173 | ||
174 | ASM_PFX(ArmDisableInstructionCache): | |
175 | ldr R1,=IC_ON | |
176 | mrc p15,0,R0,c1,c0,0 @Read control register configuration data | |
177 | bic R0,R0,R1 @Clear I bit. | |
178 | mcr p15,0,r0,c1,c0,0 @Write control register configuration data | |
98bc0c8c | 179 | dsb |
180 | isb | |
2ef2b01e A |
181 | bx LR |
182 | ||
1bfda055 | 183 | ASM_PFX(ArmEnableSWPInstruction): |
184 | mrc p15, 0, r0, c1, c0, 0 | |
185 | orr r0, r0, #0x00000400 | |
186 | mcr p15, 0, r0, c1, c0, 0 | |
187 | isb | |
188 | bx LR | |
189 | ||
2ef2b01e A |
190 | ASM_PFX(ArmEnableBranchPrediction): |
191 | mrc p15, 0, r0, c1, c0, 0 | |
192 | orr r0, r0, #0x00000800 | |
193 | mcr p15, 0, r0, c1, c0, 0 | |
98bc0c8c | 194 | dsb |
195 | isb | |
2ef2b01e A |
196 | bx LR |
197 | ||
198 | ASM_PFX(ArmDisableBranchPrediction): | |
199 | mrc p15, 0, r0, c1, c0, 0 | |
200 | bic r0, r0, #0x00000800 | |
201 | mcr p15, 0, r0, c1, c0, 0 | |
98bc0c8c | 202 | dsb |
203 | isb | |
2ef2b01e A |
204 | bx LR |
205 | ||
f0fef790 | 206 | ASM_PFX(ArmSetLowVectors): |
207 | mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data) | |
208 | bic r0, r0, #0x00002000 @ clear V bit | |
209 | mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data) | |
210 | isb | |
211 | bx LR | |
212 | ||
213 | ASM_PFX(ArmSetHighVectors): | |
214 | mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data) | |
215 | orr r0, r0, #0x00002000 @ clear V bit | |
216 | mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data) | |
217 | isb | |
218 | bx LR | |
98bc0c8c | 219 | |
220 | ASM_PFX(ArmV7AllDataCachesOperation): | |
221 | stmfd SP!,{r4-r12, LR} | |
222 | mov R1, R0 @ Save Function call in R1 | |
223 | mrc p15, 1, R6, c0, c0, 1 @ Read CLIDR | |
224 | ands R3, R6, #0x7000000 @ Mask out all but Level of Coherency (LoC) | |
225 | mov R3, R3, LSR #23 @ Cache level value (naturally aligned) | |
226 | beq L_Finished | |
227 | mov R10, #0 | |
228 | ||
229 | Loop1: | |
230 | add R2, R10, R10, LSR #1 @ Work out 3xcachelevel | |
231 | mov R12, R6, LSR R2 @ bottom 3 bits are the Cache type for this level | |
232 | and R12, R12, #7 @ get those 3 bits alone | |
233 | cmp R12, #2 | |
234 | blt L_Skip @ no cache or only instruction cache at this level | |
235 | mcr p15, 2, R10, c0, c0, 0 @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction | |
548af3e7 | 236 | isb @ isb to sync the change to the CacheSizeID reg |
237 | mrc p15, 1, R12, c0, c0, 0 @ reads current Cache Size ID register (CCSIDR) | |
98bc0c8c | 238 | and R2, R12, #0x7 @ extract the line length field |
548af3e7 | 239 | add R2, R2, #4 @ add 4 for the line length offset (log2 16 bytes) |
240 | @ ldr R4, =0x3FF | |
98bc0c8c | 241 | mov R4, #0x400 |
242 | sub R4, R4, #1 | |
243 | ands R4, R4, R12, LSR #3 @ R4 is the max number on the way size (right aligned) | |
244 | clz R5, R4 @ R5 is the bit position of the way size increment | |
548af3e7 | 245 | @ ldr R7, =0x00007FFF |
98bc0c8c | 246 | mov R7, #0x00008000 |
247 | sub R7, R7, #1 | |
248 | ands R7, R7, R12, LSR #13 @ R7 is the max number of the index size (right aligned) | |
249 | ||
250 | Loop2: | |
251 | mov R9, R4 @ R9 working copy of the max way size (right aligned) | |
252 | ||
253 | Loop3: | |
254 | orr R0, R10, R9, LSL R5 @ factor in the way number and cache number into R11 | |
255 | orr R0, R0, R7, LSL R2 @ factor in the index number | |
256 | ||
257 | blx R1 | |
258 | ||
259 | subs R9, R9, #1 @ decrement the way number | |
260 | bge Loop3 | |
261 | subs R7, R7, #1 @ decrement the index | |
262 | bge Loop2 | |
263 | L_Skip: | |
264 | add R10, R10, #2 @ increment the cache number | |
265 | cmp R3, R10 | |
266 | bgt Loop1 | |
267 | ||
268 | L_Finished: | |
7800c283 | 269 | dsb |
98bc0c8c | 270 | ldmfd SP!, {r4-r12, lr} |
271 | bx LR | |
272 | ||
026c3d34 | 273 | ASM_PFX(ArmDataMemoryBarrier): |
274 | dmb | |
275 | bx LR | |
276 | ||
277 | ASM_PFX(ArmDataSyncronizationBarrier): | |
7800c283 | 278 | ASM_PFX(ArmDrainWriteBuffer): |
026c3d34 | 279 | dsb |
280 | bx LR | |
281 | ||
282 | ASM_PFX(ArmInstructionSynchronizationBarrier): | |
283 | isb | |
284 | bx LR | |
285 | ||
1bfda055 | 286 | ASM_PFX(ArmWriteNsacr): |
287 | mcr p15, 0, r0, c1, c1, 2 | |
288 | bx lr | |
289 | ||
290 | ASM_PFX(ArmWriteScr): | |
291 | mcr p15, 0, r0, c1, c1, 0 | |
292 | bx lr | |
293 | ||
294 | ASM_PFX(ArmWriteAuxCr): | |
295 | mcr p15, 0, r0, c1, c0, 1 | |
296 | bx lr | |
297 | ||
298 | ASM_PFX(ArmReadAuxCr): | |
299 | mrc p15, 0, r0, c1, c0, 1 | |
300 | bx lr | |
301 | ||
302 | ASM_PFX(ArmWriteVMBar): | |
303 | mcr p15, 0, r0, c12, c0, 1 | |
304 | bx lr | |
305 | ||
306 | ASM_PFX(ArmWriteVBar): | |
f0fef790 | 307 | # Set the Address of the Vector Table in the VBAR register |
1bfda055 | 308 | mcr p15, 0, r0, c12, c0, 0 |
f0fef790 | 309 | # Ensure the SCTLR.V bit is clear |
310 | mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data) | |
311 | bic r0, r0, #0x00002000 @ clear V bit | |
312 | mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data) | |
313 | isb | |
1bfda055 | 314 | bx lr |
315 | ||
316 | ASM_PFX(ArmWriteCPACR): | |
317 | mcr p15, 0, r0, c1, c0, 2 | |
318 | bx lr | |
319 | ||
320 | ASM_PFX(ArmEnableVFP): | |
4705b7da | 321 | # Read CPACR (Coprocessor Access Control Register) |
1bfda055 | 322 | mrc p15, 0, r0, c1, c0, 2 |
4705b7da | 323 | # Enable VPF access (Full Access to CP10, CP11) (V* instructions) |
324 | orr r0, r0, #0x00f00000 | |
325 | # Write back CPACR (Coprocessor Access Control Register) | |
1bfda055 | 326 | mcr p15, 0, r0, c1, c0, 2 |
4705b7da | 327 | # Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally. |
328 | mov r0, #0x40000000 | |
329 | mcr p10,#0x7,r0,c8,c0,#0 | |
1bfda055 | 330 | bx lr |
331 | ||
332 | ASM_PFX(ArmCallWFI): | |
333 | wfi | |
334 | bx lr | |
335 | ||
63adfb11 | 336 | #Note: Return 0 in Uniprocessor implementation |
1bfda055 | 337 | ASM_PFX(ArmReadCbar): |
63adfb11 | 338 | mrc p15, 4, r0, c15, c0, 0 @ Read Configuration Base Address Register |
1bfda055 | 339 | bx lr |
340 | ||
341 | ASM_PFX(ArmInvalidateInstructionAndDataTlb): | |
342 | mcr p15, 0, r0, c8, c7, 0 @ Invalidate Inst TLB and Data TLB | |
343 | dsb | |
344 | bx lr | |
345 | ||
346 | ASM_PFX(ArmReadMpidr): | |
2ac288f9 | 347 | mrc p15, 0, r0, c0, c0, 5 @ read MPIDR |
1bfda055 | 348 | bx lr |
0530bfe3 | 349 | |
350 | ASM_PFX(ArmReadTpidrurw): | |
351 | mrc p15, 0, r0, c13, c0, 2 @ read TPIDRURW | |
352 | bx lr | |
353 | ||
354 | ASM_PFX(ArmWriteTpidrurw): | |
355 | mcr p15, 0, r0, c13, c0, 2 @ write TPIDRURW | |
356 | bx lr | |
98bc0c8c | 357 | |
2ef2b01e | 358 | ASM_FUNCTION_REMOVE_IF_UNREFERENCED |