Fixes to get CodeSourcery GCC and RVCT 3.1 compiling.
[mirror_edk2.git] / ArmPkg / Library / ArmLib / Common / ArmLibSupport.asm
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1//------------------------------------------------------------------------------
2//
d6ebcab7 3// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
2ef2b01e 4//
d6ebcab7 5// This program and the accompanying materials
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6// are licensed and made available under the terms and conditions of the BSD License
7// which accompanies this distribution. The full text of the license may be found at
8// http://opensource.org/licenses/bsd-license.php
9//
10// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12//
13//------------------------------------------------------------------------------
14
507ebc1a 15#include <AsmMacroIoLib.h>
16
17 INCLUDE AsmMacroIoLib.inc
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18
19 EXPORT Cp15IdCode
20 EXPORT Cp15CacheInfo
1bfda055 21 EXPORT ArmIsMPCore
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22 EXPORT ArmEnableInterrupts
23 EXPORT ArmDisableInterrupts
24 EXPORT ArmGetInterruptState
0416278c 25 EXPORT ArmEnableFiq
26 EXPORT ArmDisableFiq
27 EXPORT ArmGetFiqState
2ef2b01e 28 EXPORT ArmInvalidateTlb
1bfda055 29 EXPORT ArmSetTTBR0
30 EXPORT ArmGetTTBR0BaseAddress
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31 EXPORT ArmSetDomainAccessControl
32 EXPORT CPSRMaskInsert
33 EXPORT CPSRRead
34
35 AREA ArmLibSupport, CODE, READONLY
36
37Cp15IdCode
38 mrc p15,0,R0,c0,c0,0
39 bx LR
40
41Cp15CacheInfo
42 mrc p15,0,R0,c0,c0,1
43 bx LR
44
1bfda055 45ArmIsMPCore
46 mrc p15,0,R0,c0,c0,5
507ebc1a 47 // Get Multiprocessing extension (bit31) & U bit (bit30)
1bfda055 48 and R0, R0, #0xC0000000
507ebc1a 49 // if bit30 == 0 then the processor is part of a multiprocessor system)
1bfda055 50 and R0, R0, #0x80000000
51 bx LR
52
2ef2b01e 53ArmEnableInterrupts
2ac288f9 54 mrs R0,CPSR
55 bic R0,R0,#0x80 ;Enable IRQ interrupts
56 msr CPSR_c,R0
57 bx LR
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58
59ArmDisableInterrupts
2ac288f9 60 mrs R0,CPSR
61 orr R1,R0,#0x80 ;Disable IRQ interrupts
62 msr CPSR_c,R1
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63 tst R0,#0x80
64 moveq R0,#1
65 movne R0,#0
2ac288f9 66 bx LR
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67
68ArmGetInterruptState
2ac288f9 69 mrs R0,CPSR
70 tst R0,#0x80 ;Check if IRQ is enabled.
71 moveq R0,#1
72 movne R0,#0
73 bx LR
0416278c 74
75ArmEnableFiq
2ac288f9 76 mrs R0,CPSR
77 bic R0,R0,#0x40 ;Enable IRQ interrupts
78 msr CPSR_c,R0
79 bx LR
0416278c 80
81ArmDisableFiq
2ac288f9 82 mrs R0,CPSR
83 orr R1,R0,#0x40 ;Disable IRQ interrupts
84 msr CPSR_c,R1
0416278c 85 tst R0,#0x40
86 moveq R0,#1
87 movne R0,#0
2ac288f9 88 bx LR
0416278c 89
90ArmGetFiqState
2ac288f9 91 mrs R0,CPSR
92 tst R0,#0x40 ;Check if IRQ is enabled.
93 moveq R0,#1
94 movne R0,#0
95 bx LR
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96
97ArmInvalidateTlb
98 mov r0,#0
99 mcr p15,0,r0,c8,c7,0
100 bx lr
101
1bfda055 102ArmSetTTBR0
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103 mcr p15,0,r0,c2,c0,0
104 bx lr
105
1bfda055 106ArmGetTTBR0BaseAddress
c2b5ca8b 107 mrc p15,0,r0,c2,c0,0
507ebc1a 108 LoadConstantToReg(0xFFFFC000,r1) // and r0, r0, #0xFFFFC000
109 and r0, r0, r1
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110 bx lr
111
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112ArmSetDomainAccessControl
113 mcr p15,0,r0,c3,c0,0
114 bx lr
115
116CPSRMaskInsert ; on entry, r0 is the mask and r1 is the field to insert
117 stmfd sp!, {r4-r12, lr} ; save all the banked registers
118 mov r3, sp ; copy the stack pointer into a non-banked register
119 mrs r2, cpsr ; read the cpsr
120 bic r2, r2, r0 ; clear mask in the cpsr
121 and r1, r1, r0 ; clear bits outside the mask in the input
122 orr r2, r2, r1 ; set field
123 msr cpsr_cxsf, r2 ; write back cpsr (may have caused a mode switch)
124 mov sp, r3 ; restore stack pointer
125 ldmfd sp!, {r4-r12, lr} ; restore registers
126 bx lr ; return (hopefully thumb-safe!)
127
128CPSRRead
129 mrs r0, cpsr
130 bx lr
131
132 END
133
134