ArmPkg/ArmMmuLib ARM: split ArmMmuLibCore.c into core and update code

[mirror_edk2.git] / ArmPkg / Library / ArmMmuLib / Arm / ArmMmuLibCore.c

/** @file\r
*  File managing the MMU for ARMv7 architecture\r
*\r
*  Copyright (c) 2011-2016, ARM Limited. All rights reserved.\r
*\r
*  SPDX-License-Identifier: BSD-2-Clause-Patent\r
*\r
**/\r
\r
#include <Uefi.h>\r
#include <Chipset/ArmV7.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/CacheMaintenanceLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/ArmLib.h>\r
#include <Library/BaseLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/PcdLib.h>\r
\r
#define ID_MMFR0_SHARELVL_SHIFT       12\r
#define ID_MMFR0_SHARELVL_MASK       0xf\r
#define ID_MMFR0_SHARELVL_ONE          0\r
#define ID_MMFR0_SHARELVL_TWO          1\r
\r
#define ID_MMFR0_INNERSHR_SHIFT       28\r
#define ID_MMFR0_INNERSHR_MASK       0xf\r
#define ID_MMFR0_OUTERSHR_SHIFT        8\r
#define ID_MMFR0_OUTERSHR_MASK       0xf\r
\r
#define ID_MMFR0_SHR_IMP_UNCACHED      0\r
#define ID_MMFR0_SHR_IMP_HW_COHERENT   1\r
#define ID_MMFR0_SHR_IGNORED         0xf\r
\r
UINTN\r
EFIAPI\r
ArmReadIdMmfr0 (\r
  VOID\r
  );\r
\r
BOOLEAN\r
EFIAPI\r
ArmHasMpExtensions (\r
  VOID\r
  );\r
\r
STATIC\r
BOOLEAN\r
PreferNonshareableMemory (\r
  VOID\r
  )\r
{\r
  UINTN   Mmfr;\r
  UINTN   Val;\r
\r
  if (FeaturePcdGet (PcdNormalMemoryNonshareableOverride)) {\r
    return TRUE;\r
  }\r
\r
  //\r
  // Check whether the innermost level of shareability (the level we will use\r
  // by default to map normal memory) is implemented with hardware coherency\r
  // support. Otherwise, revert to mapping as non-shareable.\r
  //\r
  Mmfr = ArmReadIdMmfr0 ();\r
  switch ((Mmfr >> ID_MMFR0_SHARELVL_SHIFT) & ID_MMFR0_SHARELVL_MASK) {\r
  case ID_MMFR0_SHARELVL_ONE:\r
    // one level of shareability\r
    Val = (Mmfr >> ID_MMFR0_OUTERSHR_SHIFT) & ID_MMFR0_OUTERSHR_MASK;\r
    break;\r
  case ID_MMFR0_SHARELVL_TWO:\r
    // two levels of shareability\r
    Val = (Mmfr >> ID_MMFR0_INNERSHR_SHIFT) & ID_MMFR0_INNERSHR_MASK;\r
    break;\r
  default:\r
    // unexpected value -> shareable is the safe option\r
    ASSERT (FALSE);\r
    return FALSE;\r
  }\r
  return Val != ID_MMFR0_SHR_IMP_HW_COHERENT;\r
}\r
\r
STATIC\r
VOID\r
PopulateLevel2PageTable (\r
  IN UINT32                         *SectionEntry,\r
  IN UINT32                         PhysicalBase,\r
  IN UINT32                         RemainLength,\r
  IN ARM_MEMORY_REGION_ATTRIBUTES   Attributes\r
  )\r
{\r
  UINT32* PageEntry;\r
  UINT32  Pages;\r
  UINT32  Index;\r
  UINT32  PageAttributes;\r
  UINT32  SectionDescriptor;\r
  UINT32  TranslationTable;\r
  UINT32  BaseSectionAddress;\r
  UINT32  FirstPageOffset;\r
\r
  switch (Attributes) {\r
    case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:\r
    case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:\r
      PageAttributes = TT_DESCRIPTOR_PAGE_WRITE_BACK;\r
      break;\r
    case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE:\r
    case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE:\r
      PageAttributes = TT_DESCRIPTOR_PAGE_WRITE_BACK;\r
      PageAttributes &= ~TT_DESCRIPTOR_PAGE_S_SHARED;\r
      break;\r
    case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:\r
    case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:\r
      PageAttributes = TT_DESCRIPTOR_PAGE_WRITE_THROUGH;\r
      break;\r
    case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:\r
    case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE:\r
      PageAttributes = TT_DESCRIPTOR_PAGE_DEVICE;\r
      break;\r
    case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:\r
    case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:\r
      PageAttributes = TT_DESCRIPTOR_PAGE_UNCACHED;\r
      break;\r
    default:\r
      PageAttributes = TT_DESCRIPTOR_PAGE_UNCACHED;\r
      break;\r
  }\r
\r
  if (PreferNonshareableMemory ()) {\r
    PageAttributes &= ~TT_DESCRIPTOR_PAGE_S_SHARED;\r
  }\r
\r
  // Check if the Section Entry has already been populated. Otherwise attach a\r
  // Level 2 Translation Table to it\r
  if (*SectionEntry != 0) {\r
    // The entry must be a page table. Otherwise it exists an overlapping in the memory map\r
    if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(*SectionEntry)) {\r
      TranslationTable = *SectionEntry & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK;\r
    } else if ((*SectionEntry & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SECTION) {\r
      // Case where a virtual memory map descriptor overlapped a section entry\r
\r
      // Allocate a Level2 Page Table for this Section\r
      TranslationTable = (UINTN)AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_PAGE_SIZE + TRANSLATION_TABLE_PAGE_ALIGNMENT));\r
      TranslationTable = ((UINTN)TranslationTable + TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK;\r
\r
      // Translate the Section Descriptor into Page Descriptor\r
      SectionDescriptor = TT_DESCRIPTOR_PAGE_TYPE_PAGE | ConvertSectionAttributesToPageAttributes (*SectionEntry, FALSE);\r
\r
      BaseSectionAddress = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(*SectionEntry);\r
\r
      // Populate the new Level2 Page Table for the section\r
      PageEntry = (UINT32*)TranslationTable;\r
      for (Index = 0; Index < TRANSLATION_TABLE_PAGE_COUNT; Index++) {\r
        PageEntry[Index] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(BaseSectionAddress + (Index << 12)) | SectionDescriptor;\r
      }\r
\r
      // Overwrite the section entry to point to the new Level2 Translation Table\r
      *SectionEntry = (TranslationTable & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) |\r
          (IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(Attributes) ? (1 << 3) : 0) |\r
          TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;\r
    } else {\r
      // We do not support the other section type (16MB Section)\r
      ASSERT(0);\r
      return;\r
    }\r
  } else {\r
    TranslationTable = (UINTN)AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_PAGE_SIZE + TRANSLATION_TABLE_PAGE_ALIGNMENT));\r
    TranslationTable = ((UINTN)TranslationTable + TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK;\r
\r
    ZeroMem ((VOID *)TranslationTable, TRANSLATION_TABLE_PAGE_SIZE);\r
\r
    *SectionEntry = (TranslationTable & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) |\r
        (IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(Attributes) ? (1 << 3) : 0) |\r
        TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;\r
  }\r
\r
  FirstPageOffset = (PhysicalBase & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT;\r
  PageEntry = (UINT32 *)TranslationTable + FirstPageOffset;\r
  Pages     = RemainLength / TT_DESCRIPTOR_PAGE_SIZE;\r
\r
  ASSERT (FirstPageOffset + Pages <= TRANSLATION_TABLE_PAGE_COUNT);\r
\r
  for (Index = 0; Index < Pages; Index++) {\r
    *PageEntry++     =  TT_DESCRIPTOR_PAGE_BASE_ADDRESS(PhysicalBase) | PageAttributes;\r
    PhysicalBase += TT_DESCRIPTOR_PAGE_SIZE;\r
  }\r
\r
}\r
\r
STATIC\r
VOID\r
FillTranslationTable (\r
  IN  UINT32                        *TranslationTable,\r
  IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryRegion\r
  )\r
{\r
  UINT32  *SectionEntry;\r
  UINT32  Attributes;\r
  UINT32  PhysicalBase;\r
  UINT64  RemainLength;\r
  UINT32  PageMapLength;\r
\r
  ASSERT(MemoryRegion->Length > 0);\r
\r
  if (MemoryRegion->PhysicalBase >= SIZE_4GB) {\r
    return;\r
  }\r
\r
  PhysicalBase = MemoryRegion->PhysicalBase;\r
  RemainLength = MIN(MemoryRegion->Length, SIZE_4GB - PhysicalBase);\r
\r
  switch (MemoryRegion->Attributes) {\r
    case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:\r
      Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(0);\r
      break;\r
    case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE:\r
      Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(0);\r
      Attributes &= ~TT_DESCRIPTOR_SECTION_S_SHARED;\r
      break;\r
    case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:\r
      Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0);\r
      break;\r
    case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:\r
      Attributes = TT_DESCRIPTOR_SECTION_DEVICE(0);\r
      break;\r
    case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:\r
      Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);\r
      break;\r
    case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:\r
      Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(1);\r
      break;\r
    case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE:\r
      Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(1);\r
      Attributes &= ~TT_DESCRIPTOR_SECTION_S_SHARED;\r
      break;\r
    case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:\r
      Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(1);\r
      break;\r
    case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE:\r
      Attributes = TT_DESCRIPTOR_SECTION_DEVICE(1);\r
      break;\r
    case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:\r
      Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(1);\r
      break;\r
    default:\r
      Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);\r
      break;\r
  }\r
\r
  if (PreferNonshareableMemory ()) {\r
    Attributes &= ~TT_DESCRIPTOR_SECTION_S_SHARED;\r
  }\r
\r
  // Get the first section entry for this mapping\r
  SectionEntry    = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);\r
\r
  while (RemainLength != 0) {\r
    if (PhysicalBase % TT_DESCRIPTOR_SECTION_SIZE == 0 &&\r
        RemainLength >= TT_DESCRIPTOR_SECTION_SIZE) {\r
      // Case: Physical address aligned on the Section Size (1MB) && the length\r
      // is greater than the Section Size\r
      *SectionEntry++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;\r
      PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;\r
      RemainLength -= TT_DESCRIPTOR_SECTION_SIZE;\r
    } else {\r
      PageMapLength = MIN (RemainLength, TT_DESCRIPTOR_SECTION_SIZE -\r
                                         (PhysicalBase % TT_DESCRIPTOR_SECTION_SIZE));\r
\r
      // Case: Physical address aligned on the Section Size (1MB) && the length\r
      //       does not fill a section\r
      // Case: Physical address NOT aligned on the Section Size (1MB)\r
      PopulateLevel2PageTable (SectionEntry++, PhysicalBase, PageMapLength,\r
        MemoryRegion->Attributes);\r
\r
      // If it is the last entry\r
      if (RemainLength < TT_DESCRIPTOR_SECTION_SIZE) {\r
        break;\r
      }\r
\r
      PhysicalBase += PageMapLength;\r
      RemainLength -= PageMapLength;\r
    }\r
  }\r
}\r
\r
RETURN_STATUS\r
EFIAPI\r
ArmConfigureMmu (\r
  IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryTable,\r
  OUT VOID                         **TranslationTableBase OPTIONAL,\r
  OUT UINTN                         *TranslationTableSize OPTIONAL\r
  )\r
{\r
  VOID*                         TranslationTable;\r
  ARM_MEMORY_REGION_ATTRIBUTES  TranslationTableAttribute;\r
  UINT32                        TTBRAttributes;\r
\r
  // Allocate pages for translation table.\r
  TranslationTable = AllocatePages (EFI_SIZE_TO_PAGES (TRANSLATION_TABLE_SECTION_SIZE + TRANSLATION_TABLE_SECTION_ALIGNMENT));\r
  if (TranslationTable == NULL) {\r
    return RETURN_OUT_OF_RESOURCES;\r
  }\r
  TranslationTable = (VOID*)(((UINTN)TranslationTable + TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK);\r
\r
  if (TranslationTableBase != NULL) {\r
    *TranslationTableBase = TranslationTable;\r
  }\r
\r
  if (TranslationTableSize != NULL) {\r
    *TranslationTableSize = TRANSLATION_TABLE_SECTION_SIZE;\r
  }\r
\r
  ZeroMem (TranslationTable, TRANSLATION_TABLE_SECTION_SIZE);\r
\r
  // By default, mark the translation table as belonging to a uncached region\r
  TranslationTableAttribute = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;\r
  while (MemoryTable->Length != 0) {\r
    // Find the memory attribute for the Translation Table\r
    if (((UINTN)TranslationTable >= MemoryTable->PhysicalBase) && ((UINTN)TranslationTable <= MemoryTable->PhysicalBase - 1 + MemoryTable->Length)) {\r
      TranslationTableAttribute = MemoryTable->Attributes;\r
    }\r
\r
    FillTranslationTable (TranslationTable, MemoryTable);\r
    MemoryTable++;\r
  }\r
\r
  // Translate the Memory Attributes into Translation Table Register Attributes\r
  if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) ||\r
      (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK)) {\r
    TTBRAttributes = ArmHasMpExtensions () ? TTBR_MP_WRITE_BACK_ALLOC : TTBR_WRITE_BACK_ALLOC;\r
  } else {\r
    // Page tables must reside in memory mapped as write-back cacheable\r
    ASSERT (0);\r
    return RETURN_UNSUPPORTED;\r
  }\r
\r
  if (TTBRAttributes & TTBR_SHAREABLE) {\r
    if (PreferNonshareableMemory ()) {\r
      TTBRAttributes ^= TTBR_SHAREABLE;\r
    } else {\r
      //\r
      // Unlike the S bit in the short descriptors, which implies inner shareable\r
      // on an implementation that supports two levels, the meaning of the S bit\r
      // in the TTBR depends on the NOS bit, which defaults to Outer Shareable.\r
      // However, we should only set this bit after we have confirmed that the\r
      // implementation supports multiple levels, or else the NOS bit is UNK/SBZP\r
      //\r
      if (((ArmReadIdMmfr0 () >> 12) & 0xf) != 0) {\r
        TTBRAttributes |= TTBR_NOT_OUTER_SHAREABLE;\r
      }\r
    }\r
  }\r
\r
  ArmCleanInvalidateDataCache ();\r
  ArmInvalidateInstructionCache ();\r
\r
  ArmDisableDataCache ();\r
  ArmDisableInstructionCache();\r
  // TLBs are also invalidated when calling ArmDisableMmu()\r
  ArmDisableMmu ();\r
\r
  // Make sure nothing sneaked into the cache\r
  ArmCleanInvalidateDataCache ();\r
  ArmInvalidateInstructionCache ();\r
\r
  ArmSetTTBR0 ((VOID *)(UINTN)(((UINTN)TranslationTable & ~TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK) | (TTBRAttributes & 0x7F)));\r
\r
  //\r
  // The TTBCR register value is undefined at reset in the Non-Secure world.\r
  // Writing 0 has the effect of:\r
  //   Clearing EAE: Use short descriptors, as mandated by specification.\r
  //   Clearing PD0 and PD1: Translation Table Walk Disable is off.\r
  //   Clearing N: Perform all translation table walks through TTBR0.\r
  //               (0 is the default reset value in systems not implementing\r
  //               the Security Extensions.)\r
  //\r
  ArmSetTTBCR (0);\r
\r
  ArmSetDomainAccessControl (DOMAIN_ACCESS_CONTROL_NONE(15) |\r
                             DOMAIN_ACCESS_CONTROL_NONE(14) |\r
                             DOMAIN_ACCESS_CONTROL_NONE(13) |\r
                             DOMAIN_ACCESS_CONTROL_NONE(12) |\r
                             DOMAIN_ACCESS_CONTROL_NONE(11) |\r
                             DOMAIN_ACCESS_CONTROL_NONE(10) |\r
                             DOMAIN_ACCESS_CONTROL_NONE( 9) |\r
                             DOMAIN_ACCESS_CONTROL_NONE( 8) |\r
                             DOMAIN_ACCESS_CONTROL_NONE( 7) |\r
                             DOMAIN_ACCESS_CONTROL_NONE( 6) |\r
                             DOMAIN_ACCESS_CONTROL_NONE( 5) |\r
                             DOMAIN_ACCESS_CONTROL_NONE( 4) |\r
                             DOMAIN_ACCESS_CONTROL_NONE( 3) |\r
                             DOMAIN_ACCESS_CONTROL_NONE( 2) |\r
                             DOMAIN_ACCESS_CONTROL_NONE( 1) |\r
                             DOMAIN_ACCESS_CONTROL_CLIENT(0));\r
\r
  ArmEnableInstructionCache();\r
  ArmEnableDataCache();\r
  ArmEnableMmu();\r
  return RETURN_SUCCESS;\r
}\r