UefiCpuPkg: Move AsmRelocateApLoopStart from Mpfuncs.nasm to AmdSev.nasm

[mirror_edk2.git] / ArmPkg / Library / CompilerIntrinsicsLib / Arm / udivmoddi4.S

#------------------------------------------------------------------------------\r
#\r
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
#\r
# SPDX-License-Identifier: BSD-2-Clause-Patent\r
#\r
#------------------------------------------------------------------------------\r
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#include <AsmMacroIoLib.h>\r
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  .syntax unified\r
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ASM_FUNC(__udivmoddi4)\r
  stmfd  sp!, {r4, r5, r6, r7, lr}\r
  add  r7, sp, #12\r
  stmfd  sp!, {r10, r11}\r
  sub  sp, sp, #20\r
  stmia  sp, {r2-r3}\r
  ldr  r6, [sp, #48]\r
  orrs  r2, r2, r3\r
  mov  r10, r0\r
  mov  r11, r1\r
  beq  L2\r
  subs  ip, r1, #0\r
  bne  L4\r
  cmp  r3, #0\r
  bne  L6\r
  cmp  r6, #0\r
  beq  L8\r
  mov  r1, r2\r
  bl  ASM_PFX(__umodsi3)\r
  mov  r1, #0\r
  stmia  r6, {r0-r1}\r
L8:\r
  ldr  r1, [sp, #0]\r
  mov  r0, r10\r
  b  L45\r
L6:\r
  cmp  r6, #0\r
  movne  r1, #0\r
  stmiane  r6, {r0-r1}\r
  b  L2\r
L4:\r
  ldr  r1, [sp, #0]\r
  cmp  r1, #0\r
  bne  L12\r
  ldr  r2, [sp, #4]\r
  cmp  r2, #0\r
  bne  L14\r
  cmp  r6, #0\r
  beq  L16\r
  mov  r1, r2\r
  mov  r0, r11\r
  bl  ASM_PFX(__umodsi3)\r
  mov  r1, #0\r
  stmia  r6, {r0-r1}\r
L16:\r
  ldr  r1, [sp, #4]\r
  mov  r0, r11\r
L45:\r
  bl  ASM_PFX(__udivsi3)\r
L46:\r
  mov  r10, r0\r
  mov  r11, #0\r
  b  L10\r
L14:\r
  subs  r1, r0, #0\r
  bne  L18\r
  cmp  r6, #0\r
  beq  L16\r
  ldr  r1, [sp, #4]\r
  mov  r0, r11\r
  bl  ASM_PFX(__umodsi3)\r
  mov  r4, r10\r
  mov  r5, r0\r
  stmia  r6, {r4-r5}\r
  b  L16\r
L18:\r
  sub  r3, r2, #1\r
  tst  r2, r3\r
  bne  L22\r
  cmp  r6, #0\r
  movne  r4, r0\r
  andne  r5, ip, r3\r
  stmiane  r6, {r4-r5}\r
L24:\r
  rsb  r3, r2, #0\r
  and  r3, r2, r3\r
  clz  r3, r3\r
  rsb  r3, r3, #31\r
  mov  r0, ip, lsr r3\r
  b  L46\r
L22:\r
  clz  r2, r2\r
  clz  r3, ip\r
  rsb  r3, r3, r2\r
  cmp  r3, #30\r
  bhi  L48\r
  rsb  r2, r3, #31\r
  add  lr, r3, #1\r
  mov  r3, r1, asl r2\r
  str  r3, [sp, #12]\r
  mov  r3, r1, lsr lr\r
  ldr  r0, [sp, #0]\r
  mov  r5, ip, lsr lr\r
  orr  r4, r3, ip, asl r2\r
  str  r0, [sp, #8]\r
  b  L29\r
L12:\r
  ldr  r3, [sp, #4]\r
  cmp  r3, #0\r
  bne  L30\r
  sub  r3, r1, #1\r
  tst  r1, r3\r
  bne  L32\r
  cmp  r6, #0\r
  andne  r3, r3, r0\r
  movne  r2, r3\r
  movne  r3, #0\r
  stmiane  r6, {r2-r3}\r
L34:\r
  cmp  r1, #1\r
  beq  L10\r
  rsb  r3, r1, #0\r
  and  r3, r1, r3\r
  clz  r3, r3\r
  rsb  r0, r3, #31\r
  mov  r1, ip, lsr r0\r
  rsb  r3, r0, #32\r
  mov  r0, r10, lsr r0\r
  orr  ip, r0, ip, asl r3\r
  str  r1, [sp, #12]\r
  str  ip, [sp, #8]\r
  ldrd  r10, [sp, #8]\r
  b  L10\r
L32:\r
  clz  r2, r1\r
  clz  r3, ip\r
  rsb  r3, r3, r2\r
  rsb  r4, r3, #31\r
  mov  r2, r0, asl r4\r
  mvn  r1, r3\r
  and  r2, r2, r1, asr #31\r
  add  lr, r3, #33\r
  str  r2, [sp, #8]\r
  add  r2, r3, #1\r
  mov  r3, r3, asr #31\r
  and  r0, r3, r0, asl r1\r
  mov  r3, r10, lsr r2\r
  orr  r3, r3, ip, asl r4\r
  and  r3, r3, r1, asr #31\r
  orr  r0, r0, r3\r
  mov  r3, ip, lsr lr\r
  str  r0, [sp, #12]\r
  mov  r0, r10, lsr lr\r
  and  r5, r3, r2, asr #31\r
  rsb  r3, lr, #31\r
  mov  r3, r3, asr #31\r
  orr  r0, r0, ip, asl r1\r
  and  r3, r3, ip, lsr r2\r
  and  r0, r0, r2, asr #31\r
  orr  r4, r3, r0\r
  b  L29\r
L30:\r
  clz  r2, r3\r
  clz  r3, ip\r
  rsb  r3, r3, r2\r
  cmp  r3, #31\r
  bls  L37\r
L48:\r
  cmp  r6, #0\r
  stmiane  r6, {r10-r11}\r
  b  L2\r
L37:\r
  rsb  r1, r3, #31\r
  mov  r0, r0, asl r1\r
  add  lr, r3, #1\r
  mov  r2, #0\r
  str  r0, [sp, #12]\r
  mov  r0, r10, lsr lr\r
  str  r2, [sp, #8]\r
  sub  r2, r3, #31\r
  and  r0, r0, r2, asr #31\r
  mov  r3, ip, lsr lr\r
  orr  r4, r0, ip, asl r1\r
  and  r5, r3, r2, asr #31\r
L29:\r
  mov  ip, #0\r
  mov  r10, ip\r
  b  L40\r
L41:\r
  ldr  r1, [sp, #12]\r
  ldr  r2, [sp, #8]\r
  mov  r3, r4, lsr #31\r
  orr  r5, r3, r5, asl #1\r
  mov  r3, r1, lsr #31\r
  orr  r4, r3, r4, asl #1\r
  mov  r3, r2, lsr #31\r
  orr  r0, r3, r1, asl #1\r
  orr  r1, ip, r2, asl #1\r
  ldmia  sp, {r2-r3}\r
  str  r0, [sp, #12]\r
  subs  r2, r2, r4\r
  sbc  r3, r3, r5\r
  str  r1, [sp, #8]\r
  subs  r0, r2, #1\r
  sbc  r1, r3, #0\r
  mov  r2, r1, asr #31\r
  ldmia  sp, {r0-r1}\r
  mov  r3, r2\r
  and  ip, r2, #1\r
  and  r3, r3, r1\r
  and  r2, r2, r0\r
  subs  r4, r4, r2\r
  sbc  r5, r5, r3\r
  add  r10, r10, #1\r
L40:\r
  cmp  r10, lr\r
  bne  L41\r
  ldrd  r0, [sp, #8]\r
  adds  r0, r0, r0\r
  adc  r1, r1, r1\r
  cmp  r6, #0\r
  orr  r10, r0, ip\r
  mov  r11, r1\r
  stmiane  r6, {r4-r5}\r
  b  L10\r
L2:\r
  mov  r10, #0\r
  mov  r11, #0\r
L10:\r
  mov  r0, r10\r
  mov  r1, r11\r
  sub  sp, r7, #20\r
  ldmfd  sp!, {r10, r11}\r
  ldmfd  sp!, {r4, r5, r6, r7, pc}\r