[mirror_edk2.git] / ArmPlatformPkg / ArmJunoPkg / AcpiTables / AcpiSsdtRootPci.asl

/** @file\r
  Differentiated System Description Table Fields (SSDT)\r
\r
  Copyright (c) 2014-2015, ARM Ltd. All rights reserved.<BR>\r
    This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#include "ArmPlatform.h"\r
\r
/*\r
  See Reference [1] 6.2.12\r
  "There are two ways that _PRT can be used. ...\r
  In the second model, the PCI interrupts are hardwired to specific interrupt\r
  inputs on the interrupt controller and are not configurable. In this case,\r
  the Source field in _PRT does not reference a device, but instead contains\r
  the value zero, and the Source Index field contains the global system\r
  interrupt to which the PCI interrupt is hardwired."\r
*/\r
#define PRT_ENTRY(Address, Pin, Interrupt)                                                       \\r
          Package (4) {                                                                           \\r
            Address,    /* uses the same format as _ADR */                                        \\r
            Pin,        /* The PCI pin number of the device (0-INTA, 1-INTB, 2-INTC, 3-INTD). */  \\r
            Zero,       /* allocated from the global interrupt pool. */                           \\r
            Interrupt   /* global system interrupt number */                                      \\r
          }\r
\r
/*\r
  See Reference [1] 6.1.1\r
  "High word–Device #, Low word–Function #. (for example, device 3, function 2 is\r
   0x00030002). To refer to all the functions on a device #, use a function number of FFFF)."\r
*/\r
#define ROOT_PRT_ENTRY(Pin, Interrupt)   PRT_ENTRY(0x0000FFFF, Pin, Interrupt)\r
                                                    // Device 0 for Bridge.\r
\r
\r
DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_OEM_REVISION) {\r
  Scope(_SB) {\r
	//\r
	// PCI Root Complex\r
	//\r
	Device(PCI0)\r
    {\r
  		Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge\r
  		Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge\r
  		Name(_SEG, Zero) // PCI Segment Group number\r
  		Name(_BBN, Zero) // PCI Base Bus Number\r
  		Name(_CCA, 1)    // Initially mark the PCI coherent (for JunoR1)\r
\r
        // Root Complex 0\r
        Device (RP0) {\r
            Name(_ADR, 0xF0000000)    // Dev 0, Func 0\r
        }\r
\r
		// PCI Routing Table\r
		Name(_PRT, Package() {\r
			ROOT_PRT_ENTRY(0, 168),   // INTA\r
			ROOT_PRT_ENTRY(1, 169),   // INTB\r
			ROOT_PRT_ENTRY(2, 170),   // INTC\r
			ROOT_PRT_ENTRY(3, 171),   // INTD\r
		})\r
        // Root complex resources\r
		Method (_CRS, 0, Serialized) {\r
			Name (RBUF, ResourceTemplate () {\r
				WordBusNumber ( // Bus numbers assigned to this root\r
					ResourceProducer,\r
					MinFixed, MaxFixed, PosDecode,\r
					0,   // AddressGranularity\r
					0,   // AddressMinimum - Minimum Bus Number\r
					255, // AddressMaximum - Maximum Bus Number\r
					0,   // AddressTranslation - Set to 0\r
					256  // RangeLength - Number of Busses\r
				)\r
\r
				DWordMemory ( // 32-bit BAR Windows\r
					ResourceProducer, PosDecode,\r
					MinFixed, MaxFixed,\r
					Cacheable, ReadWrite,\r
					0x00000000, 							// Granularity\r
					0x50000000, 							// Min Base Address\r
					0x57FFFFFF, 							// Max Base Address\r
					0x00000000, 							// Translate\r
					0x08000000								// Length\r
				)\r
\r
				QWordMemory ( // 64-bit BAR Windows\r
					ResourceProducer, PosDecode,\r
					MinFixed, MaxFixed,\r
					Cacheable, ReadWrite,\r
					0x00000000, 							// Granularity\r
					0x4000000000, 							// Min Base Address\r
					0x40FFFFFFFF, 							// Max Base Address\r
					0x00000000, 							// Translate\r
					0x100000000								// Length\r
				)\r
\r
				DWordIo ( // IO window\r
					ResourceProducer,\r
					MinFixed,\r
					MaxFixed,\r
					PosDecode,\r
					EntireRange,\r
					0x00000000, 							// Granularity\r
					0x5f800000, 							// Min Base Address\r
					0x5fffffff, 							// Max Base Address\r
					0x5f800000, 							// Translate\r
					0x00800000  							// Length\r
				)\r
			}) // Name(RBUF)\r
\r
			Return (RBUF)\r
		} // Method(_CRS)\r
\r
		//\r
		// OS Control Handoff\r
		//\r
		Name(SUPP, Zero) // PCI _OSC Support Field value\r
		Name(CTRL, Zero) // PCI _OSC Control Field value\r
\r
		/*\r
	  See [1] 6.2.10, [2] 4.5\r
		*/\r
		Method(_OSC,4) {\r
			// Check for proper UUID\r
			If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {\r
				// Create DWord-adressable fields from the Capabilities Buffer\r
				CreateDWordField(Arg3,0,CDW1)\r
				CreateDWordField(Arg3,4,CDW2)\r
				CreateDWordField(Arg3,8,CDW3)\r
\r
				// Save Capabilities DWord2 & 3\r
				Store(CDW2,SUPP)\r
				Store(CDW3,CTRL)\r
\r
				// Only allow native hot plug control if OS supports:\r
				// * ASPM\r
				// * Clock PM\r
				// * MSI/MSI-X\r
				If(LNotEqual(And(SUPP, 0x16), 0x16)) {\r
					And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits)\r
				}\r
\r
				// Always allow native PME, AER (no dependencies)\r
\r
				// Never allow SHPC (no SHPC controller in this system)\r
				And(CTRL,0x1D,CTRL)\r
\r
#if 0\r
				If(LNot(And(CDW1,1))) {		// Query flag clear?\r
					// Disable GPEs for features granted native control.\r
					If(And(CTRL,0x01)) {	// Hot plug control granted?\r
						Store(0,HPCE)		// clear the hot plug SCI enable bit\r
						Store(1,HPCS)		// clear the hot plug SCI status bit\r
					}\r
					If(And(CTRL,0x04)) {	// PME control granted?\r
						Store(0,PMCE)		// clear the PME SCI enable bit\r
						Store(1,PMCS)		// clear the PME SCI status bit\r
					}\r
					If(And(CTRL,0x10)) {	// OS restoring PCIe cap structure?\r
						// Set status to not restore PCIe cap structure\r
						// upon resume from S3\r
						Store(1,S3CR)\r
					}\r
				}\r
#endif\r
\r
				If(LNotEqual(Arg1,One)) {	// Unknown revision\r
					Or(CDW1,0x08,CDW1)\r
				}\r
\r
				If(LNotEqual(CDW3,CTRL)) {	// Capabilities bits were masked\r
					Or(CDW1,0x10,CDW1)\r
				}\r
				// Update DWORD3 in the buffer\r
				Store(CTRL,CDW3)\r
				Return(Arg3)\r
			} Else {\r
				Or(CDW1,4,CDW1) // Unrecognized UUID\r
				Return(Arg3)\r
			}\r
		} // End _OSC\r
    } // PCI0\r
  }\r
}\r
Commit	Line	Data
ae52e921 LL	1	/** @file\r
	2	Differentiated System Description Table Fields (SSDT)\r
	3	\r
	4	Copyright (c) 2014-2015, ARM Ltd. All rights reserved.<BR>\r
	5	This program and the accompanying materials\r
	6	are licensed and made available under the terms and conditions of the BSD License\r
	7	which accompanies this distribution. The full text of the license may be found at\r
	8	http://opensource.org/licenses/bsd-license.php\r
	9	\r
	10	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	11	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	12	\r
	13	**/\r
	14	\r
	15	#include "ArmPlatform.h"\r
	16	\r
	17	/*\r
	18	See Reference [1] 6.2.12\r
	19	"There are two ways that _PRT can be used. ...\r
	20	In the second model, the PCI interrupts are hardwired to specific interrupt\r
	21	inputs on the interrupt controller and are not configurable. In this case,\r
	22	the Source field in _PRT does not reference a device, but instead contains\r
	23	the value zero, and the Source Index field contains the global system\r
	24	interrupt to which the PCI interrupt is hardwired."\r
	25	*/\r
	26	#define PRT_ENTRY(Address, Pin, Interrupt) \\r
	27	Package (4) { \\r
	28	Address, /* uses the same format as _ADR */ \\r
	29	Pin, /* The PCI pin number of the device (0-INTA, 1-INTB, 2-INTC, 3-INTD). */ \\r
	30	Zero, /* allocated from the global interrupt pool. */ \\r
	31	Interrupt /* global system interrupt number */ \\r
	32	}\r
	33	\r
	34	/*\r
	35	See Reference [1] 6.1.1\r
	36	"High word–Device #, Low word–Function #. (for example, device 3, function 2 is\r
	37	0x00030002). To refer to all the functions on a device #, use a function number of FFFF)."\r
	38	*/\r
	39	#define ROOT_PRT_ENTRY(Pin, Interrupt) PRT_ENTRY(0x0000FFFF, Pin, Interrupt)\r
	40	// Device 0 for Bridge.\r
	41	\r
	42	\r
	43	DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_OEM_REVISION) {\r
	44	Scope(_SB) {\r
	45	//\r
	46	// PCI Root Complex\r
	47	//\r
	48	Device(PCI0)\r
	49	{\r
	50	Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge\r
	51	Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge\r
	52	Name(_SEG, Zero) // PCI Segment Group number\r
	53	Name(_BBN, Zero) // PCI Base Bus Number\r
368002a3	54	Name(_CCA, 1) // Initially mark the PCI coherent (for JunoR1)\r
ae52e921 LL	55	\r
	56	// Root Complex 0\r
	57	Device (RP0) {\r
	58	Name(_ADR, 0xF0000000) // Dev 0, Func 0\r
	59	}\r
	60	\r
	61	// PCI Routing Table\r
	62	Name(_PRT, Package() {\r
	63	ROOT_PRT_ENTRY(0, 168), // INTA\r
	64	ROOT_PRT_ENTRY(1, 169), // INTB\r
	65	ROOT_PRT_ENTRY(2, 170), // INTC\r
	66	ROOT_PRT_ENTRY(3, 171), // INTD\r
	67	})\r
	68	// Root complex resources\r
	69	Method (_CRS, 0, Serialized) {\r
	70	Name (RBUF, ResourceTemplate () {\r
	71	WordBusNumber ( // Bus numbers assigned to this root\r
	72	ResourceProducer,\r
	73	MinFixed, MaxFixed, PosDecode,\r
	74	0, // AddressGranularity\r
	75	0, // AddressMinimum - Minimum Bus Number\r
	76	255, // AddressMaximum - Maximum Bus Number\r
	77	0, // AddressTranslation - Set to 0\r
	78	256 // RangeLength - Number of Busses\r
	79	)\r
	80	\r
	81	DWordMemory ( // 32-bit BAR Windows\r
	82	ResourceProducer, PosDecode,\r
	83	MinFixed, MaxFixed,\r
	84	Cacheable, ReadWrite,\r
	85	0x00000000, // Granularity\r
	86	0x50000000, // Min Base Address\r
	87	0x57FFFFFF, // Max Base Address\r
	88	0x00000000, // Translate\r
	89	0x08000000 // Length\r
	90	)\r
	91	\r
	92	QWordMemory ( // 64-bit BAR Windows\r
	93	ResourceProducer, PosDecode,\r
	94	MinFixed, MaxFixed,\r
	95	Cacheable, ReadWrite,\r
	96	0x00000000, // Granularity\r
	97	0x4000000000, // Min Base Address\r
	98	0x40FFFFFFFF, // Max Base Address\r
	99	0x00000000, // Translate\r
	100	0x100000000 // Length\r
	101	)\r
	102	\r
	103	DWordIo ( // IO window\r
	104	ResourceProducer,\r
	105	MinFixed,\r
	106	MaxFixed,\r
	107	PosDecode,\r
	108	EntireRange,\r
	109	0x00000000, // Granularity\r
	110	0x5f800000, // Min Base Address\r
	111	0x5fffffff, // Max Base Address\r
	112	0x5f800000, // Translate\r
	113	0x00800000 // Length\r
	114	)\r
	115	}) // Name(RBUF)\r
	116	\r
	117	Return (RBUF)\r
	118	} // Method(_CRS)\r
119	\r
120	//\r
121	// OS Control Handoff\r
122	//\r
123	Name(SUPP, Zero) // PCI _OSC Support Field value\r
124	Name(CTRL, Zero) // PCI _OSC Control Field value\r
125	\r
126	/*\r
127	See [1] 6.2.10, [2] 4.5\r
128	*/\r
129	Method(_OSC,4) {\r
130	// Check for proper UUID\r
131	If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {\r
132	// Create DWord-adressable fields from the Capabilities Buffer\r
133	CreateDWordField(Arg3,0,CDW1)\r
134	CreateDWordField(Arg3,4,CDW2)\r
135	CreateDWordField(Arg3,8,CDW3)\r
136	\r
137	// Save Capabilities DWord2 & 3\r
138	Store(CDW2,SUPP)\r
139	Store(CDW3,CTRL)\r
140	\r
141	// Only allow native hot plug control if OS supports:\r
142	// * ASPM\r
143	// * Clock PM\r
144	// * MSI/MSI-X\r
145	If(LNotEqual(And(SUPP, 0x16), 0x16)) {\r
146	And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits)\r
147	}\r
148	\r
149	// Always allow native PME, AER (no dependencies)\r
150	\r
151	// Never allow SHPC (no SHPC controller in this system)\r
152	And(CTRL,0x1D,CTRL)\r
153	\r
154	#if 0\r
155	If(LNot(And(CDW1,1))) { // Query flag clear?\r
156	// Disable GPEs for features granted native control.\r
157	If(And(CTRL,0x01)) { // Hot plug control granted?\r
158	Store(0,HPCE) // clear the hot plug SCI enable bit\r
159	Store(1,HPCS) // clear the hot plug SCI status bit\r
160	}\r
161	If(And(CTRL,0x04)) { // PME control granted?\r
162	Store(0,PMCE) // clear the PME SCI enable bit\r
163	Store(1,PMCS) // clear the PME SCI status bit\r
164	}\r
165	If(And(CTRL,0x10)) { // OS restoring PCIe cap structure?\r
166	// Set status to not restore PCIe cap structure\r
167	// upon resume from S3\r
168	Store(1,S3CR)\r
169	}\r
170	}\r
171	#endif\r
172	\r
173	If(LNotEqual(Arg1,One)) { // Unknown revision\r
174	Or(CDW1,0x08,CDW1)\r
175	}\r
176	\r
177	If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked\r
178	Or(CDW1,0x10,CDW1)\r
179	}\r
180	// Update DWORD3 in the buffer\r
181	Store(CTRL,CDW3)\r
182	Return(Arg3)\r
183	} Else {\r
184	Or(CDW1,4,CDW1) // Unrecognized UUID\r
185	Return(Arg3)\r
186	}\r
187	} // End _OSC\r
188	} // PCI0\r
189	}\r
190	}\r