[mirror_edk2.git] / ArmPlatformPkg / ArmPlatformPkg.dec

#/** @file\r
#\r
#  Copyright (c) 2011-2015, ARM Limited. All rights reserved.\r
#  Copyright (c) 2015, Intel Corporation. All rights reserved.\r
#\r
#  This program and the accompanying materials\r
#  are licensed and made available under the terms and conditions of the BSD License\r
#  which accompanies this distribution.  The full text of the license may be found at\r
#  http://opensource.org/licenses/bsd-license.php\r
#\r
#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
#\r
#**/\r
\r
[Defines]\r
  DEC_SPECIFICATION              = 0x00010005\r
  PACKAGE_NAME                   = ArmPlatformPkg\r
  PACKAGE_GUID                   = 3308e0a0-1d94-11e0-915c-0002a5d5c51b\r
  PACKAGE_VERSION                = 0.1\r
\r
################################################################################\r
#\r
# Include Section - list of Include Paths that are provided by this package.\r
#                   Comments are used for Keywords and Module Types.\r
#\r
# Supported Module Types:\r
#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION\r
#\r
################################################################################\r
[Includes.common]\r
  Include                        # Root include for the package\r
\r
[Guids.common]\r
  gArmPlatformTokenSpaceGuid   = { 0x9c0aaed4, 0x74c5, 0x4043, { 0xb4, 0x17, 0xa3, 0x22, 0x38, 0x14, 0xce, 0x76 } }\r
  #\r
  # Following Guid must match FILE_GUID in MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf\r
  #\r
  gVariableRuntimeDxeFileGuid = { 0xcbd2e4d5, 0x7068, 0x4ff5, { 0xb4, 0x62, 0x98, 0x22, 0xb4, 0xad, 0x8d, 0x60 } }\r
\r
  ## Include/Guid/ArmGlobalVariableHob.h\r
  gArmGlobalVariableGuid      = { 0xc3253c90, 0xa24f, 0x4599, { 0xa6, 0x64, 0x1f, 0x88, 0x13, 0x77, 0x8f, 0xc9} }\r
\r
  gArmBootMonFsFileInfoGuid   = { 0x41e26b9c, 0xada6, 0x45b3, { 0x80, 0x8e, 0x23, 0x57, 0xa3, 0x5b, 0x60, 0xd6 } }\r
\r
[Ppis]\r
  ## Include/Ppi/ArmGlobalVariable.h\r
  gArmGlobalVariablePpiGuid = { 0xab1c1816, 0xd542, 0x4e6f, {0x9b, 0x1e, 0x8e, 0xcd, 0x92, 0x53, 0xe2, 0xe7} }\r
\r
[PcdsFeatureFlag.common]\r
  # Set this PCD to TRUE to map NORFlash at 0x0. FALSE means the DRAM is mapped at 0x0.\r
  gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping|FALSE|BOOLEAN|0x00000012\r
\r
  gArmPlatformTokenSpaceGuid.PcdStandalone|TRUE|BOOLEAN|0x00000001\r
  gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|FALSE|BOOLEAN|0x00000002\r
  gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|FALSE|BOOLEAN|0x00000004\r
\r
  gArmPlatformTokenSpaceGuid.PcdNorFlashCheckBlockLocked|FALSE|BOOLEAN|0x0000003C\r
\r
  # Disable the GOP controller on ExitBootServices(). By default the value is FALSE,\r
  # we assume the OS will handle the FrameBuffer from the UEFI GOP information.\r
  gArmPlatformTokenSpaceGuid.PcdGopDisableOnExitBootServices|FALSE|BOOLEAN|0x0000003D\r
\r
  # Enable Legacy Linux support in the BDS\r
  gArmPlatformTokenSpaceGuid.PcdBdsLinuxSupport|TRUE|BOOLEAN|0x0000002E\r
\r
[PcdsFixedAtBuild.common]\r
  gArmPlatformTokenSpaceGuid.PcdCoreCount|1|UINT32|0x00000039\r
  gArmPlatformTokenSpaceGuid.PcdClusterCount|1|UINT32|0x00000038\r
\r
  # Stack for CPU Cores in Secure Mode\r
  gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0|UINT32|0x00000005\r
  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x10000|UINT32|0x00000036\r
  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize|0x1000|UINT32|0x00000006\r
\r
  # Stack for CPU Cores in Non Secure Mode\r
  gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0|UINT64|0x00000009\r
  gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000|UINT32|0x00000037\r
  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x1000|UINT32|0x0000000A\r
\r
  # Size of the region used by UEFI in permanent memory (Reserved 128MB by default)\r
  gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x08000000|UINT32|0x00000015\r
\r
  # Size to reserve in the primary core stack for PEI Global Variables\r
  #  = sizeof(UINTN) /* PcdPeiServicePtr or HobListPtr */\r
  gArmPlatformTokenSpaceGuid.PcdPeiGlobalVariableSize|0x4|UINT32|0x00000016\r
  # PeiServicePtr and HobListPtr shares the same location in the PEI Global Variable list\r
  # PeiServicePtr is only valid with PEI Core and HobListPtr only when the PEI Core is skipped.\r
  ## TO BE REMOVED\r
  ## ArmPlatformTokenSpaceGuid.PcdPeiServicePtrGlobalOffset|0x0|UINT32|0x00000017\r
  ## TO BE REMOVED\r
  ## gArmPlatformTokenSpaceGuid.PcdHobListPtrGlobalOffset|0x0|UINT32|0x00000018\r
\r
  # Size to reserve in the primary core stack for SEC Global Variables\r
  gArmPlatformTokenSpaceGuid.PcdSecGlobalVariableSize|0x0|UINT32|0x00000031\r
\r
  # Boot Monitor FileSystem\r
  gArmPlatformTokenSpaceGuid.PcdBootMonFsSupportedDevicePaths|L""|VOID*|0x0000003A\r
\r
  #\r
  # ARM Primecells\r
  #\r
\r
  ## SP804 DualTimer\r
  gArmPlatformTokenSpaceGuid.PcdSP804TimerFrequencyInMHz|1|UINT32|0x0000001D\r
  gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicInterruptNum|0|UINT32|0x0000001E\r
  gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicBase|0|UINT32|0x0000002A\r
  gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase|0|UINT32|0x0000002B\r
  gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase|0|UINT32|0x0000002C\r
\r
  ## SP805 Watchdog\r
  gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x0|UINT32|0x00000023\r
  gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz|32000|UINT32|0x00000021\r
\r
  ## PL011 UART\r
  gArmPlatformTokenSpaceGuid.PL011UartClkInHz|24000000|UINT32|0x0000001F\r
  gArmPlatformTokenSpaceGuid.PL011UartInteger|0|UINT32|0x00000020\r
  gArmPlatformTokenSpaceGuid.PL011UartFractional|0|UINT32|0x0000002D\r
\r
  ## PL061 GPIO\r
  gArmPlatformTokenSpaceGuid.PcdPL061GpioBase|0x0|UINT32|0x00000025\r
\r
  ## PL111 Lcd & HdLcd\r
  gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x0|UINT32|0x00000026\r
  gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x0|UINT32|0x00000027\r
\r
  ## PL180 MCI\r
  gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x00000000|UINT32|0x00000028\r
  gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x00000000|UINT32|0x00000029\r
\r
  #\r
  # BDS - Boot Manager\r
  #\r
  gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Platform"|VOID*|0x00000019\r
  gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Default Boot Device"|VOID*|0x0000000C\r
  gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L""|VOID*|0x0000000D\r
  gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|L""|VOID*|0x000000F\r
\r
  gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L""|VOID*|0x0000001B\r
  gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L""|VOID*|0x0000001C\r
\r
[PcdsFixedAtBuild.common,PcdsDynamic.common]\r
  ## PL031 RealTimeClock\r
  gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0|UINT32|0x00000024\r
  gArmPlatformTokenSpaceGuid.PcdPL031RtcPpmAccuracy|300000000|UINT32|0x00000022\r
\r
  #\r
  # Inclusive range of allowed PCI buses.\r
  #\r
  gArmPlatformTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x0000003E\r
  gArmPlatformTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000003F\r
\r
  #\r
  # Bases, sizes and translation offsets of IO and MMIO spaces, respectively.\r
  # Note that "IO" is just another MMIO range that simulates IO space; there\r
  # are no special instructions to access it.\r
  #\r
  # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are\r
  # specific to their containing address spaces. In order to get the physical\r
  # address for the CPU, for a given access, the respective translation value\r
  # has to be added.\r
  #\r
  # The translations always have to be initialized like this, using UINT64:\r
  #\r
  #   UINT64 IoCpuBase;     // mapping target in 64-bit cpu-physical space\r
  #   UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space\r
  #   UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space\r
  #\r
  #   PcdPciIoTranslation     = IoCpuBase     - PcdPciIoBase;\r
  #   PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;\r
  #   PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;\r
  #\r
  # because (a) the target address space (ie. the cpu-physical space) is\r
  # 64-bit, and (b) the translation values are meant as offsets for *modular*\r
  # arithmetic.\r
  #\r
  # Accordingly, the translation itself needs to be implemented as:\r
  #\r
  #   UINT64 UntranslatedIoAddress;     // input parameter\r
  #   UINT32 UntranslatedMmio32Address; // input parameter\r
  #   UINT64 UntranslatedMmio64Address; // input parameter\r
  #\r
  #   UINT64 TranslatedIoAddress;       // output parameter\r
  #   UINT64 TranslatedMmio32Address;   // output parameter\r
  #   UINT64 TranslatedMmio64Address;   // output parameter\r
  #\r
  #   TranslatedIoAddress     = UntranslatedIoAddress +\r
  #                             PcdPciIoTranslation;\r
  #   TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +\r
  #                             PcdPciMmio32Translation;\r
  #   TranslatedMmio64Address = UntranslatedMmio64Address +\r
  #                             PcdPciMmio64Translation;\r
  #\r
  #  The modular arithmetic performed in UINT64 ensures that the translation\r
  #  works correctly regardless of the relation between IoCpuBase and\r
  #  PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and\r
  #  PcdPciMmio64Base.\r
  #\r
  gArmPlatformTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000040\r
  gArmPlatformTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000041\r
  gArmPlatformTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000042\r
  gArmPlatformTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000043\r
  gArmPlatformTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000044\r
  gArmPlatformTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000045\r
  gArmPlatformTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000046\r
  gArmPlatformTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000047\r
  gArmPlatformTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000048\r
\r
[PcdsFixedAtBuild.ARM]\r
  # Stack for CPU Cores in Secure Monitor Mode\r
  gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007\r
  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x1000|UINT32|0x00000008\r
\r
[PcdsFixedAtBuild.AARCH64]\r
  # The Secure World is only running in EL3. Only one set of stacks is needed for AArch64.\r
  # The Secure stacks are described by PcdCPUCoresSecStackBase, PcdCPUCoreSecPrimaryStackSize\r
  # and PcdCPUCoreSecSecondaryStackSize\r
  gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007\r
  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x0|UINT32|0x00000008\r
\r
Commit	Line	Data
11c20f4e	1	#/** @file\r
11c20f4e	2	#\r
5c2d456b	3	# Copyright (c) 2011-2015, ARM Limited. All rights reserved.\r
ad7a56e5	4	# Copyright (c) 2015, Intel Corporation. All rights reserved.\r
11c20f4e	5	#\r
3402aac7 RC	6	# This program and the accompanying materials\r
	7	# are licensed and made available under the terms and conditions of the BSD License\r
	8	# which accompanies this distribution. The full text of the license may be found at\r
	9	# http://opensource.org/licenses/bsd-license.php\r
	10	#\r
	11	# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	12	# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
11c20f4e	13	#\r
	14	#**/\r
	15	\r
	16	[Defines]\r
	17	DEC_SPECIFICATION = 0x00010005\r
	18	PACKAGE_NAME = ArmPlatformPkg\r
3402aac7	19	PACKAGE_GUID = 3308e0a0-1d94-11e0-915c-0002a5d5c51b\r
11c20f4e	20	PACKAGE_VERSION = 0.1\r
	21	\r
	22	################################################################################\r
	23	#\r
	24	# Include Section - list of Include Paths that are provided by this package.\r
	25	# Comments are used for Keywords and Module Types.\r
	26	#\r
	27	# Supported Module Types:\r
	28	# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION\r
	29	#\r
	30	################################################################################\r
	31	[Includes.common]\r
	32	Include # Root include for the package\r
	33	\r
	34	[Guids.common]\r
	35	gArmPlatformTokenSpaceGuid = { 0x9c0aaed4, 0x74c5, 0x4043, { 0xb4, 0x17, 0xa3, 0x22, 0x38, 0x14, 0xce, 0x76 } }\r
	36	#\r
	37	# Following Guid must match FILE_GUID in MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf\r
	38	#\r
	39	gVariableRuntimeDxeFileGuid = { 0xcbd2e4d5, 0x7068, 0x4ff5, { 0xb4, 0x62, 0x98, 0x22, 0xb4, 0xad, 0x8d, 0x60 } }\r
	40	\r
8fc38a3f	41	## Include/Guid/ArmGlobalVariableHob.h\r
	42	gArmGlobalVariableGuid = { 0xc3253c90, 0xa24f, 0x4599, { 0xa6, 0x64, 0x1f, 0x88, 0x13, 0x77, 0x8f, 0xc9} }\r
	43	\r
da5daf36 HL	44	gArmBootMonFsFileInfoGuid = { 0x41e26b9c, 0xada6, 0x45b3, { 0x80, 0x8e, 0x23, 0x57, 0xa3, 0x5b, 0x60, 0xd6 } }\r
da5daf36 HL	45	\r
8fc38a3f	46	[Ppis]\r
	47	## Include/Ppi/ArmGlobalVariable.h\r
	48	gArmGlobalVariablePpiGuid = { 0xab1c1816, 0xd542, 0x4e6f, {0x9b, 0x1e, 0x8e, 0xcd, 0x92, 0x53, 0xe2, 0xe7} }\r
	49	\r
11c20f4e	50	[PcdsFeatureFlag.common]\r
	51	# Set this PCD to TRUE to map NORFlash at 0x0. FALSE means the DRAM is mapped at 0x0.\r
	52	gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping\|FALSE\|BOOLEAN\|0x00000012\r
3402aac7	53	\r
11c20f4e	54	gArmPlatformTokenSpaceGuid.PcdStandalone\|TRUE\|BOOLEAN\|0x00000001\r
	55	gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec\|FALSE\|BOOLEAN\|0x00000002\r
	56	gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores\|FALSE\|BOOLEAN\|0x00000004\r
	57	\r
68dda854	58	gArmPlatformTokenSpaceGuid.PcdNorFlashCheckBlockLocked\|FALSE\|BOOLEAN\|0x0000003C\r
d8c4bb9a OM	59	\r
	60	# Disable the GOP controller on ExitBootServices(). By default the value is FALSE,\r
	61	# we assume the OS will handle the FrameBuffer from the UEFI GOP information.\r
	62	gArmPlatformTokenSpaceGuid.PcdGopDisableOnExitBootServices\|FALSE\|BOOLEAN\|0x0000003D\r
	63	\r
5d9e9d1a OM	64	# Enable Legacy Linux support in the BDS\r
	65	gArmPlatformTokenSpaceGuid.PcdBdsLinuxSupport\|TRUE\|BOOLEAN\|0x0000002E\r
	66	\r
11c20f4e	67	[PcdsFixedAtBuild.common]\r
695df8ba	68	gArmPlatformTokenSpaceGuid.PcdCoreCount\|1\|UINT32\|0x00000039\r
2dbcb8f0	69	gArmPlatformTokenSpaceGuid.PcdClusterCount\|1\|UINT32\|0x00000038\r
3402aac7	70	\r
11c20f4e	71	# Stack for CPU Cores in Secure Mode\r
11c20f4e	72	gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase\|0\|UINT32\|0x00000005\r
2dbcb8f0	73	gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize\|0x10000\|UINT32\|0x00000036\r
2dbcb8f0	74	gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize\|0x1000\|UINT32\|0x00000006\r
11c20f4e	75	\r
11c20f4e	76	# Stack for CPU Cores in Non Secure Mode\r
bb5420bb	77	gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase\|0\|UINT64\|0x00000009\r
2dbcb8f0	78	gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize\|0x10000\|UINT32\|0x00000037\r
2dbcb8f0	79	gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize\|0x1000\|UINT32\|0x0000000A\r
3402aac7	80	\r
11c20f4e	81	# Size of the region used by UEFI in permanent memory (Reserved 128MB by default)\r
	82	gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize\|0x08000000\|UINT32\|0x00000015\r
	83	\r
	84	# Size to reserve in the primary core stack for PEI Global Variables\r
	85	# = sizeof(UINTN) /* PcdPeiServicePtr or HobListPtr */\r
	86	gArmPlatformTokenSpaceGuid.PcdPeiGlobalVariableSize\|0x4\|UINT32\|0x00000016\r
	87	# PeiServicePtr and HobListPtr shares the same location in the PEI Global Variable list\r
3402aac7	88	# PeiServicePtr is only valid with PEI Core and HobListPtr only when the PEI Core is skipped.\r
ac0a171a AB	89	## TO BE REMOVED\r
ac0a171a AB	90	## ArmPlatformTokenSpaceGuid.PcdPeiServicePtrGlobalOffset\|0x0\|UINT32\|0x00000017\r
183dda94 AB	91	## TO BE REMOVED\r
183dda94 AB	92	## gArmPlatformTokenSpaceGuid.PcdHobListPtrGlobalOffset\|0x0\|UINT32\|0x00000018\r
11c20f4e	93	\r
8fc38a3f	94	# Size to reserve in the primary core stack for SEC Global Variables\r
	95	gArmPlatformTokenSpaceGuid.PcdSecGlobalVariableSize\|0x0\|UINT32\|0x00000031\r
	96	\r
94e0955d OM	97	# Boot Monitor FileSystem\r
	98	gArmPlatformTokenSpaceGuid.PcdBootMonFsSupportedDevicePaths\|L""\|VOID*\|0x0000003A\r
	99	\r
11c20f4e	100	#\r
	101	# ARM Primecells\r
	102	#\r
	103	\r
	104	## SP804 DualTimer\r
	105	gArmPlatformTokenSpaceGuid.PcdSP804TimerFrequencyInMHz\|1\|UINT32\|0x0000001D\r
	106	gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicInterruptNum\|0\|UINT32\|0x0000001E\r
	107	gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicBase\|0\|UINT32\|0x0000002A\r
	108	gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase\|0\|UINT32\|0x0000002B\r
	109	gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase\|0\|UINT32\|0x0000002C\r
	110	\r
	111	## SP805 Watchdog\r
	112	gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase\|0x0\|UINT32\|0x00000023\r
	113	gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz\|32000\|UINT32\|0x00000021\r
	114	\r
	115	## PL011 UART\r
051e63bb	116	gArmPlatformTokenSpaceGuid.PL011UartClkInHz\|24000000\|UINT32\|0x0000001F\r
	117	gArmPlatformTokenSpaceGuid.PL011UartInteger\|0\|UINT32\|0x00000020\r
	118	gArmPlatformTokenSpaceGuid.PL011UartFractional\|0\|UINT32\|0x0000002D\r
11c20f4e	119	\r
11c20f4e	120	## PL061 GPIO\r
11c20f4e	121	gArmPlatformTokenSpaceGuid.PcdPL061GpioBase\|0x0\|UINT32\|0x00000025\r
3402aac7	122	\r
98622390	123	## PL111 Lcd & HdLcd\r
11c20f4e	124	gArmPlatformTokenSpaceGuid.PcdPL111LcdBase\|0x0\|UINT32\|0x00000026\r
11c20f4e	125	gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase\|0x0\|UINT32\|0x00000027\r
3402aac7	126	\r
11c20f4e	127	## PL180 MCI\r
	128	gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress\|0x00000000\|UINT32\|0x00000028\r
	129	gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress\|0x00000000\|UINT32\|0x00000029\r
	130	\r
	131	#\r
	132	# BDS - Boot Manager\r
	133	#\r
	134	gArmPlatformTokenSpaceGuid.PcdFirmwareVendor\|"ARM Platform"\|VOID*\|0x00000019\r
	135	gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription\|L"Default Boot Device"\|VOID*\|0x0000000C\r
	136	gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath\|L""\|VOID*\|0x0000000D\r
6bcedcec	137	gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument\|L""\|VOID*\|0x000000F\r
3402aac7	138	\r
11c20f4e	139	gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths\|L""\|VOID*\|0x0000001B\r
11c20f4e	140	gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths\|L""\|VOID*\|0x0000001C\r
1bc83266	141	\r
b4e2799b AB	142	[PcdsFixedAtBuild.common,PcdsDynamic.common]\r
	143	## PL031 RealTimeClock\r
	144	gArmPlatformTokenSpaceGuid.PcdPL031RtcBase\|0x0\|UINT32\|0x00000024\r
	145	gArmPlatformTokenSpaceGuid.PcdPL031RtcPpmAccuracy\|300000000\|UINT32\|0x00000022\r
	146	\r
e48f1f15 LE	147	#\r
	148	# Inclusive range of allowed PCI buses.\r
	149	#\r
	150	gArmPlatformTokenSpaceGuid.PcdPciBusMin\|0x0\|UINT32\|0x0000003E\r
	151	gArmPlatformTokenSpaceGuid.PcdPciBusMax\|0x0\|UINT32\|0x0000003F\r
	152	\r
	153	#\r
	154	# Bases, sizes and translation offsets of IO and MMIO spaces, respectively.\r
	155	# Note that "IO" is just another MMIO range that simulates IO space; there\r
	156	# are no special instructions to access it.\r
	157	#\r
	158	# The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are\r
	159	# specific to their containing address spaces. In order to get the physical\r
	160	# address for the CPU, for a given access, the respective translation value\r
	161	# has to be added.\r
	162	#\r
	163	# The translations always have to be initialized like this, using UINT64:\r
	164	#\r
	165	# UINT64 IoCpuBase; // mapping target in 64-bit cpu-physical space\r
	166	# UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space\r
	167	# UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space\r
	168	#\r
	169	# PcdPciIoTranslation = IoCpuBase - PcdPciIoBase;\r
	170	# PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;\r
	171	# PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;\r
	172	#\r
	173	# because (a) the target address space (ie. the cpu-physical space) is\r
	174	# 64-bit, and (b) the translation values are meant as offsets for modular\r
	175	# arithmetic.\r
	176	#\r
	177	# Accordingly, the translation itself needs to be implemented as:\r
	178	#\r
	179	# UINT64 UntranslatedIoAddress; // input parameter\r
	180	# UINT32 UntranslatedMmio32Address; // input parameter\r
	181	# UINT64 UntranslatedMmio64Address; // input parameter\r
	182	#\r
	183	# UINT64 TranslatedIoAddress; // output parameter\r
	184	# UINT64 TranslatedMmio32Address; // output parameter\r
	185	# UINT64 TranslatedMmio64Address; // output parameter\r
	186	#\r
	187	# TranslatedIoAddress = UntranslatedIoAddress +\r
	188	# PcdPciIoTranslation;\r
	189	# TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +\r
	190	# PcdPciMmio32Translation;\r
	191	# TranslatedMmio64Address = UntranslatedMmio64Address +\r
	192	# PcdPciMmio64Translation;\r
	193	#\r
	194	# The modular arithmetic performed in UINT64 ensures that the translation\r
	195	# works correctly regardless of the relation between IoCpuBase and\r
	196	# PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and\r
	197	# PcdPciMmio64Base.\r
	198	#\r
	199	gArmPlatformTokenSpaceGuid.PcdPciIoBase\|0x0\|UINT64\|0x00000040\r
	200	gArmPlatformTokenSpaceGuid.PcdPciIoSize\|0x0\|UINT64\|0x00000041\r
	201	gArmPlatformTokenSpaceGuid.PcdPciIoTranslation\|0x0\|UINT64\|0x00000042\r
	202	gArmPlatformTokenSpaceGuid.PcdPciMmio32Base\|0x0\|UINT32\|0x00000043\r
	203	gArmPlatformTokenSpaceGuid.PcdPciMmio32Size\|0x0\|UINT32\|0x00000044\r
	204	gArmPlatformTokenSpaceGuid.PcdPciMmio32Translation\|0x0\|UINT64\|0x00000045\r
	205	gArmPlatformTokenSpaceGuid.PcdPciMmio64Base\|0x0\|UINT64\|0x00000046\r
	206	gArmPlatformTokenSpaceGuid.PcdPciMmio64Size\|0x0\|UINT64\|0x00000047\r
	207	gArmPlatformTokenSpaceGuid.PcdPciMmio64Translation\|0x0\|UINT64\|0x00000048\r
	208	\r
1bc83266 HL	209	[PcdsFixedAtBuild.ARM]\r
	210	# Stack for CPU Cores in Secure Monitor Mode\r
	211	gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase\|0\|UINT32\|0x00000007\r
	212	gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize\|0x1000\|UINT32\|0x00000008\r
	213	\r
	214	[PcdsFixedAtBuild.AARCH64]\r
	215	# The Secure World is only running in EL3. Only one set of stacks is needed for AArch64.\r
	216	# The Secure stacks are described by PcdCPUCoresSecStackBase, PcdCPUCoreSecPrimaryStackSize\r
	217	# and PcdCPUCoreSecSecondaryStackSize\r
	218	gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase\|0\|UINT32\|0x00000007\r
	219	gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize\|0x0\|UINT32\|0x00000008\r
	220	\r