ArmPlaformPkg: Replaced gArmPlatformTokenSpaceGuid.PcdPlatformBootTimeOut
[mirror_edk2.git] / ArmPlatformPkg / ArmPlatformPkg.dec
CommitLineData
11c20f4e 1#/** @file\r
2#\r
5c2d456b 3# Copyright (c) 2011-2015, ARM Limited. All rights reserved.\r
11c20f4e 4#\r
3402aac7
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5# This program and the accompanying materials\r
6# are licensed and made available under the terms and conditions of the BSD License\r
7# which accompanies this distribution. The full text of the license may be found at\r
8# http://opensource.org/licenses/bsd-license.php\r
9#\r
10# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
11c20f4e 12#\r
13#**/\r
14\r
15[Defines]\r
16 DEC_SPECIFICATION = 0x00010005\r
17 PACKAGE_NAME = ArmPlatformPkg\r
3402aac7 18 PACKAGE_GUID = 3308e0a0-1d94-11e0-915c-0002a5d5c51b\r
11c20f4e 19 PACKAGE_VERSION = 0.1\r
20\r
21################################################################################\r
22#\r
23# Include Section - list of Include Paths that are provided by this package.\r
24# Comments are used for Keywords and Module Types.\r
25#\r
26# Supported Module Types:\r
27# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION\r
28#\r
29################################################################################\r
30[Includes.common]\r
31 Include # Root include for the package\r
32\r
33[Guids.common]\r
34 gArmPlatformTokenSpaceGuid = { 0x9c0aaed4, 0x74c5, 0x4043, { 0xb4, 0x17, 0xa3, 0x22, 0x38, 0x14, 0xce, 0x76 } }\r
35 #\r
36 # Following Guid must match FILE_GUID in MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf\r
37 #\r
38 gVariableRuntimeDxeFileGuid = { 0xcbd2e4d5, 0x7068, 0x4ff5, { 0xb4, 0x62, 0x98, 0x22, 0xb4, 0xad, 0x8d, 0x60 } }\r
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39 #\r
40 # Following Guid must match FILE_GUID in SecurityPkg/VariableAuthenticated/RuntimeDxe/VariableRuntimeDxe.inf\r
41 #\r
42 gVariableAuthenticatedRuntimeDxeFileGuid = { 0x2226f30f, 0x3d5b, 0x402d, {0x99, 0x36, 0xa9, 0x71, 0x84, 0xEB, 0x45, 0x16 } }\r
11c20f4e 43\r
8fc38a3f 44 ## Include/Guid/ArmGlobalVariableHob.h\r
45 gArmGlobalVariableGuid = { 0xc3253c90, 0xa24f, 0x4599, { 0xa6, 0x64, 0x1f, 0x88, 0x13, 0x77, 0x8f, 0xc9} }\r
46\r
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47 gArmBootMonFsFileInfoGuid = { 0x41e26b9c, 0xada6, 0x45b3, { 0x80, 0x8e, 0x23, 0x57, 0xa3, 0x5b, 0x60, 0xd6 } }\r
48\r
8fc38a3f 49[Ppis]\r
50 ## Include/Ppi/ArmGlobalVariable.h\r
51 gArmGlobalVariablePpiGuid = { 0xab1c1816, 0xd542, 0x4e6f, {0x9b, 0x1e, 0x8e, 0xcd, 0x92, 0x53, 0xe2, 0xe7} }\r
52\r
11c20f4e 53[PcdsFeatureFlag.common]\r
54 # Set this PCD to TRUE to map NORFlash at 0x0. FALSE means the DRAM is mapped at 0x0.\r
55 gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping|FALSE|BOOLEAN|0x00000012\r
3402aac7 56\r
11c20f4e 57 gArmPlatformTokenSpaceGuid.PcdStandalone|TRUE|BOOLEAN|0x00000001\r
58 gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|FALSE|BOOLEAN|0x00000002\r
59 gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|FALSE|BOOLEAN|0x00000004\r
60\r
68dda854 61 gArmPlatformTokenSpaceGuid.PcdNorFlashCheckBlockLocked|FALSE|BOOLEAN|0x0000003C\r
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62\r
63 # Disable the GOP controller on ExitBootServices(). By default the value is FALSE,\r
64 # we assume the OS will handle the FrameBuffer from the UEFI GOP information.\r
65 gArmPlatformTokenSpaceGuid.PcdGopDisableOnExitBootServices|FALSE|BOOLEAN|0x0000003D\r
66\r
11c20f4e 67[PcdsFixedAtBuild.common]\r
695df8ba 68 gArmPlatformTokenSpaceGuid.PcdCoreCount|1|UINT32|0x00000039\r
2dbcb8f0 69 gArmPlatformTokenSpaceGuid.PcdClusterCount|1|UINT32|0x00000038\r
3402aac7 70\r
11c20f4e 71 # Stack for CPU Cores in Secure Mode\r
72 gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0|UINT32|0x00000005\r
2dbcb8f0 73 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x10000|UINT32|0x00000036\r
74 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize|0x1000|UINT32|0x00000006\r
11c20f4e 75\r
11c20f4e 76 # Stack for CPU Cores in Non Secure Mode\r
bb5420bb 77 gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0|UINT64|0x00000009\r
2dbcb8f0 78 gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000|UINT32|0x00000037\r
79 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x1000|UINT32|0x0000000A\r
3402aac7 80\r
11c20f4e 81 # Size of the region used by UEFI in permanent memory (Reserved 128MB by default)\r
82 gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x08000000|UINT32|0x00000015\r
83\r
84 # Size to reserve in the primary core stack for PEI Global Variables\r
85 # = sizeof(UINTN) /* PcdPeiServicePtr or HobListPtr */\r
86 gArmPlatformTokenSpaceGuid.PcdPeiGlobalVariableSize|0x4|UINT32|0x00000016\r
87 # PeiServicePtr and HobListPtr shares the same location in the PEI Global Variable list\r
3402aac7 88 # PeiServicePtr is only valid with PEI Core and HobListPtr only when the PEI Core is skipped.\r
11c20f4e 89 gArmPlatformTokenSpaceGuid.PcdPeiServicePtrGlobalOffset|0x0|UINT32|0x00000017\r
90 gArmPlatformTokenSpaceGuid.PcdHobListPtrGlobalOffset|0x0|UINT32|0x00000018\r
91\r
8fc38a3f 92 # Size to reserve in the primary core stack for SEC Global Variables\r
93 gArmPlatformTokenSpaceGuid.PcdSecGlobalVariableSize|0x0|UINT32|0x00000031\r
94\r
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95 # Boot Monitor FileSystem\r
96 gArmPlatformTokenSpaceGuid.PcdBootMonFsSupportedDevicePaths|L""|VOID*|0x0000003A\r
97\r
11c20f4e 98 #\r
99 # ARM Primecells\r
100 #\r
101\r
102 ## SP804 DualTimer\r
103 gArmPlatformTokenSpaceGuid.PcdSP804TimerFrequencyInMHz|1|UINT32|0x0000001D\r
104 gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicInterruptNum|0|UINT32|0x0000001E\r
105 gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicBase|0|UINT32|0x0000002A\r
106 gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase|0|UINT32|0x0000002B\r
107 gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase|0|UINT32|0x0000002C\r
108\r
109 ## SP805 Watchdog\r
110 gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x0|UINT32|0x00000023\r
111 gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz|32000|UINT32|0x00000021\r
112\r
113 ## PL011 UART\r
051e63bb 114 gArmPlatformTokenSpaceGuid.PL011UartClkInHz|24000000|UINT32|0x0000001F\r
115 gArmPlatformTokenSpaceGuid.PL011UartInteger|0|UINT32|0x00000020\r
116 gArmPlatformTokenSpaceGuid.PL011UartFractional|0|UINT32|0x0000002D\r
11c20f4e 117\r
11c20f4e 118 ## PL061 GPIO\r
119 gArmPlatformTokenSpaceGuid.PcdPL061GpioBase|0x0|UINT32|0x00000025\r
3402aac7 120\r
98622390 121 ## PL111 Lcd & HdLcd\r
11c20f4e 122 gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x0|UINT32|0x00000026\r
123 gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x0|UINT32|0x00000027\r
3402aac7 124\r
11c20f4e 125 ## PL180 MCI\r
126 gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x00000000|UINT32|0x00000028\r
127 gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x00000000|UINT32|0x00000029\r
128\r
129 #\r
130 # BDS - Boot Manager\r
131 #\r
132 gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Platform"|VOID*|0x00000019\r
133 gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Default Boot Device"|VOID*|0x0000000C\r
134 gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L""|VOID*|0x0000000D\r
135 gArmPlatformTokenSpaceGuid.PcdDefaultBootInitrdPath|L""|VOID*|0x0000000E\r
6bcedcec 136 gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|L""|VOID*|0x000000F\r
3402aac7 137 # PcdDefaultBootType define the type of the binary pointed by PcdDefaultBootDevicePath:\r
11c20f4e 138 # - 0 = an EFI application\r
139 # - 1 = a Linux kernel with ATAG support\r
140 # - 2 = a Linux kernel with FDT support\r
141 gArmPlatformTokenSpaceGuid.PcdDefaultBootType|0|UINT32|0x00000010\r
3402aac7 142\r
11c20f4e 143 gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L""|VOID*|0x0000001B\r
144 gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L""|VOID*|0x0000001C\r
1bc83266 145\r
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146[PcdsFixedAtBuild.common,PcdsDynamic.common]\r
147 ## PL031 RealTimeClock\r
148 gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0|UINT32|0x00000024\r
149 gArmPlatformTokenSpaceGuid.PcdPL031RtcPpmAccuracy|300000000|UINT32|0x00000022\r
150\r
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151 #\r
152 # Inclusive range of allowed PCI buses.\r
153 #\r
154 gArmPlatformTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x0000003E\r
155 gArmPlatformTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000003F\r
156\r
157 #\r
158 # Bases, sizes and translation offsets of IO and MMIO spaces, respectively.\r
159 # Note that "IO" is just another MMIO range that simulates IO space; there\r
160 # are no special instructions to access it.\r
161 #\r
162 # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are\r
163 # specific to their containing address spaces. In order to get the physical\r
164 # address for the CPU, for a given access, the respective translation value\r
165 # has to be added.\r
166 #\r
167 # The translations always have to be initialized like this, using UINT64:\r
168 #\r
169 # UINT64 IoCpuBase; // mapping target in 64-bit cpu-physical space\r
170 # UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space\r
171 # UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space\r
172 #\r
173 # PcdPciIoTranslation = IoCpuBase - PcdPciIoBase;\r
174 # PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;\r
175 # PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;\r
176 #\r
177 # because (a) the target address space (ie. the cpu-physical space) is\r
178 # 64-bit, and (b) the translation values are meant as offsets for *modular*\r
179 # arithmetic.\r
180 #\r
181 # Accordingly, the translation itself needs to be implemented as:\r
182 #\r
183 # UINT64 UntranslatedIoAddress; // input parameter\r
184 # UINT32 UntranslatedMmio32Address; // input parameter\r
185 # UINT64 UntranslatedMmio64Address; // input parameter\r
186 #\r
187 # UINT64 TranslatedIoAddress; // output parameter\r
188 # UINT64 TranslatedMmio32Address; // output parameter\r
189 # UINT64 TranslatedMmio64Address; // output parameter\r
190 #\r
191 # TranslatedIoAddress = UntranslatedIoAddress +\r
192 # PcdPciIoTranslation;\r
193 # TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +\r
194 # PcdPciMmio32Translation;\r
195 # TranslatedMmio64Address = UntranslatedMmio64Address +\r
196 # PcdPciMmio64Translation;\r
197 #\r
198 # The modular arithmetic performed in UINT64 ensures that the translation\r
199 # works correctly regardless of the relation between IoCpuBase and\r
200 # PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and\r
201 # PcdPciMmio64Base.\r
202 #\r
203 gArmPlatformTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000040\r
204 gArmPlatformTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000041\r
205 gArmPlatformTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000042\r
206 gArmPlatformTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000043\r
207 gArmPlatformTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000044\r
208 gArmPlatformTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000045\r
209 gArmPlatformTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000046\r
210 gArmPlatformTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000047\r
211 gArmPlatformTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000048\r
212\r
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213[PcdsFixedAtBuild.ARM]\r
214 # Stack for CPU Cores in Secure Monitor Mode\r
215 gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007\r
216 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x1000|UINT32|0x00000008\r
217\r
218[PcdsFixedAtBuild.AARCH64]\r
219 # The Secure World is only running in EL3. Only one set of stacks is needed for AArch64.\r
220 # The Secure stacks are described by PcdCPUCoresSecStackBase, PcdCPUCoreSecPrimaryStackSize\r
221 # and PcdCPUCoreSecSecondaryStackSize\r
222 gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007\r
223 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x0|UINT32|0x00000008\r
224\r