[mirror_edk2.git] / ArmPlatformPkg / ArmVExpressPkg / Include / VExpressMotherBoard.h

/** @file\r
*  Header defining Versatile Express constants (Base addresses, sizes, flags)\r
*\r
*  Copyright (c) 2011, ARM Limited. All rights reserved.\r
*\r
*  This program and the accompanying materials\r
*  are licensed and made available under the terms and conditions of the BSD License\r
*  which accompanies this distribution.  The full text of the license may be found at\r
*  http://opensource.org/licenses/bsd-license.php\r
*\r
*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
*\r
**/\r
\r
#ifndef __VEXPRESSMOTHERBOARD_H_\r
#define __VEXPRESSMOTHERBOARD_H_\r
\r
#include <ArmPlatform.h>\r
\r
/***********************************************************************************\r
// Motherboard memory-mapped peripherals\r
************************************************************************************/\r
\r
// Define MotherBoard SYS flags offsets (from ARM_VE_BOARD_PERIPH_BASE)\r
#define ARM_VE_SYS_LED_REG                        (ARM_VE_BOARD_PERIPH_BASE + 0x00008)\r
#define ARM_VE_SYS_FLAGS_REG                      (ARM_VE_BOARD_PERIPH_BASE + 0x00030)\r
#define ARM_VE_SYS_FLAGS_SET_REG                  (ARM_VE_BOARD_PERIPH_BASE + 0x00030)\r
#define ARM_VE_SYS_FLAGS_CLR_REG                  (ARM_VE_BOARD_PERIPH_BASE + 0x00034)\r
#define ARM_VE_SYS_FLAGS_NV_REG                   (ARM_VE_BOARD_PERIPH_BASE + 0x00038)\r
#define ARM_VE_SYS_FLAGS_NV_SET_REG               (ARM_VE_BOARD_PERIPH_BASE + 0x00038)\r
#define ARM_VE_SYS_FLAGS_NV_CLR_REG               (ARM_VE_BOARD_PERIPH_BASE + 0x0003C)\r
#define ARM_VE_SYS_FLASH                          (ARM_VE_BOARD_PERIPH_BASE + 0x0004C)\r
#define ARM_VE_SYS_PROCID0_REG                    (ARM_VE_BOARD_PERIPH_BASE + 0x00084)\r
#define ARM_VE_SYS_PROCID1_REG                    (ARM_VE_BOARD_PERIPH_BASE + 0x00088)\r
#define ARM_VE_SYS_CFGDATA_REG                    (ARM_VE_BOARD_PERIPH_BASE + 0x000A0)\r
#define ARM_VE_SYS_CFGCTRL_REG                    (ARM_VE_BOARD_PERIPH_BASE + 0x000A4)\r
#define ARM_VE_SYS_CFGSTAT_REG                    (ARM_VE_BOARD_PERIPH_BASE + 0x000A8)\r
\r
// SP810 Controller\r
#define SP810_CTRL_BASE                           (ARM_VE_BOARD_PERIPH_BASE + 0x01000)\r
\r
// Uart0\r
#define PL011_CONSOLE_UART_BASE                   (ARM_VE_BOARD_PERIPH_BASE + 0x09000)\r
\r
// SP805 Watchdog on motherboard\r
#define SP805_WDOG_MOTHERBOARD_BASE               (ARM_VE_BOARD_PERIPH_BASE + 0x0F000)\r
\r
// SP804 Timer Bases\r
#define SP804_TIMER0_BASE                         (ARM_VE_BOARD_PERIPH_BASE + 0x11000)\r
#define SP804_TIMER1_BASE                         (ARM_VE_BOARD_PERIPH_BASE + 0x11020)\r
#define SP804_TIMER2_BASE                         (ARM_VE_BOARD_PERIPH_BASE + 0x12000)\r
#define SP804_TIMER3_BASE                         (ARM_VE_BOARD_PERIPH_BASE + 0x12020)\r
\r
// PL031 Real Time Clock\r
#define PL031_RTC_BASE                            (ARM_VE_BOARD_PERIPH_BASE + 0x17000)\r
\r
// PL111 Colour LCD Controller - motherboard\r
#define PL111_CLCD_MOTHERBOARD_BASE               (ARM_VE_BOARD_PERIPH_BASE + 0x1F000)\r
#define PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID  1\r
\r
// VRAM offset for the PL111 Colour LCD Controller on the motherboard\r
#define VRAM_MOTHERBOARD_BASE                     (ARM_VE_SMB_PERIPH_BASE   + 0x00000)\r
\r
#define ARM_VE_SYS_PROC_ID_MASK                   (0xFF << 24)\r
#define ARM_VE_SYS_PROC_ID_UNSUPPORTED            (0xFF << 24)\r
#define ARM_VE_SYS_PROC_ID_CORTEX_A9              (0x0C << 24)\r
#define ARM_VE_SYS_PROC_ID_CORTEX_A5              (0x12 << 24)\r
#define ARM_VE_SYS_PROC_ID_CORTEX_A15             (0x14 << 24)\r
\r
//\r
// Sites where the peripheral is fitted\r
//\r
#define ARM_VE_UNSUPPORTED                        ~0\r
#define ARM_VE_MOTHERBOARD_SITE                   0\r
#define ARM_VE_DAUGHTERBOARD_1_SITE               1\r
#define ARM_VE_DAUGHTERBOARD_2_SITE               2\r
\r
#define VIRTUAL_SYS_CFG(site,func)                (((site) << 24) | (func))\r
\r
//\r
// System Configuration Control Functions\r
//\r
#define SYS_CFG_OSC                               1\r
#define SYS_CFG_VOLT                              2\r
#define SYS_CFG_AMP                               3\r
#define SYS_CFG_TEMP                              4\r
#define SYS_CFG_RESET                             5\r
#define SYS_CFG_SCC                               6\r
#define SYS_CFG_MUXFPGA                           7\r
#define SYS_CFG_SHUTDOWN                          8\r
#define SYS_CFG_REBOOT                            9\r
#define SYS_CFG_DVIMODE                           11\r
#define SYS_CFG_POWER                             12\r
// Oscillator for Site 1\r
#define SYS_CFG_OSC_SITE1                         VIRTUAL_SYS_CFG(ARM_VE_DAUGHTERBOARD_1_SITE,SYS_CFG_OSC)\r
// Oscillator for Site 2\r
#define SYS_CFG_OSC_SITE2                         VIRTUAL_SYS_CFG(ARM_VE_DAUGHTERBOARD_2_SITE,SYS_CFG_OSC)\r
// Can not access the battery backed-up hardware clock on the Versatile Express motherboard\r
#define SYS_CFG_RTC                               VIRTUAL_SYS_CFG(ARM_VE_UNSUPPORTED,1)\r
\r
#endif /* VEXPRESSMOTHERBOARD_H_ */\r
Commit	Line	Data
76bc1743	1	/** @file\r
	2	* Header defining Versatile Express constants (Base addresses, sizes, flags)\r
	3	*\r
	4	* Copyright (c) 2011, ARM Limited. All rights reserved.\r
	5	*\r
	6	* This program and the accompanying materials\r
	7	* are licensed and made available under the terms and conditions of the BSD License\r
	8	* which accompanies this distribution. The full text of the license may be found at\r
	9	* http://opensource.org/licenses/bsd-license.php\r
	10	*\r
	11	* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	12	* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	13	*\r
	14	**/\r
	15	\r
	16	#ifndef __VEXPRESSMOTHERBOARD_H_\r
	17	#define __VEXPRESSMOTHERBOARD_H_\r
	18	\r
	19	#include <ArmPlatform.h>\r
	20	\r
	21	/***********************************************************************************\r
	22	// Motherboard memory-mapped peripherals\r
	23	************************************************************************************/\r
	24	\r
	25	// Define MotherBoard SYS flags offsets (from ARM_VE_BOARD_PERIPH_BASE)\r
	26	#define ARM_VE_SYS_LED_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00008)\r
	27	#define ARM_VE_SYS_FLAGS_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00030)\r
	28	#define ARM_VE_SYS_FLAGS_SET_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00030)\r
	29	#define ARM_VE_SYS_FLAGS_CLR_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00034)\r
	30	#define ARM_VE_SYS_FLAGS_NV_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00038)\r
	31	#define ARM_VE_SYS_FLAGS_NV_SET_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00038)\r
	32	#define ARM_VE_SYS_FLAGS_NV_CLR_REG (ARM_VE_BOARD_PERIPH_BASE + 0x0003C)\r
	33	#define ARM_VE_SYS_FLASH (ARM_VE_BOARD_PERIPH_BASE + 0x0004C)\r
	34	#define ARM_VE_SYS_PROCID0_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00084)\r
	35	#define ARM_VE_SYS_PROCID1_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00088)\r
	36	#define ARM_VE_SYS_CFGDATA_REG (ARM_VE_BOARD_PERIPH_BASE + 0x000A0)\r
	37	#define ARM_VE_SYS_CFGCTRL_REG (ARM_VE_BOARD_PERIPH_BASE + 0x000A4)\r
	38	#define ARM_VE_SYS_CFGSTAT_REG (ARM_VE_BOARD_PERIPH_BASE + 0x000A8)\r
	39	\r
	40	// SP810 Controller\r
	41	#define SP810_CTRL_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x01000)\r
	42	\r
	43	// Uart0\r
	44	#define PL011_CONSOLE_UART_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x09000)\r
	45	\r
	46	// SP805 Watchdog on motherboard\r
	47	#define SP805_WDOG_MOTHERBOARD_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x0F000)\r
	48	\r
	49	// SP804 Timer Bases\r
	50	#define SP804_TIMER0_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x11000)\r
	51	#define SP804_TIMER1_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x11020)\r
	52	#define SP804_TIMER2_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x12000)\r
	53	#define SP804_TIMER3_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x12020)\r
	54	\r
	55	// PL031 Real Time Clock\r
	56	#define PL031_RTC_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x17000)\r
	57	\r
	58	// PL111 Colour LCD Controller - motherboard\r
	59	#define PL111_CLCD_MOTHERBOARD_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x1F000)\r
	60	#define PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID 1\r
	61	\r
	62	// VRAM offset for the PL111 Colour LCD Controller on the motherboard\r
	63	#define VRAM_MOTHERBOARD_BASE (ARM_VE_SMB_PERIPH_BASE + 0x00000)\r
	64	\r
44788bae	65	#define ARM_VE_SYS_PROC_ID_MASK (0xFF << 24)\r
	66	#define ARM_VE_SYS_PROC_ID_UNSUPPORTED (0xFF << 24)\r
	67	#define ARM_VE_SYS_PROC_ID_CORTEX_A9 (0x0C << 24)\r
	68	#define ARM_VE_SYS_PROC_ID_CORTEX_A5 (0x12 << 24)\r
	69	#define ARM_VE_SYS_PROC_ID_CORTEX_A15 (0x14 << 24)\r
76bc1743	70	\r
	71	//\r
	72	// Sites where the peripheral is fitted\r
	73	//\r
	74	#define ARM_VE_UNSUPPORTED ~0\r
	75	#define ARM_VE_MOTHERBOARD_SITE 0\r
	76	#define ARM_VE_DAUGHTERBOARD_1_SITE 1\r
	77	#define ARM_VE_DAUGHTERBOARD_2_SITE 2\r
	78	\r
7b80d1a3	79	#define VIRTUAL_SYS_CFG(site,func) (((site) << 24) \| (func))\r
	80	\r
	81	//\r
	82	// System Configuration Control Functions\r
	83	//\r
	84	#define SYS_CFG_OSC 1\r
	85	#define SYS_CFG_VOLT 2\r
	86	#define SYS_CFG_AMP 3\r
	87	#define SYS_CFG_TEMP 4\r
	88	#define SYS_CFG_RESET 5\r
	89	#define SYS_CFG_SCC 6\r
	90	#define SYS_CFG_MUXFPGA 7\r
	91	#define SYS_CFG_SHUTDOWN 8\r
	92	#define SYS_CFG_REBOOT 9\r
	93	#define SYS_CFG_DVIMODE 11\r
	94	#define SYS_CFG_POWER 12\r
	95	// Oscillator for Site 1\r
	96	#define SYS_CFG_OSC_SITE1 VIRTUAL_SYS_CFG(ARM_VE_DAUGHTERBOARD_1_SITE,SYS_CFG_OSC)\r
	97	// Oscillator for Site 2\r
	98	#define SYS_CFG_OSC_SITE2 VIRTUAL_SYS_CFG(ARM_VE_DAUGHTERBOARD_2_SITE,SYS_CFG_OSC)\r
	99	// Can not access the battery backed-up hardware clock on the Versatile Express motherboard\r
	100	#define SYS_CFG_RTC VIRTUAL_SYS_CFG(ARM_VE_UNSUPPORTED,1)\r
	101	\r
76bc1743	102	#endif /* VEXPRESSMOTHERBOARD_H_ */\r