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1d5d0ae9 | 1 | /** @file |
2 | * | |
0db25ccc | 3 | * Copyright (c) 2011-2012, ARM Limited. All rights reserved. |
1d5d0ae9 | 4 | * |
5 | * This program and the accompanying materials | |
6 | * are licensed and made available under the terms and conditions of the BSD License | |
7 | * which accompanies this distribution. The full text of the license may be found at | |
8 | * http://opensource.org/licenses/bsd-license.php | |
9 | * | |
10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, | |
11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. | |
12 | * | |
13 | **/ | |
14 | ||
15 | #include <Library/IoLib.h> | |
1d5d0ae9 | 16 | #include <Library/ArmPlatformLib.h> |
17 | #include <Library/DebugLib.h> | |
18 | #include <Library/PcdLib.h> | |
23792dea | 19 | #include <Library/SerialPortLib.h> |
20 | ||
1d5d0ae9 | 21 | #include <Drivers/PL341Dmc.h> |
8e06b586 | 22 | #include <Drivers/PL301Axi.h> |
23792dea | 23 | #include <Drivers/SP804Timer.h> |
2637d1ef | 24 | |
44788bae | 25 | #include <Ppi/ArmMpCoreInfo.h> |
26 | ||
5cc45b70 | 27 | #include <ArmPlatform.h> |
28 | ||
e862cd50 | 29 | #define SerialPrint(txt) SerialPortWrite ((UINT8*)(txt), AsciiStrLen(txt)+1); |
1d5d0ae9 | 30 | |
44788bae | 31 | ARM_CORE_INFO mVersatileExpressMpCoreInfoCTA9x4[] = { |
32 | { | |
33 | // Cluster 0, Core 0 | |
34 | 0x0, 0x0, | |
35 | ||
36 | // MP Core MailBox Set/Get/Clear Addresses and Clear Value | |
37 | (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG, | |
38 | (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG, | |
39 | (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG, | |
40 | (UINT64)0xFFFFFFFF | |
41 | }, | |
42 | { | |
43 | // Cluster 0, Core 1 | |
44 | 0x0, 0x1, | |
45 | ||
46 | // MP Core MailBox Set/Get/Clear Addresses and Clear Value | |
47 | (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG, | |
48 | (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG, | |
49 | (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG, | |
50 | (UINT64)0xFFFFFFFF | |
51 | }, | |
52 | { | |
53 | // Cluster 0, Core 2 | |
54 | 0x0, 0x2, | |
55 | ||
56 | // MP Core MailBox Set/Get/Clear Addresses and Clear Value | |
57 | (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG, | |
58 | (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG, | |
59 | (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG, | |
60 | (UINT64)0xFFFFFFFF | |
61 | }, | |
62 | { | |
63 | // Cluster 0, Core 3 | |
64 | 0x0, 0x3, | |
65 | ||
66 | // MP Core MailBox Set/Get/Clear Addresses and Clear Value | |
67 | (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG, | |
68 | (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG, | |
69 | (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG, | |
70 | (UINT64)0xFFFFFFFF | |
71 | } | |
72 | }; | |
73 | ||
1d5d0ae9 | 74 | // DDR2 timings |
8be5d4d6 | 75 | PL341_DMC_CONFIG DDRTimings = { |
8be5d4d6 | 76 | .MaxChip = 1, |
77 | .IsUserCfg = TRUE, | |
78 | .User0Cfg = 0x7C924924, | |
79 | .User2Cfg = (TC_UIOLHXC_VALUE << TC_UIOLHNC_SHIFT) | (TC_UIOLHXC_VALUE << TC_UIOLHPC_SHIFT) | (0x1 << TC_UIOHOCT_SHIFT) | (0x1 << TC_UIOHSTOP_SHIFT), | |
80 | .HasQos = TRUE, | |
06a89733 | 81 | .RefreshPeriod = 0x3D0, |
82 | .CasLatency = 0x8, | |
83 | .WriteLatency = 0x3, | |
8be5d4d6 | 84 | .t_mrd = 0x2, |
85 | .t_ras = 0xA, | |
86 | .t_rc = 0xE, | |
87 | .t_rcd = 0x104, | |
88 | .t_rfc = 0x2f32, | |
89 | .t_rp = 0x14, | |
90 | .t_rrd = 0x2, | |
91 | .t_wr = 0x4, | |
92 | .t_wtr = 0x2, | |
93 | .t_xp = 0x2, | |
94 | .t_xsr = 0xC8, | |
95 | .t_esr = 0x14, | |
96 | .MemoryCfg = DMC_MEMORY_CONFIG_ACTIVE_CHIP_1 | DMC_MEMORY_CONFIG_BURST_4 | | |
97 | DMC_MEMORY_CONFIG_ROW_ADDRESS_15 | DMC_MEMORY_CONFIG_COLUMN_ADDRESS_10, | |
98 | .MemoryCfg2 = DMC_MEMORY_CFG2_DQM_INIT | DMC_MEMORY_CFG2_CKE_INIT | | |
99 | DMC_MEMORY_CFG2_BANK_BITS_3 | DMC_MEMORY_CFG2_MEM_WIDTH_32, | |
100 | .MemoryCfg3 = 0x00000001, | |
101 | .ChipCfg0 = 0x00010000, | |
102 | .t_faw = 0x00000A0D, | |
103 | .ModeReg = DDR2_MR_BURST_LENGTH_4 | DDR2_MR_CAS_LATENCY_4 | DDR2_MR_WR_CYCLES_4, | |
104 | .ExtModeReg = DDR_EMR_RTT_50R | (DDR_EMR_ODS_VAL << DDR_EMR_ODS_MASK), | |
1d5d0ae9 | 105 | }; |
106 | ||
a534d714 | 107 | /** |
108 | Return the current Boot Mode | |
109 | ||
110 | This function returns the boot reason on the platform | |
111 | ||
112 | @return Return the current Boot Mode of the platform | |
113 | ||
114 | **/ | |
115 | EFI_BOOT_MODE | |
116 | ArmPlatformGetBootMode ( | |
117 | VOID | |
118 | ) | |
119 | { | |
12c5ae23 | 120 | if (MmioRead32(ARM_VE_SYS_FLAGS_NV_REG) == 0) { |
121 | return BOOT_WITH_FULL_CONFIGURATION; | |
122 | } else { | |
123 | return BOOT_ON_S2_RESUME; | |
124 | } | |
a534d714 | 125 | } |
126 | ||
aa01abaa | 127 | /** |
128 | Initialize controllers that must setup in the normal world | |
129 | ||
5cc45b70 | 130 | This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei |
aa01abaa | 131 | in the PEI phase. |
132 | ||
133 | **/ | |
f437141a | 134 | RETURN_STATUS |
135 | ArmPlatformInitialize ( | |
136 | IN UINTN MpId | |
aa01abaa | 137 | ) |
138 | { | |
f437141a | 139 | if (!IS_PRIMARY_CORE(MpId)) { |
140 | return RETURN_SUCCESS; | |
141 | } | |
142 | ||
23792dea | 143 | // Configure periodic timer (TIMER0) for 1MHz operation |
144 | MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER0_TIMCLK); | |
145 | // Configure 1MHz clock | |
146 | MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER1_TIMCLK); | |
147 | // configure SP810 to use 1MHz clock and disable | |
148 | MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK); | |
149 | // Configure SP810 to use 1MHz clock and disable | |
150 | MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK); | |
f437141a | 151 | |
152 | return RETURN_SUCCESS; | |
aa01abaa | 153 | } |
154 | ||
1d5d0ae9 | 155 | /** |
156 | Initialize the system (or sometimes called permanent) memory | |
157 | ||
158 | This memory is generally represented by the DRAM. | |
159 | ||
160 | **/ | |
aa01abaa | 161 | VOID |
162 | ArmPlatformInitializeSystemMemory ( | |
163 | VOID | |
164 | ) | |
165 | { | |
8d0fe26c | 166 | UINT32 Value; |
167 | ||
168 | // Memory Map remapping | |
169 | if (FeaturePcdGet(PcdNorFlashRemapping)) { | |
170 | SerialPrint ("Secure ROM at 0x0\n\r"); | |
171 | } else { | |
172 | Value = MmioRead32(ARM_VE_SYS_CFGRW1_REG); //Scc - CFGRW1 | |
173 | // Remap the DRAM to 0x0 | |
174 | MmioWrite32(ARM_VE_SYS_CFGRW1_REG, (Value & 0x0FFFFFFF) | ARM_VE_CFGRW1_REMAP_DRAM); | |
175 | } | |
176 | ||
06a89733 | 177 | PL341DmcInit(ARM_VE_DMC_BASE, &DDRTimings); |
aa01abaa | 178 | PL301AxiInit(ARM_VE_FAXI_BASE); |
1d5d0ae9 | 179 | } |
44788bae | 180 | |
181 | EFI_STATUS | |
182 | PrePeiCoreGetMpCoreInfo ( | |
183 | OUT UINTN *CoreCount, | |
184 | OUT ARM_CORE_INFO **ArmCoreTable | |
185 | ) | |
186 | { | |
187 | *CoreCount = sizeof(mVersatileExpressMpCoreInfoCTA9x4) / sizeof(ARM_CORE_INFO); | |
188 | *ArmCoreTable = mVersatileExpressMpCoreInfoCTA9x4; | |
189 | ||
190 | return EFI_SUCCESS; | |
191 | } | |
192 | ||
193 | // Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore | |
194 | EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID; | |
195 | ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo }; | |
196 | ||
197 | EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = { | |
198 | { | |
199 | EFI_PEI_PPI_DESCRIPTOR_PPI, | |
200 | &mArmMpCoreInfoPpiGuid, | |
201 | &mMpCoreInfoPpi | |
202 | } | |
203 | }; | |
204 | ||
77de7e53 | 205 | VOID |
206 | ArmPlatformGetPlatformPpiList ( | |
207 | OUT UINTN *PpiListSize, | |
208 | OUT EFI_PEI_PPI_DESCRIPTOR **PpiList | |
209 | ) | |
210 | { | |
44788bae | 211 | *PpiListSize = sizeof(gPlatformPpiTable); |
212 | *PpiList = gPlatformPpiTable; | |
77de7e53 | 213 | } |
214 |