projects / mirror_edk2.git / blame
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| b99f8126 GP |
1 | /** @file\r |
| 2 | \r | |
| 3 | This header file contains the platform independent parts of ARM Mali DP\r | |
| 4 | \r | |
| 5 | Copyright (c) 2017-2018, Arm Limited. All rights reserved.<BR>\r | |
| 6 | This program and the accompanying materials\r | |
| 7 | are licensed and made available under the terms and conditions of the BSD License\r | |
| 8 | which accompanies this distribution. The full text of the license may be found at\r | |
| 9 | http://opensource.org/licenses/bsd-license.php\r | |
| 10 | \r | |
| 11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 13 | \r | |
| 14 | **/\r | |
| 15 | #ifndef ARMMALIDP_H_\r | |
| 16 | #define ARMMALIDP_H_\r | |
| 17 | \r | |
| 18 | #define DP_BASE (FixedPcdGet64 (PcdArmMaliDpBase))\r | |
| 19 | \r | |
| 20 | // MALI DP Ids\r | |
| 21 | #define MALIDP_NOT_PRESENT 0xFFF\r | |
| 22 | #define MALIDP_500 0x500\r | |
| 23 | #define MALIDP_550 0x550\r | |
| 24 | #define MALIDP_650 0x650\r | |
| 25 | \r | |
| 26 | // DP500 Peripheral Ids\r | |
| 27 | #define DP500_ID_PART_0 0x00\r | |
| 28 | #define DP500_ID_DES_0 0xB\r | |
| 29 | #define DP500_ID_PART_1 0x5\r | |
| 30 | \r | |
| 31 | #define DP500_ID_REVISION 0x1\r | |
| 32 | #define DP500_ID_JEDEC 0x1\r | |
| 33 | #define DP500_ID_DES_1 0x3\r | |
| 34 | \r | |
| 35 | #define DP500_PERIPHERAL_ID0_VAL (DP500_ID_PART_0)\r | |
| 36 | #define DP500_PERIPHERAL_ID1_VAL ((DP500_ID_DES_0 << 4) \\r | |
| 37 | | DP500_ID_PART_1)\r | |
| 38 | #define DP500_PERIPHERAL_ID2_VAL ((DP500_ID_REVISION << 4) \\r | |
| 39 | | (DP500_ID_JEDEC << 3) \\r | |
| 40 | | (DP500_ID_DES_1))\r | |
| 41 | \r | |
| 42 | // DP550 Peripheral Ids\r | |
| 43 | #define DP550_ID_PART_0 0x50\r | |
| 44 | #define DP550_ID_DES_0 0xB\r | |
| 45 | #define DP550_ID_PART_1 0x5\r | |
| 46 | \r | |
| 47 | #define DP550_ID_REVISION 0x0\r | |
| 48 | #define DP550_ID_JEDEC 0x1\r | |
| 49 | #define DP550_ID_DES_1 0x3\r | |
| 50 | \r | |
| 51 | #define DP550_PERIPHERAL_ID0_VAL (DP550_ID_PART_0)\r | |
| 52 | #define DP550_PERIPHERAL_ID1_VAL ((DP550_ID_DES_0 << 4) \\r | |
| 53 | | DP550_ID_PART_1)\r | |
| 54 | #define DP550_PERIPHERAL_ID2_VAL ((DP550_ID_REVISION << 4) \\r | |
| 55 | | (DP550_ID_JEDEC << 3) \\r | |
| 56 | | (DP550_ID_DES_1))\r | |
| 57 | \r | |
| 58 | // DP650 Peripheral Ids\r | |
| 59 | #define DP650_ID_PART_0 0x50\r | |
| 60 | #define DP650_ID_DES_0 0xB\r | |
| 61 | #define DP650_ID_PART_1 0x6\r | |
| 62 | \r | |
| 63 | #define DP650_ID_REVISION 0x0\r | |
| 64 | #define DP650_ID_JEDEC 0x1\r | |
| 65 | #define DP650_ID_DES_1 0x3\r | |
| 66 | \r | |
| 67 | #define DP650_PERIPHERAL_ID0_VAL (DP650_ID_PART_0)\r | |
| 68 | #define DP650_PERIPHERAL_ID1_VAL ((DP650_ID_DES_0 << 4) \\r | |
| 69 | | DP650_ID_PART_1)\r | |
| 70 | #define DP650_PERIPHERAL_ID2_VAL ((DP650_ID_REVISION << 4) \\r | |
| 71 | | (DP650_ID_JEDEC << 3) \\r | |
| 72 | | (DP650_ID_DES_1))\r | |
| 73 | \r | |
| 74 | // Display Engine (DE) control register offsets for DP550/DP650\r | |
| 75 | #define DP_DE_STATUS 0x00000\r | |
| 76 | #define DP_DE_IRQ_SET 0x00004\r | |
| 77 | #define DP_DE_IRQ_MASK 0x00008\r | |
| 78 | #define DP_DE_IRQ_CLEAR 0x0000C\r | |
| 79 | #define DP_DE_CONTROL 0x00010\r | |
| 80 | #define DP_DE_PROG_LINE 0x00014\r | |
| 81 | #define DP_DE_AXI_CONTROL 0x00018\r | |
| 82 | #define DP_DE_AXI_QOS 0x0001C\r | |
| 83 | #define DP_DE_DISPLAY_FUNCTION 0x00020\r | |
| 84 | \r | |
| 85 | #define DP_DE_H_INTERVALS 0x00030\r | |
| 86 | #define DP_DE_V_INTERVALS 0x00034\r | |
| 87 | #define DP_DE_SYNC_CONTROL 0x00038\r | |
| 88 | #define DP_DE_HV_ACTIVESIZE 0x0003C\r | |
| 89 | #define DP_DE_DISPLAY_SIDEBAND 0x00040\r | |
| 90 | #define DP_DE_BACKGROUND_COLOR 0x00044\r | |
| 91 | #define DP_DE_DISPLAY_SPLIT 0x00048\r | |
| 92 | #define DP_DE_OUTPUT_DEPTH 0x0004C\r | |
| 93 | \r | |
| 94 | // Display Engine (DE) control register offsets for DP500\r | |
| 95 | #define DP_DE_DP500_CORE_ID 0x00018\r | |
| 96 | #define DP_DE_DP500_CONTROL 0x0000C\r | |
| 97 | #define DP_DE_DP500_PROG_LINE 0x00010\r | |
| 98 | #define DP_DE_DP500_H_INTERVALS 0x00028\r | |
| 99 | #define DP_DE_DP500_V_INTERVALS 0x0002C\r | |
| 100 | #define DP_DE_DP500_SYNC_CONTROL 0x00030\r | |
| 101 | #define DP_DE_DP500_HV_ACTIVESIZE 0x00034\r | |
| 102 | #define DP_DE_DP500_BG_COLOR_RG 0x0003C\r | |
| 103 | #define DP_DE_DP500_BG_COLOR_B 0x00040\r | |
| 104 | \r | |
| 105 | /* Display Engine (DE) graphics layer (LG) register offsets\r | |
| 106 | * NOTE: For DP500 it will be LG2.\r | |
| 107 | */\r | |
| 108 | #define DE_LG_OFFSET 0x00300\r | |
| 109 | #define DP_DE_LG_FORMAT (DE_LG_OFFSET)\r | |
| 110 | #define DP_DE_LG_CONTROL (DE_LG_OFFSET + 0x04)\r | |
| 111 | #define DP_DE_LG_COMPOSE (DE_LG_OFFSET + 0x08)\r | |
| 112 | #define DP_DE_LG_IN_SIZE (DE_LG_OFFSET + 0x0C)\r | |
| 113 | #define DP_DE_LG_CMP_SIZE (DE_LG_OFFSET + 0x10)\r | |
| 114 | #define DP_DE_LG_OFFSET (DE_LG_OFFSET + 0x14)\r | |
| 115 | #define DP_DE_LG_H_STRIDE (DE_LG_OFFSET + 0x18)\r | |
| 116 | #define DP_DE_LG_PTR_LOW (DE_LG_OFFSET + 0x1C)\r | |
| 117 | #define DP_DE_LG_PTR_HIGH (DE_LG_OFFSET + 0x20)\r | |
| 118 | #define DP_DE_LG_CHROMA_KEY (DE_LG_OFFSET + 0x2C)\r | |
| 119 | #define DP_DE_LG_AD_CONTROL (DE_LG_OFFSET + 0x30)\r | |
| 120 | #define DP_DE_LG_MMU_CONTROL (DE_LG_OFFSET + 0x48)\r | |
| 121 | \r | |
| 122 | // Display core (DC) control register offsets.\r | |
| 123 | #define DP_DC_OFFSET 0x0C000\r | |
| 124 | #define DP_DC_STATUS (DP_DC_OFFSET + 0x00)\r | |
| 125 | #define DP_DC_IRQ_SET (DP_DC_OFFSET + 0x04)\r | |
| 126 | #define DP_DC_IRQ_MASK (DP_DC_OFFSET + 0x08)\r | |
| 127 | #define DP_DC_IRQ_CLEAR (DP_DC_OFFSET + 0x0C)\r | |
| 128 | #define DP_DC_CONTROL (DP_DC_OFFSET + 0x10)\r | |
| 129 | #define DP_DC_CONFIG_VALID (DP_DC_OFFSET + 0x14)\r | |
| 130 | #define DP_DC_CORE_ID (DP_DC_OFFSET + 0x18)\r | |
| 131 | \r | |
| 132 | // DP500 has a global configuration register.\r | |
| 133 | #define DP_DP500_CONFIG_VALID (0xF00)\r | |
| 134 | \r | |
| 135 | // Display core ID register offsets.\r | |
| 136 | #define DP_DC_ID_OFFSET 0x0FF00\r | |
| 137 | #define DP_DC_ID_PERIPHERAL_ID4 (DP_DC_ID_OFFSET + 0xD0)\r | |
| 138 | #define DP_DC_CONFIGURATION_ID (DP_DC_ID_OFFSET + 0xD4)\r | |
| 139 | #define DP_DC_PERIPHERAL_ID0 (DP_DC_ID_OFFSET + 0xE0)\r | |
| 140 | #define DP_DC_PERIPHERAL_ID1 (DP_DC_ID_OFFSET + 0xE4)\r | |
| 141 | #define DP_DC_PERIPHERAL_ID2 (DP_DC_ID_OFFSET + 0xE8)\r | |
| 142 | #define DP_DC_COMPONENT_ID0 (DP_DC_ID_OFFSET + 0xF0)\r | |
| 143 | #define DP_DC_COMPONENT_ID1 (DP_DC_ID_OFFSET + 0xF4)\r | |
| 144 | #define DP_DC_COMPONENT_ID2 (DP_DC_ID_OFFSET + 0xF8)\r | |
| 145 | #define DP_DC_COMPONENT_ID3 (DP_DC_ID_OFFSET + 0xFC)\r | |
| 146 | \r | |
| 147 | #define DP_DP500_ID_OFFSET 0x0F00\r | |
| 148 | #define DP_DP500_ID_PERIPHERAL_ID4 (DP_DP500_ID_OFFSET + 0xD0)\r | |
| 149 | #define DP_DP500_CONFIGURATION_ID (DP_DP500_ID_OFFSET + 0xD4)\r | |
| 150 | #define DP_DP500_PERIPHERAL_ID0 (DP_DP500_ID_OFFSET + 0xE0)\r | |
| 151 | #define DP_DP500_PERIPHERAL_ID1 (DP_DP500_ID_OFFSET + 0xE4)\r | |
| 152 | #define DP_DP500_PERIPHERAL_ID2 (DP_DP500_ID_OFFSET + 0xE8)\r | |
| 153 | #define DP_DP500_COMPONENT_ID0 (DP_DP500_ID_OFFSET + 0xF0)\r | |
| 154 | #define DP_DP500_COMPONENT_ID1 (DP_DP500_ID_OFFSET + 0xF4)\r | |
| 155 | #define DP_DP500_COMPONENT_ID2 (DP_DP500_ID_OFFSET + 0xF8)\r | |
| 156 | #define DP_DP500_COMPONENT_ID3 (DP_DP500_ID_OFFSET + 0xFC)\r | |
| 157 | \r | |
| 158 | // Display status configuration mode activation flag\r | |
| 159 | #define DP_DC_STATUS_CM_ACTIVE_FLAG (0x1U << 16)\r | |
| 160 | \r | |
| 161 | // Display core control configuration mode\r | |
| 162 | #define DP_DC_CONTROL_SRST_ACTIVE (0x1U << 18)\r | |
| 163 | #define DP_DC_CONTROL_CRST_ACTIVE (0x1U << 17)\r | |
| 164 | #define DP_DC_CONTROL_CM_ACTIVE (0x1U << 16)\r | |
| 165 | \r | |
| 166 | #define DP_DE_DP500_CONTROL_SOFTRESET_REQ (0x1U << 16)\r | |
| 167 | #define DP_DE_DP500_CONTROL_CONFIG_REQ (0x1U << 17)\r | |
| 168 | \r | |
| 169 | // Display core configuration valid register\r | |
| 170 | #define DP_DC_CONFIG_VALID_CVAL (0x1U)\r | |
| 171 | \r | |
| 172 | // DC_CORE_ID\r | |
| 173 | // Display core version register PRODUCT_ID\r | |
| 174 | #define DP_DC_CORE_ID_SHIFT 16\r | |
| 175 | #define DP_DE_DP500_CORE_ID_SHIFT DP_DC_CORE_ID_SHIFT\r | |
| 176 | \r | |
| 177 | // Timing settings\r | |
| 178 | #define DP_DE_HBACKPORCH_SHIFT 16\r | |
| 179 | #define DP_DE_VBACKPORCH_SHIFT 16\r | |
| 180 | #define DP_DE_VSP_SHIFT 28\r | |
| 181 | #define DP_DE_VSYNCWIDTH_SHIFT 16\r | |
| 182 | #define DP_DE_HSP_SHIFT 13\r | |
| 183 | #define DP_DE_V_ACTIVE_SHIFT 16\r | |
| 184 | \r | |
| 185 | // BACKGROUND_COLOR\r | |
| 186 | #define DP_DE_BG_R_PIXEL_SHIFT 16\r | |
| 187 | #define DP_DE_BG_G_PIXEL_SHIFT 8\r | |
| 188 | \r | |
| 189 | //Graphics layer LG_FORMAT Pixel Format\r | |
| 190 | #define DP_PIXEL_FORMAT_ARGB_8888 0x8\r | |
| 191 | #define DP_PIXEL_FORMAT_ABGR_8888 0x9\r | |
| 192 | #define DP_PIXEL_FORMAT_RGBA_8888 0xA\r | |
| 193 | #define DP_PIXEL_FORMAT_BGRA_8888 0xB\r | |
| 194 | #define DP_PIXEL_FORMAT_XRGB_8888 0x10\r | |
| 195 | #define DP_PIXEL_FORMAT_XBGR_8888 0x11\r | |
| 196 | #define DP_PIXEL_FORMAT_RGBX_8888 0x12\r | |
| 197 | #define DP_PIXEL_FORMAT_BGRX_8888 0x13\r | |
| 198 | #define DP_PIXEL_FORMAT_RGB_888 0x18\r | |
| 199 | #define DP_PIXEL_FORMAT_BGR_888 0x19\r | |
| 200 | \r | |
| 201 | // DP500 format code are different than DP550/DP650\r | |
| 202 | #define DP_PIXEL_FORMAT_DP500_ARGB_8888 0x2\r | |
| 203 | #define DP_PIXEL_FORMAT_DP500_ABGR_8888 0x3\r | |
| 204 | #define DP_PIXEL_FORMAT_DP500_XRGB_8888 0x4\r | |
| 205 | #define DP_PIXEL_FORMAT_DP500_XBGR_8888 0x5\r | |
| 206 | \r | |
| 207 | // Graphics layer LG_PTR_LOW and LG_PTR_HIGH\r | |
| 208 | #define DP_DE_LG_PTR_LOW_MASK 0xFFFFFFFFU\r | |
| 209 | #define DP_DE_LG_PTR_HIGH_SHIFT 32\r | |
| 210 | \r | |
| 211 | // Graphics layer LG_CONTROL register characteristics\r | |
| 212 | #define DP_DE_LG_L_ALPHA_SHIFT 16\r | |
| 213 | #define DP_DE_LG_CHK_SHIFT 15\r | |
| 214 | #define DP_DE_LG_PMUL_SHIFT 14\r | |
| 215 | #define DP_DE_LG_COM_SHIFT 12\r | |
| 216 | #define DP_DE_LG_VFP_SHIFT 11\r | |
| 217 | #define DP_DE_LG_HFP_SHIFT 10\r | |
| 218 | #define DP_DE_LG_ROTATION_SHIFT 8\r | |
| 219 | \r | |
| 220 | #define DP_DE_LG_LAYER_BLEND_NO_BG 0x0U\r | |
| 221 | #define DP_DE_LG_PIXEL_BLEND_NO_BG 0x1U\r | |
| 222 | #define DP_DE_LG_LAYER_BLEND_BG 0x2U\r | |
| 223 | #define DP_DE_LG_PIXEL_BLEND_BG 0x3U\r | |
| 224 | #define DP_DE_LG_ENABLE 0x1U\r | |
| 225 | \r | |
| 226 | // Graphics layer LG_IN_SIZE register characteristics\r | |
| 227 | #define DP_DE_LG_V_IN_SIZE_SHIFT 16\r | |
| 228 | \r | |
| 229 | // Graphics layer LG_CMP_SIZE register characteristics\r | |
| 230 | #define DP_DE_LG_V_CMP_SIZE_SHIFT 16\r | |
| 231 | #define DP_DE_LG_V_OFFSET_SHIFT 16\r | |
| 232 | \r | |
| 233 | // Helper display timing macro functions.\r | |
| 234 | #define H_INTERVALS(Hfp, Hbp) ((Hbp << DP_DE_HBACKPORCH_SHIFT) | Hfp)\r | |
| 235 | #define V_INTERVALS(Vfp, Vbp) ((Vbp << DP_DE_VBACKPORCH_SHIFT) | Vfp)\r | |
| 236 | #define SYNC_WIDTH(Hsw, Vsw) ((Vsw << DP_DE_VSYNCWIDTH_SHIFT) | Hsw)\r | |
| 237 | #define HV_ACTIVE(Hor, Ver) ((Ver << DP_DE_V_ACTIVE_SHIFT) | Hor)\r | |
| 238 | \r | |
| 239 | // Helper layer graphics macros.\r | |
| 240 | #define FRAME_IN_SIZE(Hor, Ver) ((Ver << DP_DE_LG_V_IN_SIZE_SHIFT) | Hor)\r | |
| 241 | #define FRAME_CMP_SIZE(Hor, Ver) ((Ver << DP_DE_LG_V_CMP_SIZE_SHIFT) | Hor)\r | |
| 242 | \r | |
| 243 | #endif /* ARMMALIDP_H_ */\r |