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b1b69d26 | 1 | /** @file\r |
4257dfaa | 2 | This file contains the platform independent parts of HdLcd\r |
3e7105bb | 3 | \r |
b1b69d26 | 4 | Copyright (c) 2011-2018, ARM Ltd. All rights reserved.<BR>\r |
3e7105bb AB |
5 | \r |
6 | This program and the accompanying materials\r | |
7 | are licensed and made available under the terms and conditions of the BSD License\r | |
8 | which accompanies this distribution. The full text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
14 | **/\r | |
15 | \r | |
16 | #include <Library/DebugLib.h>\r | |
17 | #include <Library/IoLib.h>\r | |
18 | #include <Library/LcdHwLib.h>\r | |
19 | #include <Library/LcdPlatformLib.h>\r | |
20 | #include <Library/MemoryAllocationLib.h>\r | |
21 | #include <Library/PcdLib.h>\r | |
22 | \r | |
23 | #include "HdLcd.h"\r | |
24 | \r | |
fe787dfb | 25 | #define BYTES_PER_PIXEL 4\r |
3e7105bb | 26 | \r |
4257dfaa GP |
27 | /** Initialize display.\r |
28 | \r | |
29 | @param[in] VramBaseAddress Address of the framebuffer.\r | |
30 | \r | |
31 | @retval EFI_SUCCESS Display initialization successful.\r | |
32 | **/\r | |
3e7105bb AB |
33 | EFI_STATUS\r |
34 | LcdInitialize (\r | |
35 | IN EFI_PHYSICAL_ADDRESS VramBaseAddress\r | |
36 | )\r | |
37 | {\r | |
38 | // Disable the controller\r | |
b1b69d26 | 39 | MmioWrite32 (HDLCD_REG_COMMAND, HDLCD_DISABLE);\r |
3e7105bb AB |
40 | \r |
41 | // Disable all interrupts\r | |
b1b69d26 | 42 | MmioWrite32 (HDLCD_REG_INT_MASK, 0);\r |
3e7105bb AB |
43 | \r |
44 | // Define start of the VRAM. This never changes for any graphics mode\r | |
b1b69d26 | 45 | MmioWrite32 (HDLCD_REG_FB_BASE, (UINT32)VramBaseAddress);\r |
3e7105bb AB |
46 | \r |
47 | // Setup various registers that never change\r | |
b1b69d26 GP |
48 | MmioWrite32 (HDLCD_REG_BUS_OPTIONS, (4 << 8) | HDLCD_BURST_8);\r |
49 | \r | |
50 | MmioWrite32 (HDLCD_REG_POLARITIES, HDLCD_DEFAULT_POLARITIES);\r | |
51 | \r | |
52 | MmioWrite32 (\r | |
53 | HDLCD_REG_PIXEL_FORMAT,\r | |
54 | HDLCD_LITTLE_ENDIAN | HDLCD_4BYTES_PER_PIXEL\r | |
55 | );\r | |
56 | \r | |
3e7105bb AB |
57 | return EFI_SUCCESS;\r |
58 | }\r | |
59 | \r | |
4257dfaa GP |
60 | /** Set requested mode of the display.\r |
61 | \r | |
62 | @param[in] ModeNumber Display mode number.\r | |
63 | \r | |
64 | @retval EFI_SUCCESS Display mode set successfully.\r | |
3da4193b | 65 | @retval !(EFI_SUCCESS) Other errors.\r |
4257dfaa | 66 | **/\r |
3e7105bb AB |
67 | EFI_STATUS\r |
68 | LcdSetMode (\r | |
69 | IN UINT32 ModeNumber\r | |
70 | )\r | |
71 | {\r | |
72 | EFI_STATUS Status;\r | |
262c8846 GP |
73 | SCAN_TIMINGS *Horizontal;\r |
74 | SCAN_TIMINGS *Vertical;\r | |
fe787dfb GP |
75 | \r |
76 | EFI_GRAPHICS_OUTPUT_MODE_INFORMATION ModeInfo;\r | |
3e7105bb | 77 | \r |
3e7105bb | 78 | // Set the video mode timings and other relevant information\r |
b1b69d26 GP |
79 | Status = LcdPlatformGetTimings (\r |
80 | ModeNumber,\r | |
262c8846 GP |
81 | &Horizontal,\r |
82 | &Vertical\r | |
b1b69d26 | 83 | );\r |
b1b69d26 | 84 | if (EFI_ERROR (Status)) {\r |
3da4193b GP |
85 | ASSERT_EFI_ERROR (Status);\r |
86 | return Status;\r | |
3e7105bb AB |
87 | }\r |
88 | \r | |
262c8846 GP |
89 | ASSERT (Horizontal != NULL);\r |
90 | ASSERT (Vertical != NULL);\r | |
91 | \r | |
fe787dfb GP |
92 | // Get the pixel format information.\r |
93 | Status = LcdPlatformQueryMode (ModeNumber, &ModeInfo);\r | |
b1b69d26 | 94 | if (EFI_ERROR (Status)) {\r |
3da4193b GP |
95 | ASSERT_EFI_ERROR (Status);\r |
96 | return Status;\r | |
3e7105bb AB |
97 | }\r |
98 | \r | |
fe787dfb GP |
99 | if (ModeInfo.PixelFormat == PixelBlueGreenRedReserved8BitPerColor) {\r |
100 | MmioWrite32 (HDLCD_REG_RED_SELECT, (8 << 8) | 16);\r | |
101 | MmioWrite32 (HDLCD_REG_BLUE_SELECT, (8 << 8) | 0);\r | |
102 | } else {\r | |
103 | MmioWrite32 (HDLCD_REG_BLUE_SELECT, (8 << 8) | 16);\r | |
104 | MmioWrite32 (HDLCD_REG_RED_SELECT, (8 << 8) | 0);\r | |
105 | }\r | |
106 | \r | |
107 | MmioWrite32 (HDLCD_REG_GREEN_SELECT, (8 << 8) | 8);\r | |
3e7105bb AB |
108 | \r |
109 | // Disable the controller\r | |
b1b69d26 | 110 | MmioWrite32 (HDLCD_REG_COMMAND, HDLCD_DISABLE);\r |
3e7105bb AB |
111 | \r |
112 | // Update the frame buffer information with the new settings\r | |
262c8846 GP |
113 | MmioWrite32 (\r |
114 | HDLCD_REG_FB_LINE_LENGTH,\r | |
fe787dfb | 115 | Horizontal->Resolution * BYTES_PER_PIXEL\r |
262c8846 GP |
116 | );\r |
117 | \r | |
fe787dfb GP |
118 | MmioWrite32 (\r |
119 | HDLCD_REG_FB_LINE_PITCH,\r | |
120 | Horizontal->Resolution * BYTES_PER_PIXEL\r | |
121 | );\r | |
262c8846 GP |
122 | \r |
123 | MmioWrite32 (HDLCD_REG_FB_LINE_COUNT, Vertical->Resolution - 1);\r | |
3e7105bb AB |
124 | \r |
125 | // Set the vertical timing information\r | |
262c8846 GP |
126 | MmioWrite32 (HDLCD_REG_V_SYNC, Vertical->Sync);\r |
127 | MmioWrite32 (HDLCD_REG_V_BACK_PORCH, Vertical->BackPorch);\r | |
128 | MmioWrite32 (HDLCD_REG_V_DATA, Vertical->Resolution - 1);\r | |
129 | MmioWrite32 (HDLCD_REG_V_FRONT_PORCH, Vertical->FrontPorch);\r | |
3e7105bb AB |
130 | \r |
131 | // Set the horizontal timing information\r | |
262c8846 GP |
132 | MmioWrite32 (HDLCD_REG_H_SYNC, Horizontal->Sync);\r |
133 | MmioWrite32 (HDLCD_REG_H_BACK_PORCH, Horizontal->BackPorch);\r | |
134 | MmioWrite32 (HDLCD_REG_H_DATA, Horizontal->Resolution - 1);\r | |
135 | MmioWrite32 (HDLCD_REG_H_FRONT_PORCH, Horizontal->FrontPorch);\r | |
3e7105bb AB |
136 | \r |
137 | // Enable the controller\r | |
b1b69d26 | 138 | MmioWrite32 (HDLCD_REG_COMMAND, HDLCD_ENABLE);\r |
3e7105bb AB |
139 | \r |
140 | return EFI_SUCCESS;\r | |
141 | }\r | |
142 | \r | |
4257dfaa GP |
143 | /** De-initializes the display.\r |
144 | **/\r | |
3e7105bb AB |
145 | VOID\r |
146 | LcdShutdown (\r | |
147 | VOID\r | |
148 | )\r | |
149 | {\r | |
150 | // Disable the controller\r | |
151 | MmioWrite32 (HDLCD_REG_COMMAND, HDLCD_DISABLE);\r | |
152 | }\r | |
153 | \r | |
4257dfaa GP |
154 | /** Check for presence of HDLCD.\r |
155 | \r | |
156 | @retval EFI_SUCCESS Returns success if platform implements a HDLCD\r | |
157 | controller.\r | |
c18ef81e GP |
158 | @retval EFI_NOT_FOUND HDLCD display controller not found on the\r |
159 | platform.\r | |
4257dfaa | 160 | **/\r |
3e7105bb AB |
161 | EFI_STATUS\r |
162 | LcdIdentify (\r | |
163 | VOID\r | |
164 | )\r | |
165 | {\r | |
c18ef81e GP |
166 | if ((MmioRead32 (HDLCD_REG_VERSION) >> 16) == HDLCD_PRODUCT_ID) {\r |
167 | return EFI_SUCCESS;\r | |
168 | }\r | |
169 | \r | |
170 | return EFI_NOT_FOUND;\r | |
3e7105bb | 171 | }\r |