projects / mirror_edk2.git / blame
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1 | /** @file\r |
| 2 | *\r | |
| 3 | * Copyright (c) 2011-2016, ARM Limited. All rights reserved.\r | |
| 4 | *\r | |
| 5 | * This program and the accompanying materials\r | |
| 6 | * are licensed and made available under the terms and conditions of the BSD License\r | |
| 7 | * which accompanies this distribution. The full text of the license may be found at\r | |
| 8 | * http://opensource.org/licenses/bsd-license.php\r | |
| 9 | *\r | |
| 10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 12 | *\r | |
| 13 | **/\r | |
| 14 | \r | |
| 15 | #ifndef __PL011_UART_H__\r | |
| 16 | #define __PL011_UART_H__\r | |
| 17 | \r | |
| 18 | #define PL011_VARIANT_ZTE 1\r | |
| 19 | \r | |
| 20 | // PL011 Registers\r | |
| 21 | #if FixedPcdGet8 (PL011UartRegOffsetVariant) == PL011_VARIANT_ZTE\r | |
| 22 | #define UARTDR 0x004\r | |
| 23 | #define UARTRSR 0x010\r | |
| 24 | #define UARTECR 0x010\r | |
| 25 | #define UARTFR 0x014\r | |
| 26 | #define UARTIBRD 0x024\r | |
| 27 | #define UARTFBRD 0x028\r | |
| 28 | #define UARTLCR_H 0x030\r | |
| 29 | #define UARTCR 0x034\r | |
| 30 | #define UARTIFLS 0x038\r | |
| 31 | #define UARTIMSC 0x040\r | |
| 32 | #define UARTRIS 0x044\r | |
| 33 | #define UARTMIS 0x048\r | |
| 34 | #define UARTICR 0x04c\r | |
| 35 | #define UARTDMACR 0x050\r | |
| 36 | #else\r | |
| 37 | #define UARTDR 0x000\r | |
| 38 | #define UARTRSR 0x004\r | |
| 39 | #define UARTECR 0x004\r | |
| 40 | #define UARTFR 0x018\r | |
| 41 | #define UARTILPR 0x020\r | |
| 42 | #define UARTIBRD 0x024\r | |
| 43 | #define UARTFBRD 0x028\r | |
| 44 | #define UARTLCR_H 0x02C\r | |
| 45 | #define UARTCR 0x030\r | |
| 46 | #define UARTIFLS 0x034\r | |
| 47 | #define UARTIMSC 0x038\r | |
| 48 | #define UARTRIS 0x03C\r | |
| 49 | #define UARTMIS 0x040\r | |
| 50 | #define UARTICR 0x044\r | |
| 51 | #define UARTDMACR 0x048\r | |
| 52 | #endif\r | |
| 53 | \r | |
| 54 | #define UARTPID0 0xFE0\r | |
| 55 | #define UARTPID1 0xFE4\r | |
| 56 | #define UARTPID2 0xFE8\r | |
| 57 | #define UARTPID3 0xFEC\r | |
| 58 | \r | |
| 59 | // Data status bits\r | |
| 60 | #define UART_DATA_ERROR_MASK 0x0F00\r | |
| 61 | \r | |
| 62 | // Status reg bits\r | |
| 63 | #define UART_STATUS_ERROR_MASK 0x0F\r | |
| 64 | \r | |
| 65 | // Flag reg bits\r | |
| 66 | #if FixedPcdGet8 (PL011UartRegOffsetVariant) == PL011_VARIANT_ZTE\r | |
| 67 | #define PL011_UARTFR_RI (1 << 0) // Ring indicator\r | |
| 68 | #define PL011_UARTFR_TXFE (1 << 7) // Transmit FIFO empty\r | |
| 69 | #define PL011_UARTFR_RXFF (1 << 6) // Receive FIFO full\r | |
| 70 | #define PL011_UARTFR_TXFF (1 << 5) // Transmit FIFO full\r | |
| 71 | #define PL011_UARTFR_RXFE (1 << 4) // Receive FIFO empty\r | |
| 72 | #define PL011_UARTFR_BUSY (1 << 8) // UART busy\r | |
| 73 | #define PL011_UARTFR_DCD (1 << 2) // Data carrier detect\r | |
| 74 | #define PL011_UARTFR_DSR (1 << 3) // Data set ready\r | |
| 75 | #define PL011_UARTFR_CTS (1 << 1) // Clear to send\r | |
| 76 | #else\r | |
| 77 | #define PL011_UARTFR_RI (1 << 8) // Ring indicator\r | |
| 78 | #define PL011_UARTFR_TXFE (1 << 7) // Transmit FIFO empty\r | |
| 79 | #define PL011_UARTFR_RXFF (1 << 6) // Receive FIFO full\r | |
| 80 | #define PL011_UARTFR_TXFF (1 << 5) // Transmit FIFO full\r | |
| 81 | #define PL011_UARTFR_RXFE (1 << 4) // Receive FIFO empty\r | |
| 82 | #define PL011_UARTFR_BUSY (1 << 3) // UART busy\r | |
| 83 | #define PL011_UARTFR_DCD (1 << 2) // Data carrier detect\r | |
| 84 | #define PL011_UARTFR_DSR (1 << 1) // Data set ready\r | |
| 85 | #define PL011_UARTFR_CTS (1 << 0) // Clear to send\r | |
| 86 | #endif\r | |
| 87 | \r | |
| 88 | // Flag reg bits - alternative names\r | |
| 89 | #define UART_TX_EMPTY_FLAG_MASK PL011_UARTFR_TXFE\r | |
| 90 | #define UART_RX_FULL_FLAG_MASK PL011_UARTFR_RXFF\r | |
| 91 | #define UART_TX_FULL_FLAG_MASK PL011_UARTFR_TXFF\r | |
| 92 | #define UART_RX_EMPTY_FLAG_MASK PL011_UARTFR_RXFE\r | |
| 93 | #define UART_BUSY_FLAG_MASK PL011_UARTFR_BUSY\r | |
| 94 | \r | |
| 95 | // Control reg bits\r | |
| 96 | #define PL011_UARTCR_CTSEN (1 << 15) // CTS hardware flow control enable\r | |
| 97 | #define PL011_UARTCR_RTSEN (1 << 14) // RTS hardware flow control enable\r | |
| 98 | #define PL011_UARTCR_RTS (1 << 11) // Request to send\r | |
| 99 | #define PL011_UARTCR_DTR (1 << 10) // Data transmit ready.\r | |
| 100 | #define PL011_UARTCR_RXE (1 << 9) // Receive enable\r | |
| 101 | #define PL011_UARTCR_TXE (1 << 8) // Transmit enable\r | |
| 102 | #define PL011_UARTCR_LBE (1 << 7) // Loopback enable\r | |
| 103 | #define PL011_UARTCR_UARTEN (1 << 0) // UART Enable\r | |
| 104 | \r | |
| 105 | // Line Control Register Bits\r | |
| 106 | #define PL011_UARTLCR_H_SPS (1 << 7) // Stick parity select\r | |
| 107 | #define PL011_UARTLCR_H_WLEN_8 (3 << 5)\r | |
| 108 | #define PL011_UARTLCR_H_WLEN_7 (2 << 5)\r | |
| 109 | #define PL011_UARTLCR_H_WLEN_6 (1 << 5)\r | |
| 110 | #define PL011_UARTLCR_H_WLEN_5 (0 << 5)\r | |
| 111 | #define PL011_UARTLCR_H_FEN (1 << 4) // FIFOs Enable\r | |
| 112 | #define PL011_UARTLCR_H_STP2 (1 << 3) // Two stop bits select\r | |
| 113 | #define PL011_UARTLCR_H_EPS (1 << 2) // Even parity select\r | |
| 114 | #define PL011_UARTLCR_H_PEN (1 << 1) // Parity Enable\r | |
| 115 | #define PL011_UARTLCR_H_BRK (1 << 0) // Send break\r | |
| 116 | \r | |
| 117 | #define PL011_UARTPID2_VER(X) (((X) >> 4) & 0xF)\r | |
| 118 | #define PL011_VER_R1P4 0x2\r | |
| 119 | \r | |
| 120 | #endif\r |