ArmPlatformPkg: Move PcdStandalone from Feature PCD to Fixed PCD

[mirror_edk2.git] / ArmPlatformPkg / PrePeiCore / MainMPCore.c

/** @file\r
*\r
*  Copyright (c) 2011, ARM Limited. All rights reserved.\r
*\r
*  This program and the accompanying materials\r
*  are licensed and made available under the terms and conditions of the BSD License\r
*  which accompanies this distribution.  The full text of the license may be found at\r
*  http://opensource.org/licenses/bsd-license.php\r
*\r
*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
*\r
**/\r
\r
#include <Library/DebugLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/ArmMPCoreMailBoxLib.h>\r
#include <Chipset/ArmV7.h>\r
#include <Drivers/PL390Gic.h>\r
\r
#include "PrePeiCore.h"\r
\r
extern EFI_PEI_PPI_DESCRIPTOR *gSecPpiTable;\r
\r
/*\r
 * This is the main function for secondary cores. They loop around until a non Null value is written to\r
 * SYS_FLAGS register.The SYS_FLAGS register is platform specific.\r
 * Note:The secondary cores, while executing secondary_main, assumes that:\r
 *      : SGI 0 is configured as Non-secure interrupt\r
 *      : Priority Mask is configured to allow SGI 0\r
 *      : Interrupt Distributor and CPU interfaces are enabled\r
 *\r
 */\r
VOID\r
EFIAPI\r
SecondaryMain (\r
  IN UINTN CoreId\r
  )\r
{\r
  // Function pointer to Secondary Core entry point\r
  VOID (*secondary_start)(VOID);\r
  UINTN secondary_entry_addr=0;\r
\r
  // Clear Secondary cores MailBox\r
  ArmClearMPCoreMailbox();\r
\r
  while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) {\r
    ArmCallWFI();\r
    // Acknowledge the interrupt and send End of Interrupt signal.\r
    PL390GicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/);\r
  }\r
\r
  secondary_start = (VOID (*)())secondary_entry_addr;\r
\r
  // Jump to secondary core entry point.\r
  secondary_start();\r
\r
  // The secondaries shouldn't reach here\r
  ASSERT(FALSE);\r
}\r
\r
VOID\r
EFIAPI\r
PrimaryMain (\r
  IN  EFI_PEI_CORE_ENTRY_POINT  PeiCoreEntryPoint\r
  )\r
{\r
  EFI_SEC_PEI_HAND_OFF        SecCoreData;\r
\r
  //Enable the GIC Distributor\r
  PL390GicEnableDistributor(PcdGet32(PcdGicDistributorBase));\r
\r
  // If ArmVe has not been built as Standalone then we need to wake up the secondary cores\r
  if (!PcdGet32(PcdStandalone)) {\r
    // Sending SGI to all the Secondary CPU interfaces\r
    PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);\r
  }\r
\r
  //\r
  // Bind this information into the SEC hand-off state\r
  // Note: this must be in sync with the stuff in the asm file\r
  // Note also:  HOBs (pei temp ram) MUST be above stack\r
  //\r
  SecCoreData.DataSize               = sizeof(EFI_SEC_PEI_HAND_OFF);\r
  SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdNormalFvBaseAddress);\r
  SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdNormalFvSize);\r
  SecCoreData.TemporaryRamBase       = (VOID *)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackBase); // We consider we run on the primary core (and so we use the first stack)\r
  SecCoreData.TemporaryRamSize       = (UINTN)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackSize);\r
  SecCoreData.PeiTemporaryRamBase    = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize / 2));\r
  SecCoreData.PeiTemporaryRamSize    = SecCoreData.TemporaryRamSize / 2;\r
  SecCoreData.StackBase              = SecCoreData.TemporaryRamBase;\r
  SecCoreData.StackSize              = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize;\r
\r
  // Jump to PEI core entry point\r
  (PeiCoreEntryPoint)(&SecCoreData, (VOID *)&gSecPpiTable);\r
}\r