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1d5d0ae9 | 1 | /** @file\r |
5a5440d0 PG |
2 | Main file supporting the transition to PEI Core in Normal World for Versatile Express\r |
3 | \r | |
4 | Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r | |
5 | \r | |
6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
7 | \r | |
1d5d0ae9 | 8 | **/\r |
9 | \r | |
1d5d0ae9 | 10 | #include <Library/BaseLib.h>\r |
6c9a3d42 | 11 | #include <Library/CacheMaintenanceLib.h>\r |
a6caee65 | 12 | #include <Library/DebugAgentLib.h>\r |
1d5d0ae9 | 13 | #include <Library/ArmLib.h>\r |
8fc38a3f | 14 | \r |
f598bf12 | 15 | #include "PrePeiCore.h"\r |
1d5d0ae9 | 16 | \r |
40b0b23e | 17 | CONST EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI mTemporaryRamSupportPpi = { PrePeiCoreTemporaryRamSupport };\r |
1d5d0ae9 | 18 | \r |
40b0b23e | 19 | CONST EFI_PEI_PPI_DESCRIPTOR gCommonPpiTable[] = {\r |
1d5d0ae9 | 20 | {\r |
8fc38a3f | 21 | EFI_PEI_PPI_DESCRIPTOR_PPI,\r |
1d5d0ae9 | 22 | &gEfiTemporaryRamSupportPpiGuid,\r |
40b0b23e | 23 | (VOID *)&mTemporaryRamSupportPpi\r |
1d5d0ae9 | 24 | }\r |
25 | };\r | |
26 | \r | |
77de7e53 | 27 | VOID\r |
28 | CreatePpiList (\r | |
29 | OUT UINTN *PpiListSize,\r | |
30 | OUT EFI_PEI_PPI_DESCRIPTOR **PpiList\r | |
31 | )\r | |
32 | {\r | |
40b0b23e | 33 | EFI_PEI_PPI_DESCRIPTOR *PlatformPpiList;\r |
77de7e53 | 34 | UINTN PlatformPpiListSize;\r |
35 | UINTN ListBase;\r | |
40b0b23e | 36 | EFI_PEI_PPI_DESCRIPTOR *LastPpi;\r |
77de7e53 | 37 | \r |
38 | // Get the Platform PPIs\r | |
39 | PlatformPpiListSize = 0;\r | |
40 | ArmPlatformGetPlatformPpiList (&PlatformPpiListSize, &PlatformPpiList);\r | |
41 | \r | |
16f3544d | 42 | // Copy the Common and Platform PPis in Temporary Memory\r |
bb5420bb | 43 | ListBase = PcdGet64 (PcdCPUCoresStackBase);\r |
40b0b23e MK |
44 | CopyMem ((VOID *)ListBase, gCommonPpiTable, sizeof (gCommonPpiTable));\r |
45 | CopyMem ((VOID *)(ListBase + sizeof (gCommonPpiTable)), PlatformPpiList, PlatformPpiListSize);\r | |
77de7e53 | 46 | \r |
47 | // Set the Terminate flag on the last PPI entry\r | |
40b0b23e | 48 | LastPpi = (EFI_PEI_PPI_DESCRIPTOR *)ListBase + ((sizeof (gCommonPpiTable) + PlatformPpiListSize) / sizeof (EFI_PEI_PPI_DESCRIPTOR)) - 1;\r |
77de7e53 | 49 | LastPpi->Flags |= EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;\r |
50 | \r | |
40b0b23e MK |
51 | *PpiList = (EFI_PEI_PPI_DESCRIPTOR *)ListBase;\r |
52 | *PpiListSize = sizeof (gCommonPpiTable) + PlatformPpiListSize;\r | |
77de7e53 | 53 | }\r |
54 | \r | |
1d5d0ae9 | 55 | VOID\r |
56 | CEntryPoint (\r | |
0787bc61 | 57 | IN UINTN MpId,\r |
1d5d0ae9 | 58 | IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint\r |
59 | )\r | |
60 | {\r | |
6dafb303 OM |
61 | // Data Cache enabled on Primary core when MMU is enabled.\r |
62 | ArmDisableDataCache ();\r | |
6dafb303 | 63 | // Invalidate instruction cache\r |
a9d7090f | 64 | ArmInvalidateInstructionCache ();\r |
6dafb303 | 65 | // Enable Instruction Caches on all cores.\r |
f598bf12 | 66 | ArmEnableInstructionCache ();\r |
1d5d0ae9 | 67 | \r |
40b0b23e MK |
68 | InvalidateDataCacheRange (\r |
69 | (VOID *)(UINTN)PcdGet64 (PcdCPUCoresStackBase),\r | |
70 | PcdGet32 (PcdCPUCorePrimaryStackSize)\r | |
71 | );\r | |
6c9a3d42 | 72 | \r |
1d5d0ae9 | 73 | //\r |
74 | // Note: Doesn't have to Enable CPU interface in non-secure world,\r | |
75 | // as Non-secure interface is already enabled in Secure world.\r | |
76 | //\r | |
77 | \r | |
a9d7090f | 78 | // Write VBAR - The Exception Vector table must be aligned to its requirement\r |
6d0ca257 OM |
79 | // Note: The AArch64 Vector table must be 2k-byte aligned - if this assertion fails ensure\r |
80 | // 'Align=4K' is defined into your FDF for this module.\r | |
81 | ASSERT (((UINTN)PeiVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);\r | |
a9d7090f | 82 | ArmWriteVBar ((UINTN)PeiVectorTable);\r |
1d5d0ae9 | 83 | \r |
a6a835bd AB |
84 | // Enable Floating Point\r |
85 | if (FixedPcdGet32 (PcdVFPEnabled)) {\r | |
86 | ArmEnableVFP ();\r | |
87 | }\r | |
88 | \r | |
40b0b23e | 89 | // Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on.\r |
1d5d0ae9 | 90 | \r |
77de7e53 | 91 | // If not primary Jump to Secondary Main\r |
bebda7ce | 92 | if (ArmPlatformIsPrimaryCore (MpId)) {\r |
a6caee65 | 93 | // Initialize the Debug Agent for Source Level Debugging\r |
94 | InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);\r | |
95 | SaveAndSetDebugTimerInterrupt (TRUE);\r | |
96 | \r | |
f437141a | 97 | // Initialize the platform specific controllers\r |
98 | ArmPlatformInitialize (MpId);\r | |
99 | \r | |
a6caee65 | 100 | // Goto primary Main.\r |
f598bf12 | 101 | PrimaryMain (PeiCoreEntryPoint);\r |
1d5d0ae9 | 102 | } else {\r |
0787bc61 | 103 | SecondaryMain (MpId);\r |
1d5d0ae9 | 104 | }\r |
105 | \r | |
106 | // PEI Core should always load and never return\r | |
107 | ASSERT (FALSE);\r | |
108 | }\r | |
109 | \r | |
110 | EFI_STATUS\r | |
111 | EFIAPI\r | |
93d451c6 | 112 | PrePeiCoreTemporaryRamSupport (\r |
40b0b23e MK |
113 | IN CONST EFI_PEI_SERVICES **PeiServices,\r |
114 | IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,\r | |
115 | IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,\r | |
116 | IN UINTN CopySize\r | |
1d5d0ae9 | 117 | )\r |
118 | {\r | |
40b0b23e MK |
119 | VOID *OldHeap;\r |
120 | VOID *NewHeap;\r | |
121 | VOID *OldStack;\r | |
122 | VOID *NewStack;\r | |
123 | UINTN HeapSize;\r | |
4960d8e0 HG |
124 | \r |
125 | HeapSize = ALIGN_VALUE (CopySize / 2, CPU_STACK_ALIGNMENT);\r | |
93d451c6 | 126 | \r |
40b0b23e MK |
127 | OldHeap = (VOID *)(UINTN)TemporaryMemoryBase;\r |
128 | NewHeap = (VOID *)((UINTN)PermanentMemoryBase + (CopySize - HeapSize));\r | |
93d451c6 | 129 | \r |
40b0b23e MK |
130 | OldStack = (VOID *)((UINTN)TemporaryMemoryBase + HeapSize);\r |
131 | NewStack = (VOID *)(UINTN)PermanentMemoryBase;\r | |
93d451c6 | 132 | \r |
133 | //\r | |
134 | // Migrate the temporary memory stack to permanent memory stack.\r | |
1d5d0ae9 | 135 | //\r |
4960d8e0 | 136 | CopyMem (NewStack, OldStack, CopySize - HeapSize);\r |
93d451c6 | 137 | \r |
138 | //\r | |
139 | // Migrate the temporary memory heap to permanent memory heap.\r | |
f598bf12 | 140 | //\r |
4960d8e0 | 141 | CopyMem (NewHeap, OldHeap, HeapSize);\r |
3402aac7 | 142 | \r |
93d451c6 | 143 | SecSwitchStack ((UINTN)NewStack - (UINTN)OldStack);\r |
1d5d0ae9 | 144 | \r |
93d451c6 | 145 | return EFI_SUCCESS;\r |
146 | }\r |