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1d5d0ae9 | 1 | /** @file\r |
2 | * Main file supporting the transition to PEI Core in Normal World for Versatile Express\r | |
3 | *\r | |
4 | * Copyright (c) 2011, ARM Limited. All rights reserved.\r | |
5 | * \r | |
6 | * This program and the accompanying materials \r | |
7 | * are licensed and made available under the terms and conditions of the BSD License \r | |
8 | * which accompanies this distribution. The full text of the license may be found at \r | |
9 | * http://opensource.org/licenses/bsd-license.php \r | |
10 | *\r | |
11 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
12 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
13 | *\r | |
14 | **/\r | |
15 | \r | |
16 | #include <PiPei.h>\r | |
17 | #include <Ppi/TemporaryRamSupport.h>\r | |
18 | #include <Library/DebugLib.h>\r | |
19 | #include <Library/PcdLib.h>\r | |
20 | #include <Library/IoLib.h>\r | |
21 | #include <Library/BaseLib.h>\r | |
22 | #include <Library/BaseMemoryLib.h>\r | |
23 | #include <Library/ArmLib.h>\r | |
24 | #include <Chipset/ArmV7.h>\r | |
25 | \r | |
26 | EFI_STATUS\r | |
27 | EFIAPI\r | |
28 | SecTemporaryRamSupport (\r | |
29 | IN CONST EFI_PEI_SERVICES **PeiServices,\r | |
30 | IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,\r | |
31 | IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,\r | |
32 | IN UINTN CopySize\r | |
33 | );\r | |
34 | \r | |
35 | VOID\r | |
36 | SecSwitchStack (\r | |
37 | INTN StackDelta\r | |
38 | );\r | |
39 | \r | |
40 | TEMPORARY_RAM_SUPPORT_PPI mSecTemporaryRamSupportPpi = {SecTemporaryRamSupport};\r | |
41 | \r | |
42 | EFI_PEI_PPI_DESCRIPTOR gSecPpiTable[] = {\r | |
43 | {\r | |
44 | EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r | |
45 | &gEfiTemporaryRamSupportPpiGuid,\r | |
46 | &mSecTemporaryRamSupportPpi\r | |
47 | }\r | |
48 | };\r | |
49 | \r | |
50 | // Vector Table for Pei Phase\r | |
51 | VOID PeiVectorTable (VOID);\r | |
52 | \r | |
53 | \r | |
54 | VOID\r | |
55 | CEntryPoint (\r | |
56 | IN UINTN CoreId,\r | |
57 | IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint\r | |
58 | )\r | |
59 | {\r | |
60 | //Clean Data cache\r | |
61 | ArmCleanInvalidateDataCache();\r | |
62 | \r | |
63 | //Invalidate instruction cache\r | |
64 | ArmInvalidateInstructionCache();\r | |
65 | \r | |
66 | // Enable Instruction & Data caches\r | |
67 | ArmEnableDataCache();\r | |
68 | ArmEnableInstructionCache();\r | |
69 | \r | |
70 | //\r | |
71 | // Note: Doesn't have to Enable CPU interface in non-secure world,\r | |
72 | // as Non-secure interface is already enabled in Secure world.\r | |
73 | //\r | |
74 | \r | |
75 | // Write VBAR - The Vector table must be 32-byte aligned\r | |
76 | ASSERT(((UINT32)PeiVectorTable & ((1 << 5)-1)) == 0);\r | |
77 | ArmWriteVBar((UINT32)PeiVectorTable);\r | |
78 | \r | |
79 | //Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on.\r | |
80 | \r | |
81 | //If not primary Jump to Secondary Main\r | |
82 | if(0 == CoreId) {\r | |
83 | //Goto primary Main.\r | |
84 | primary_main(PeiCoreEntryPoint);\r | |
85 | } else {\r | |
86 | secondary_main(CoreId);\r | |
87 | }\r | |
88 | \r | |
89 | // PEI Core should always load and never return\r | |
90 | ASSERT (FALSE);\r | |
91 | }\r | |
92 | \r | |
93 | EFI_STATUS\r | |
94 | EFIAPI\r | |
95 | SecTemporaryRamSupport (\r | |
96 | IN CONST EFI_PEI_SERVICES **PeiServices,\r | |
97 | IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,\r | |
98 | IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,\r | |
99 | IN UINTN CopySize\r | |
100 | )\r | |
101 | {\r | |
102 | //\r | |
103 | // Migrate the whole temporary memory to permenent memory.\r | |
104 | // \r | |
105 | CopyMem (\r | |
106 | (VOID*)(UINTN)PermanentMemoryBase, \r | |
107 | (VOID*)(UINTN)TemporaryMemoryBase, \r | |
108 | CopySize\r | |
109 | );\r | |
110 | \r | |
111 | SecSwitchStack((UINTN)(PermanentMemoryBase - TemporaryMemoryBase));\r | |
112 | \r | |
113 | return EFI_SUCCESS;\r | |
114 | }\r | |
115 | \r | |
116 | VOID PeiCommonExceptionEntry(UINT32 Entry, UINT32 LR) {\r | |
117 | switch (Entry) {\r | |
118 | case 0:\r | |
119 | DEBUG((EFI_D_ERROR,"Reset Exception at 0x%X\n",LR));\r | |
120 | break;\r | |
121 | case 1:\r | |
122 | DEBUG((EFI_D_ERROR,"Undefined Exception at 0x%X\n",LR));\r | |
123 | break;\r | |
124 | case 2:\r | |
125 | DEBUG((EFI_D_ERROR,"SWI Exception at 0x%X\n",LR));\r | |
126 | break;\r | |
127 | case 3:\r | |
128 | DEBUG((EFI_D_ERROR,"PrefetchAbort Exception at 0x%X\n",LR));\r | |
129 | break;\r | |
130 | case 4:\r | |
131 | DEBUG((EFI_D_ERROR,"DataAbort Exception at 0x%X\n",LR));\r | |
132 | break;\r | |
133 | case 5:\r | |
134 | DEBUG((EFI_D_ERROR,"Reserved Exception at 0x%X\n",LR));\r | |
135 | break;\r | |
136 | case 6:\r | |
137 | DEBUG((EFI_D_ERROR,"IRQ Exception at 0x%X\n",LR));\r | |
138 | break;\r | |
139 | case 7:\r | |
140 | DEBUG((EFI_D_ERROR,"FIQ Exception at 0x%X\n",LR));\r | |
141 | break;\r | |
142 | default:\r | |
143 | DEBUG((EFI_D_ERROR,"Unknown Exception at 0x%X\n",LR));\r | |
144 | break;\r | |
145 | }\r | |
146 | while(1);\r | |
147 | }\r |