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cd872e40 1/** @file\r
2*\r
1b0ac0de 3* Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
cd872e40 4*\r
5* This program and the accompanying materials\r
6* are licensed and made available under the terms and conditions of the BSD License\r
7* which accompanies this distribution. The full text of the license may be found at\r
8* http://opensource.org/licenses/bsd-license.php\r
9*\r
10* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12*\r
13**/\r
14\r
15#include "PrePi.h"\r
16\r
55a0d64b 17#include <Library/ArmGicLib.h>\r
cd872e40 18\r
99565b88 19#include <Ppi/ArmMpCoreInfo.h>\r
20\r
cd872e40 21VOID\r
22PrimaryMain (\r
23 IN UINTN UefiMemoryBase,\r
c524ffbb 24 IN UINTN StacksBase,\r
25 IN UINTN GlobalVariableBase,\r
cd872e40 26 IN UINT64 StartTimeStamp\r
27 )\r
28{\r
55a0d64b 29 // Enable the GIC Distributor\r
30 ArmGicEnableDistributor(PcdGet32(PcdGicDistributorBase));\r
cd872e40 31\r
0dbbacdf 32 // In some cases, the secondary cores are waiting for an SGI from the next stage boot loader to resume their initialization\r
d269095b 33 if (!FixedPcdGet32(PcdSendSgiToBringUpSecondaryCores)) {\r
cd872e40 34 // Sending SGI to all the Secondary CPU interfaces\r
4c19ece3 35 ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));\r
cd872e40 36 }\r
37\r
c524ffbb 38 PrePiMain (UefiMemoryBase, StacksBase, GlobalVariableBase, StartTimeStamp);\r
cd872e40 39\r
40 // We must never return\r
41 ASSERT(FALSE);\r
42}\r
43\r
44VOID\r
45SecondaryMain (\r
0787bc61 46 IN UINTN MpId\r
cd872e40 47 )\r
48{\r
99565b88 49 EFI_STATUS Status;\r
50 ARM_MP_CORE_INFO_PPI *ArmMpCoreInfoPpi;\r
51 UINTN Index;\r
52 UINTN ArmCoreCount;\r
53 ARM_CORE_INFO *ArmCoreInfoTable;\r
54 UINT32 ClusterId;\r
55 UINT32 CoreId;\r
56 VOID (*SecondaryStart)(VOID);\r
57 UINTN SecondaryEntryAddr;\r
1b0ac0de
OM
58 UINTN AcknowledgeInterrupt;\r
59 UINTN InterruptId;\r
99565b88 60\r
61 ClusterId = GET_CLUSTER_ID(MpId);\r
62 CoreId = GET_CORE_ID(MpId);\r
63\r
64 // On MP Core Platform we must implement the ARM MP Core Info PPI (gArmMpCoreInfoPpiGuid)\r
65 Status = GetPlatformPpi (&gArmMpCoreInfoPpiGuid, (VOID**)&ArmMpCoreInfoPpi);\r
66 ASSERT_EFI_ERROR (Status);\r
67\r
68 ArmCoreCount = 0;\r
69 Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);\r
70 ASSERT_EFI_ERROR (Status);\r
71\r
72 // Find the core in the ArmCoreTable\r
73 for (Index = 0; Index < ArmCoreCount; Index++) {\r
74 if ((ArmCoreInfoTable[Index].ClusterId == ClusterId) && (ArmCoreInfoTable[Index].CoreId == CoreId)) {\r
75 break;\r
76 }\r
77 }\r
78\r
79 // The ARM Core Info Table must define every core\r
80 ASSERT (Index != ArmCoreCount);\r
cd872e40 81\r
82 // Clear Secondary cores MailBox\r
99565b88 83 MmioWrite32 (ArmCoreInfoTable[Index].MailboxClearAddress, ArmCoreInfoTable[Index].MailboxClearValue);\r
cd872e40 84\r
315649cd 85 do {\r
99565b88 86 ArmCallWFI ();\r
315649cd 87\r
88 // Read the Mailbox\r
89 SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress);\r
90\r
cd872e40 91 // Acknowledge the interrupt and send End of Interrupt signal.\r
1b0ac0de 92 AcknowledgeInterrupt = ArmGicAcknowledgeInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase), &InterruptId);\r
2ca815a4 93 // Check if it is a valid interrupt ID\r
1b0ac0de 94 if (InterruptId < ArmGicGetMaxNumInterrupts (PcdGet32 (PcdGicDistributorBase))) {\r
2ca815a4 95 // Got a valid SGI number hence signal End of Interrupt\r
1b0ac0de 96 ArmGicEndOfInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase), AcknowledgeInterrupt);\r
2ca815a4 97 }\r
f93f248a 98 } while (SecondaryEntryAddr == 0);\r
cd872e40 99\r
cd872e40 100 // Jump to secondary core entry point.\r
99565b88 101 SecondaryStart = (VOID (*)())SecondaryEntryAddr;\r
102 SecondaryStart();\r
cd872e40 103\r
104 // The secondaries shouldn't reach here\r
105 ASSERT(FALSE);\r
106}\r