ArmPkg: Renamed library 'PL390GicLib' into 'ArmGicLib'

[mirror_edk2.git] / ArmPlatformPkg / Sec / SecEntryPoint.S

#------------------------------------------------------------------------------ \r
#\r
# ARM VE Entry point. Reset vector in FV header will brach to\r
# _ModuleEntryPoint. \r
#\r
#  Copyright (c) 2011, ARM Limited. All rights reserved.\r
#  \r
#  This program and the accompanying materials                          \r
#  are licensed and made available under the terms and conditions of the BSD License         \r
#  which accompanies this distribution.  The full text of the license may be found at        \r
#  http://opensource.org/licenses/bsd-license.php                                            \r
#\r
#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
#\r
#------------------------------------------------------------------------------\r
\r
#include <AsmMacroIoLib.h>\r
#include <Base.h>\r
#include <Library/PcdLib.h>\r
#include <Library/ArmPlatformLib.h>\r
#include <AutoGen.h>\r
\r
#Start of Code section\r
.text\r
.align 3\r
\r
#make _ModuleEntryPoint as global\r
GCC_ASM_EXPORT(_ModuleEntryPoint)\r
\r
#global functions referenced by this module\r
GCC_ASM_IMPORT(CEntryPoint)\r
GCC_ASM_IMPORT(ArmPlatformIsMemoryInitialized)\r
GCC_ASM_IMPORT(ArmPlatformInitializeBootMemory)\r
GCC_ASM_IMPORT(ArmDisableInterrupts)\r
GCC_ASM_IMPORT(ArmDisableCachesAndMmu)\r
GCC_ASM_IMPORT(ArmWriteVBar)\r
GCC_ASM_IMPORT(SecVectorTable)\r
\r
#if (FixedPcdGet32(PcdMPCoreSupport))\r
GCC_ASM_IMPORT(ArmIsScuEnable)\r
#endif\r
\r
StartupAddr:        .word   ASM_PFX(CEntryPoint)\r
SecVectorTableAddr: .word		ASM_PFX(SecVectorTable)\r
\r
ASM_PFX(_ModuleEntryPoint):\r
 #Set VBAR to the start of the exception vectors in Secure Mode\r
  ldr   r0, SecVectorTableAddr\r
  bl   ASM_PFX(ArmWriteVBar)\r
\r
  # First ensure all interrupts are disabled\r
  bl   ASM_PFX(ArmDisableInterrupts)\r
\r
  # Ensure that the MMU and caches are off\r
  bl  ASM_PFX(ArmDisableCachesAndMmu)\r
\r
_IdentifyCpu: \r
  # Identify CPU ID\r
  bl    ASM_PFX(ArmReadMpidr)\r
  and   r5, r0, #0xf\r
  \r
  #get ID of this CPU in Multicore system\r
  cmp   r5, #0\r
  # Only the primary core initialize the memory (SMC)\r
  beq   _InitMem\r
  \r
#if (FixedPcdGet32(PcdMPCoreSupport))\r
  # ... The secondary cores wait for SCU to be enabled\r
_WaitForEnabledScu:\r
  bl    ASM_PFX(ArmIsScuEnable)\r
  tst   r1, #1\r
  beq   _WaitForEnabledScu\r
  b     _SetupStack\r
#endif\r
  \r
_InitMem:\r
  bl    ASM_PFX(ArmPlatformIsMemoryInitialized)\r
  bne   _SetupStack\r
  \r
  # Initialize Init Memory\r
  bl    ASM_PFX(ArmPlatformInitializeBootMemory)\r
\r
  # Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)\r
  mov   r5, #0\r
 \r
_SetupStack:\r
  # Setup Stack for the 4 CPU cores\r
  #Read Stack Base address from PCD\r
  LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)\r
\r
  #read Stack size from PCD\r
  LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecStackSize), r2)\r
\r
  #calcuate Stack Pointer reg value using Stack size and CPU ID.\r
  mov     r3,r5         @ r3 = core_id\r
  mul     r3,r3,r2      @ r3 = core_id * stack_size = offset from the stack base\r
  add     r3,r3,r1      @ r3 ldr= stack_base + offset\r
  mov     sp, r3\r
  \r
  # move sec startup address into a data register\r
  # ensure we're jumping to FV version of the code (not boot remapped alias)\r
  ldr   r3, StartupAddr\r
  \r
  # Move the CoreId in r0 to be the first argument of the SEC Entry Point\r
  mov   r0, r5\r
\r
  # jump to SEC C code\r
  #    r0 = core_id\r
  blx  r3\r
\r
\r