projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 92032841 | 1 | /*++\r |
| 2 | \r | |
| 1a6f1b55 HT |
3 | Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>\r |
| 4 | This program and the accompanying materials \r | |
| 92032841 | 5 | are licensed and made available under the terms and conditions of the BSD License \r |
| 6 | which accompanies this distribution. The full text of the license may be found at \r | |
| 7 | http://opensource.org/licenses/bsd-license.php \r | |
| 8 | \r | |
| 9 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
| 10 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
| 11 | \r | |
| 12 | Module Name:\r | |
| 13 | \r | |
| 14 | Timer.h\r | |
| 15 | \r | |
| 16 | Abstract:\r | |
| 17 | \r | |
| 18 | Driver implementing the EFI 2.0 timer protocol using the ARM SP804 timer.\r | |
| 19 | \r | |
| 20 | --*/\r | |
| 21 | \r | |
| 22 | #ifndef _TIMER_SP804_H__\r | |
| 23 | #define _TIMER_SP804_H__\r | |
| 24 | \r | |
| 25 | \r | |
| 26 | \r | |
| 27 | // EB board constants\r | |
| 28 | #define EB_SP810_CTRL_BASE 0x10001000\r | |
| 29 | #define EB_SP804_TIMER0_BASE 0x10011000\r | |
| 30 | #define EB_SP804_TIMER1_BASE 0x10011020\r | |
| 31 | #define EB_SP804_TIMER2_BASE 0x10012000\r | |
| 32 | #define EB_SP804_TIMER3_BASE 0x10012020\r | |
| 33 | \r | |
| 34 | #define EB_TIMER01_INTERRUPT_NUM 36\r | |
| 35 | #define EB_TIMER23_INTERRUPT_NUM 37\r | |
| 36 | \r | |
| 37 | // SP804 Timer constants\r | |
| 38 | #define SP804_TIMER_LOAD_REG 0x00\r | |
| 39 | #define SP804_TIMER_CURRENT_REG 0x04\r | |
| 40 | #define SP804_TIMER_CONTROL_REG 0x08\r | |
| 41 | #define SP804_TIMER_INT_CLR_REG 0x0C\r | |
| 42 | #define SP804_TIMER_RAW_INT_STS_REG 0x10\r | |
| 43 | #define SP804_TIMER_MSK_INT_STS_REG 0x14\r | |
| 44 | #define SP804_TIMER_BG_LOAD_REG 0x18\r | |
| 45 | \r | |
| 46 | // Timer control register bit definitions\r | |
| 47 | #define SP804_TIMER_CTRL_ONESHOT BIT0\r | |
| 48 | #define SP804_TIMER_CTRL_32BIT BIT1\r | |
| 49 | #define SP804_TIMER_CTRL_PRESCALE_MASK (BIT3|BIT2)\r | |
| 50 | #define SP804_PRESCALE_DIV_1 0\r | |
| 51 | #define SP804_PRESCALE_DIV_16 BIT2\r | |
| 52 | #define SP804_PRESCALE_DIV_256 BIT3\r | |
| 53 | #define SP804_TIMER_CTRL_INT_ENABLE BIT5\r | |
| 54 | #define SP804_TIMER_CTRL_PERIODIC BIT6\r | |
| 55 | #define SP804_TIMER_CTRL_ENABLE BIT7\r | |
| 56 | \r | |
| 57 | // SP810 System Controller constants\r | |
| 58 | #define SP810_SYS_CTRL_REG 0x00\r | |
| 59 | #define SP810_SYS_CTRL_TIMER0_TIMCLK BIT15 // 0=REFCLK, 1=TIMCLK\r | |
| 60 | #define SP810_SYS_CTRL_TIMER0_EN BIT16\r | |
| 61 | #define SP810_SYS_CTRL_TIMER1_TIMCLK BIT17 // 0=REFCLK, 1=TIMCLK\r | |
| 62 | #define SP810_SYS_CTRL_TIMER1_EN BIT18\r | |
| 63 | #define SP810_SYS_CTRL_TIMER2_TIMCLK BIT19 // 0=REFCLK, 1=TIMCLK\r | |
| 64 | #define SP810_SYS_CTRL_TIMER2_EN BIT20\r | |
| 65 | #define SP810_SYS_CTRL_TIMER3_TIMCLK BIT21 // 0=REFCLK, 1=TIMCLK\r | |
| 66 | #define SP810_SYS_CTRL_TIMER3_EN BIT22\r | |
| 67 | \r | |
| 68 | // default timer tick period - 1ms, or 10000 units of 100ns\r | |
| 69 | //#define TIMER_DEFAULT_PERIOD 10000\r | |
| 70 | \r | |
| 71 | // default timer tick period - 50ms, or 500000 units of 100ns\r | |
| 72 | #define TIMER_DEFAULT_PERIOD 500000\r | |
| 73 | \r | |
| 74 | // default timer tick period - 500ms, or 5000000 units of 100ns\r | |
| 75 | //#define TIMER_DEFAULT_PERIOD 5000000\r | |
| 76 | \r | |
| 77 | #endif\r | |
| 78 | \r |