Add support for a RELASE build
[mirror_edk2.git] / BeagleBoardPkg / Sec / Sec.c
CommitLineData
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1/** @file\r
2 C Entry point for the SEC. First C code after the reset vector.\r
3\r
4 Copyright (c) 2008-2009, Apple Inc. All rights reserved.\r
5 \r
6 All rights reserved. This program and the accompanying materials\r
7 are licensed and made available under the terms and conditions of the BSD License\r
8 which accompanies this distribution. The full text of the license may be found at\r
9 http://opensource.org/licenses/bsd-license.php\r
10\r
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13\r
14**/\r
15\r
16#include <PiPei.h>\r
17\r
18#include <Library/DebugLib.h>\r
19#include <Library/PrePiLib.h>\r
20#include <Library/PcdLib.h>\r
21#include <Library/IoLib.h>\r
22#include <Library/OmapLib.h>\r
23#include <Library/ArmLib.h>\r
225290eb 24#include <Library/PeCoffGetEntryPointLib.h>\r
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25\r
26#include <Ppi/GuidedSectionExtraction.h>\r
27\r
28#include <Omap3530/Omap3530.h>\r
29\r
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30VOID\r
31EFIAPI \r
32_ModuleEntryPoint(\r
33 VOID\r
34 );\r
35\r
36CHAR8 *\r
37DeCygwinPathIfNeeded (\r
38 IN CHAR8 *Name\r
39 );\r
40\r
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41VOID\r
42PadConfiguration (\r
43 VOID\r
44 );\r
45\r
46VOID\r
47ClockInit (\r
48 VOID\r
49 );\r
50\r
51VOID\r
52TimerInit (\r
53 VOID\r
54 )\r
55{\r
56 UINTN Timer = FixedPcdGet32(PcdBeagleFreeTimer);\r
57 UINT32 TimerBaseAddress = TimerBase(Timer);\r
58\r
59 // Set source clock for GPT3 & GPT4 to SYS_CLK\r
60 MmioOr32(CM_CLKSEL_PER, CM_CLKSEL_PER_CLKSEL_GPT3_SYS \r
61 | CM_CLKSEL_PER_CLKSEL_GPT4_SYS);\r
62\r
63 // Set count & reload registers\r
64 MmioWrite32(TimerBaseAddress + GPTIMER_TCRR, 0x00000000);\r
65 MmioWrite32(TimerBaseAddress + GPTIMER_TLDR, 0x00000000);\r
66\r
67 // Disable interrupts\r
68 MmioWrite32(TimerBaseAddress + GPTIMER_TIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_DISABLE | TIER_MAT_IT_DISABLE);\r
69\r
70 // Start Timer\r
71 MmioWrite32(TimerBaseAddress + GPTIMER_TCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON);\r
72\r
73 //Disable OMAP Watchdog timer (WDT2)\r
74 MmioWrite32(WDTIMER2_BASE + WSPR, 0xAAAA);\r
75 DEBUG ((EFI_D_ERROR, "Magic delay to disable watchdog timers properly.\n"));\r
76 MmioWrite32(WDTIMER2_BASE + WSPR, 0x5555);\r
77}\r
78\r
79VOID\r
80UartInit (\r
81 VOID\r
82 )\r
83{\r
84 UINTN Uart = FixedPcdGet32(PcdBeagleConsoleUart);\r
85 UINT32 UartBaseAddress = UartBase(Uart);\r
86\r
87 // Set MODE_SELECT=DISABLE before trying to initialize or modify DLL, DLH registers.\r
88 MmioWrite32(UartBaseAddress + UART_MDR1_REG, UART_MDR1_MODE_SELECT_DISABLE);\r
89\r
90 // Put device in configuration mode.\r
91 MmioWrite32(UartBaseAddress + UART_LCR_REG, UART_LCR_DIV_EN_ENABLE);\r
92\r
93 // Programmable divisor N = 48Mhz/16/115200 = 26\r
94 MmioWrite32(UartBaseAddress + UART_DLL_REG, 26); // low divisor\r
95 MmioWrite32(UartBaseAddress + UART_DLH_REG, 0); // high divisor\r
96\r
97 // Enter into UART operational mode.\r
98 MmioWrite32(UartBaseAddress + UART_LCR_REG, UART_LCR_DIV_EN_DISABLE | UART_LCR_CHAR_LENGTH_8);\r
99\r
100 // Force DTR and RTS output to active\r
101 MmioWrite32(UartBaseAddress + UART_MCR_REG, UART_MCR_RTS_FORCE_ACTIVE | UART_MCR_DTR_FORCE_ACTIVE);\r
102\r
103 // Clear & enable fifos\r
104 MmioWrite32(UartBaseAddress + UART_FCR_REG, UART_FCR_TX_FIFO_CLEAR | UART_FCR_RX_FIFO_CLEAR | UART_FCR_FIFO_ENABLE); \r
105\r
106 // Restore MODE_SELECT \r
107 MmioWrite32(UartBaseAddress + UART_MDR1_REG, UART_MDR1_MODE_SELECT_UART_16X);\r
108}\r
109\r
110VOID\r
111InitCache (\r
112 IN UINT32 MemoryBase,\r
113 IN UINT32 MemoryLength\r
114 );\r
115\r
116EFI_STATUS\r
117EFIAPI\r
118ExtractGuidedSectionLibConstructor (\r
119 VOID\r
120 );\r
121\r
122EFI_STATUS\r
123EFIAPI\r
124LzmaDecompressLibConstructor (\r
125 VOID\r
126 );\r
127\r
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128/**\r
129 If the build is done on cygwin the paths are cygpaths. \r
130 /cygdrive/c/tmp.txt vs c:\tmp.txt so we need to convert\r
131 them to work with RVD commands\r
132\r
133 This is just code to help print out RVD symbol load command.\r
134 If you build with cygwin paths aren't compatible with RVD.\r
135\r
136 @param Name Path to convert if needed\r
137\r
138**/\r
139CHAR8 *\r
140SecDeCygwinPathIfNeeded (\r
141 IN CHAR8 *Name\r
142 )\r
143{\r
144 CHAR8 *Ptr;\r
145 UINTN Index;\r
146 UINTN Len;\r
147 \r
148 Ptr = AsciiStrStr (Name, "/cygdrive/");\r
149 if (Ptr == NULL) {\r
150 return Name;\r
151 }\r
152 \r
153 Len = AsciiStrLen (Ptr);\r
154 \r
155 // convert "/cygdrive" to spaces\r
156 for (Index = 0; Index < 9; Index++) {\r
157 Ptr[Index] = ' ';\r
158 }\r
159\r
160 // convert /c to c:\r
161 Ptr[9] = Ptr[10];\r
162 Ptr[10] = ':';\r
163 \r
164 // switch path seperators\r
165 for (Index = 11; Index < Len; Index++) {\r
166 if (Ptr[Index] == '/') {\r
167 Ptr[Index] = '\\' ;\r
168 }\r
169 }\r
170\r
171 return Name;\r
172}\r
173\r
174\r
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175VOID\r
176CEntryPoint (\r
177 IN VOID *MemoryBase,\r
178 IN UINTN MemorySize,\r
179 IN VOID *StackBase,\r
180 IN UINTN StackSize\r
181 )\r
182{\r
183 VOID *HobBase;\r
184\r
185 //Set up Pin muxing.\r
186 PadConfiguration();\r
187\r
188 // Set up system clocking\r
189 ClockInit();\r
190\r
191 // Build a basic HOB list\r
192 HobBase = (VOID *)(UINTN)(FixedPcdGet32(PcdEmbeddedFdBaseAddress) + FixedPcdGet32(PcdEmbeddedFdSize));\r
193 CreateHobList(MemoryBase, MemorySize, HobBase, StackBase);\r
194\r
195 // Enable program flow prediction, if supported.\r
196 ArmEnableBranchPrediction();\r
197\r
198 // Initialize CPU cache\r
199 InitCache((UINT32)MemoryBase, (UINT32)MemorySize);\r
200\r
201 // Add memory allocation hob for relocated FD\r
202 BuildMemoryAllocationHob(FixedPcdGet32(PcdEmbeddedFdBaseAddress), FixedPcdGet32(PcdEmbeddedFdSize), EfiBootServicesData);\r
203\r
204 // Add the FVs to the hob list\r
205 BuildFvHob(PcdGet32(PcdFlashFvMainBase), PcdGet32(PcdFlashFvMainSize));\r
206\r
207 // Start talking\r
208 UartInit();\r
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209 DEBUG((EFI_D_ERROR, "UART Enabled\n"));\r
210\r
211 DEBUG_CODE_BEGIN ();\r
212 //\r
213 // On a debug build print out information about the SEC. This is really info about\r
214 // the PE/COFF file we are currently running from. Useful for loading symbols in a\r
215 // debugger. Remember our image is really part of the FV.\r
216 //\r
217 RETURN_STATUS Status;\r
218 EFI_PEI_FV_HANDLE VolumeHandle;\r
219 EFI_PEI_FILE_HANDLE FileHandle;\r
220 VOID *PeCoffImage;\r
221 UINT32 Offset;\r
222 CHAR8 *FilePath;\r
223
224 FfsAnyFvFindFirstFile (EFI_FV_FILETYPE_SECURITY_CORE, &VolumeHandle, &FileHandle);
225 Status = FfsFindSectionData (EFI_SECTION_TE, FileHandle, &PeCoffImage);
226 if (EFI_ERROR (Status)) {
227 // Usually is a TE (PI striped down PE/COFF), but could be a full PE/COFF
228 Status = FfsFindSectionData (EFI_SECTION_PE32, FileHandle, &PeCoffImage);
229 }
230 if (!EFI_ERROR (Status)) {
231 Offset = PeCoffGetSizeOfHeaders (PeCoffImage);\r
232 FilePath = PeCoffLoaderGetPdbPointer (PeCoffImage);
233 if (FilePath != NULL) {
234
235 //
236 // In general you should never have to use #ifdef __CC_ARM in the code. It
237 // is hidden in the away in the MdePkg. But here we would like to print differnt things
238 // for different toolchains.
239 //
240#ifdef __CC_ARM
241 // Print out the command for the RVD debugger to load symbols for this image
920cb926 242 DEBUG ((EFI_D_ERROR, "load /a /ni /np %a &0x%08x\n", SecDeCygwinPathIfNeeded (FilePath), (CHAR8 *)PeCoffImage + Offset));
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243#elif __GNUC__\r
244 // This may not work correctly if you generate PE/COFF directlyas then the Offset would not be required
245 DEBUG ((EFI_D_ERROR, "add-symbol-file %a 0x%08x\n", FilePath, PeCoffImage + Offset));
246#else\r
247 DEBUG ((EFI_D_ERROR, "SEC starts at 0x%08x with an entry point at 0x%08x %a\n", PeCoffImage, _ModuleEntryPoint, FilePath));
248#endif\r
249 }\r
250 }
251
252 DEBUG_CODE_END ();\r
253\r
254\r
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255\r
256 // Start up a free running time so that the timer lib will work\r
257 TimerInit();\r
258\r
259 // SEC phase needs to run library constructors by hand.\r
260 ExtractGuidedSectionLibConstructor();\r
261 LzmaDecompressLibConstructor();\r
262\r
8c3f387b 263 DecompressFirstFv ();\r
264\r
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265 // Load the DXE Core and transfer control to it\r
266 LoadDxeCoreFromFv(NULL, 0);\r
267 \r
268 // DXE Core should always load and never return\r
269 ASSERT(FALSE);\r
270}\r
271\r