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1/*++
2
3Copyright (c) 2005 - 2007, Intel Corporation. All rights reserved.<BR>
4This program and the accompanying materials
5are licensed and made available under the terms and conditions of the BSD License
6which accompanies this distribution. The full text of the license may be found at
7http://opensource.org/licenses/bsd-license.php
8
9THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
11
12Module Name:
13
14 PciBus.h
15
16Abstract:
17
18 PCI Bus Driver
19
20Revision History
21
22--*/
23
24#ifndef _EFI_PCI_BUS_H
25#define _EFI_PCI_BUS_H
26
27#include <PiDxe.h>
28
29#include <Protocol/PciIo.h>
30#include <Protocol/PciRootBridgeIo.h>
31#include <Protocol/DevicePath.h>
32#include <Protocol/Decompress.h>
33#include <Protocol/UgaIo.h>
34#include <Protocol/LoadedImage.h>
35#include <Protocol/BusSpecificDriverOverride.h>
36
37#include <Guid/PciOptionRomTable.h>
38
39#include <IndustryStandard/Pci.h>
40#include <IndustryStandard/Acpi.h>
41#include <IndustryStandard/PeImage.h>
42
43#include <Library/DebugLib.h>
44#include <Library/UefiDriverEntryPoint.h>
45#include <Library/BaseLib.h>
46#include <Library/UefiLib.h>
47#include <Library/BaseMemoryLib.h>
48#include <Library/ReportStatusCodeLib.h>
49#include <Library/MemoryAllocationLib.h>
50#include <Library/UefiBootServicesTableLib.h>
51#include <Library/DevicePathLib.h>
52#include <Library/PcdLib.h>
53#include <Library/PeCoffLib.h>
54
55//
56// Driver Produced Protocol Prototypes
57//
58
59#define VGABASE1 0x3B0
60#define VGALIMIT1 0x3BB
61
62#define VGABASE2 0x3C0
63#define VGALIMIT2 0x3DF
64
65#define ISABASE 0x100
66#define ISALIMIT 0x3FF
67
68typedef enum {
69 PciBarTypeUnknown = 0,
70 PciBarTypeIo16,
71 PciBarTypeIo32,
72 PciBarTypeMem32,
73 PciBarTypePMem32,
74 PciBarTypeMem64,
75 PciBarTypePMem64,
76 PciBarTypeIo,
77 PciBarTypeMem,
78 PciBarTypeMaxType
79} PCI_BAR_TYPE;
80
81typedef struct {
82 UINT64 BaseAddress;
83 UINT64 Length;
84 UINT64 Alignment;
85 PCI_BAR_TYPE BarType;
86 BOOLEAN Prefetchable;
87 UINT8 MemType;
88 UINT8 Offset;
89} PCI_BAR;
90
91#define PCI_IO_DEVICE_SIGNATURE SIGNATURE_32 ('p','c','i','o')
92
93#define EFI_BRIDGE_IO32_DECODE_SUPPORTED 0x0001
94#define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED 0x0002
95#define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED 0x0004
96#define EFI_BRIDGE_IO16_DECODE_SUPPORTED 0x0008
97#define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010
98#define EFI_BRIDGE_MEM64_DECODE_SUPPORTED 0x0020
99#define EFI_BRIDGE_MEM32_DECODE_SUPPORTED 0x0040
100
101
102typedef struct _PCI_IO_DEVICE {
103 UINT32 Signature;
104 EFI_HANDLE Handle;
105 EFI_PCI_IO_PROTOCOL PciIo;
106 LIST_ENTRY Link;
107
108 EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;
109 EFI_DEVICE_PATH_PROTOCOL *DevicePath;
110 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
111
112 //
113 // PCI configuration space header type
114 //
115 PCI_TYPE00 Pci;
116
117 //
118 // Bus number, Device number, Function number
119 //
120 UINT8 BusNumber;
121 UINT8 DeviceNumber;
122 UINT8 FunctionNumber;
123
124 //
125 // BAR for this PCI Device
126 //
127 PCI_BAR PciBar[PCI_MAX_BAR];
128
129 //
130 // The bridge device this pci device is subject to
131 //
132 struct _PCI_IO_DEVICE *Parent;
133
134 //
135 // A linked list for children Pci Device if it is bridge device
136 //
137 LIST_ENTRY ChildList;
138
139 //
140 // TURE if the PCI bus driver creates the handle for this PCI device
141 //
142 BOOLEAN Registered;
143
144 //
145 // TRUE if the PCI bus driver successfully allocates the resource required by
146 // this PCI device
147 //
148 BOOLEAN Allocated;
149
150 //
151 // The attribute this PCI device currently set
152 //
153 UINT64 Attributes;
154
155 //
156 // The attributes this PCI device actually supports
157 //
158 UINT64 Supports;
159
160 //
161 // The resource decode the bridge supports
162 //
163 UINT32 Decodes;
164
165 //
166 // The OptionRom Size
167 //
168 UINT64 RomSize;
169
170 //
171 // TRUE if there is any EFI driver in the OptionRom
172 //
173 BOOLEAN BusOverride;
174
175 //
176 // A list tracking reserved resource on a bridge device
177 //
178 LIST_ENTRY ReservedResourceList;
179
180 //
181 // A list tracking image handle of platform specific overriding driver
182 //
183 LIST_ENTRY OptionRomDriverList;
184
185 BOOLEAN IsPciExp;
186
187} PCI_IO_DEVICE;
188
189
190#define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \
191 CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)
192
193#define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) \
194 CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)
195
196#define PCI_IO_DEVICE_FROM_LINK(a) \
197 CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)
198
199//
200// Global Variables
201//
202extern EFI_COMPONENT_NAME_PROTOCOL gPciBusComponentName;
203extern EFI_COMPONENT_NAME2_PROTOCOL gPciBusComponentName2;
204extern EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding;
205
206extern BOOLEAN gFullEnumeration;
207extern UINT64 gAllOne;
208extern UINT64 gAllZero;
209
210#include "PciIo.h"
211#include "PciCommand.h"
212#include "PciDeviceSupport.h"
213#include "PciEnumerator.h"
214#include "PciEnumeratorSupport.h"
215#include "PciDriverOverride.h"
216#include "PciRomTable.h"
217#include "PciOptionRomSupport.h"
218#include "PciPowerManagement.h"
219
220
221#define IS_ISA_BRIDGE(_p) IS_CLASS2 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA)
222#define IS_INTEL_ISA_BRIDGE(_p) (IS_CLASS2 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA_PDECODE) && ((_p)->Hdr.VendorId == 0x8086) && ((_p)->Hdr.DeviceId == 0x7110))
223#define IS_PCI_GFX(_p) IS_CLASS2 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_OTHER)
224
225#endif