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Add in the 1st version of ECP.
[mirror_edk2.git] / EdkCompatibilityPkg / Foundation / Cpu / Pentium / Include / CpuIA32.h
CommitLineData
3eb9473e 1/*++\r
2\r
3Copyright (c) 2004 - 2006, Intel Corporation \r
4All rights reserved. This program and the accompanying materials \r
5are licensed and made available under the terms and conditions of the BSD License \r
6which accompanies this distribution. The full text of the license may be found at \r
7http://opensource.org/licenses/bsd-license.php \r
8 \r
9THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
10WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
11\r
12Module Name:\r
13\r
14 CpuIA32.h\r
15\r
16Abstract:\r
17\r
18--*/\r
19\r
20#ifndef _CPU_IA32_H\r
21#define _CPU_IA32_H\r
22\r
23#include "Tiano.h"\r
24\r
25#define IA32API __cdecl\r
26\r
27typedef struct {\r
28 UINT32 RegEax;\r
29 UINT32 RegEbx;\r
30 UINT32 RegEcx;\r
31 UINT32 RegEdx;\r
32} EFI_CPUID_REGISTER;\r
33\r
34typedef struct {\r
35 UINT32 HeaderVersion;\r
36 UINT32 UpdateRevision;\r
37 UINT32 Date;\r
38 UINT32 ProcessorId;\r
39 UINT32 Checksum;\r
40 UINT32 LoaderRevision;\r
41 UINT32 ProcessorFlags;\r
42 UINT32 DataSize;\r
43 UINT32 TotalSize;\r
44 UINT8 Reserved[12];\r
45} EFI_CPU_MICROCODE_HEADER;\r
46\r
47typedef struct {\r
48 UINT32 ExtendedSignatureCount;\r
49 UINT32 ExtendedTableChecksum; \r
50 UINT8 Reserved[12];\r
51} EFI_CPU_MICROCODE_EXTENDED_TABLE_HEADER;\r
52\r
53typedef struct {\r
54 UINT32 ProcessorSignature;\r
55 UINT32 ProcessorFlag;\r
56 UINT32 ProcessorChecksum;\r
57} EFI_CPU_MICROCODE_EXTENDED_TABLE;\r
58\r
59typedef struct {\r
60 UINT32 Stepping : 4;\r
61 UINT32 Model : 4;\r
62 UINT32 Family : 4;\r
63 UINT32 Type : 2;\r
64 UINT32 Reserved1 : 2;\r
65 UINT32 ExtendedModel : 4;\r
66 UINT32 ExtendedFamily : 8;\r
67 UINT32 Reserved2 : 4;\r
68} EFI_CPU_VERSION;\r
69\r
70#define EFI_CPUID_SIGNATURE 0x0\r
71#define EFI_CPUID_VERSION_INFO 0x1\r
72#define EFI_CPUID_CACHE_INFO 0x2\r
73#define EFI_CPUID_SERIAL_NUMBER 0x3\r
74#define EFI_CPUID_EXTENDED_FUNCTION 0x80000000\r
75#define EFI_CPUID_EXTENDED_CPU_SIG 0x80000001\r
76#define EFI_CPUID_BRAND_STRING1 0x80000002\r
77#define EFI_CPUID_BRAND_STRING2 0x80000003\r
78#define EFI_CPUID_BRAND_STRING3 0x80000004\r
79\r
80#define EFI_MSR_IA32_PLATFORM_ID 0x17\r
81#define EFI_MSR_IA32_APIC_BASE 0x1B\r
82#define EFI_MSR_EBC_HARD_POWERON 0x2A\r
83#define EFI_MSR_EBC_SOFT_POWERON 0x2B\r
84#define BINIT_DRIVER_DISABLE 0x40\r
85#define INTERNAL_MCERR_DISABLE 0x20\r
86#define INITIATOR_MCERR_DISABLE 0x10\r
87#define EFI_MSR_EBC_FREQUENCY_ID 0x2C\r
88#define EFI_MSR_IA32_BIOS_UPDT_TRIG 0x79\r
89#define EFI_MSR_IA32_BIOS_SIGN_ID 0x8B\r
90#define EFI_MSR_PSB_CLOCK_STATUS 0xCD\r
91#define EFI_APIC_GLOBAL_ENABLE 0x800\r
92#define EFI_MSR_IA32_MISC_ENABLE 0x1A0\r
93#define LIMIT_CPUID_MAXVAL_ENABLE_BIT 0x00400000\r
94#define AUTOMATIC_THERMAL_CONTROL_ENABLE_BIT 0x00000008\r
95#define COMPATIBLE_FPU_OPCODE_ENABLE_BIT 0x00000004\r
96#define LOGICAL_PROCESSOR_PRIORITY_ENABLE_BIT 0x00000002\r
97#define FAST_STRING_ENABLE_BIT 0x00000001\r
98\r
99#define EFI_CACHE_VARIABLE_MTRR_BASE 0x200\r
100#define EFI_CACHE_VARIABLE_MTRR_END 0x20F\r
101#define EFI_CACHE_IA32_MTRR_DEF_TYPE 0x2FF\r
102#define EFI_CACHE_MTRR_VALID 0x800\r
103#define EFI_CACHE_FIXED_MTRR_VALID 0x400\r
104#define EFI_CACHE_VALID_ADDRESS 0xFFFFFF000\r
105#define EFI_MSR_VALID_MASK 0xFFFFFFFFF\r
106#define EFI_CACHE_VALID_EXTENDED_ADDRESS 0xFFFFFFFFFF000\r
107#define EFI_MSR_VALID_EXTENDED_MASK 0xFFFFFFFFFFFFF\r
108\r
109#define EFI_IA32_MTRR_FIX64K_00000 0x250\r
110#define EFI_IA32_MTRR_FIX16K_80000 0x258\r
111#define EFI_IA32_MTRR_FIX16K_A0000 0x259\r
112#define EFI_IA32_MTRR_FIX4K_C0000 0x268\r
113#define EFI_IA32_MTRR_FIX4K_C8000 0x269\r
114#define EFI_IA32_MTRR_FIX4K_D0000 0x26A\r
115#define EFI_IA32_MTRR_FIX4K_D8000 0x26B\r
116#define EFI_IA32_MTRR_FIX4K_E0000 0x26C\r
117#define EFI_IA32_MTRR_FIX4K_E8000 0x26D\r
118#define EFI_IA32_MTRR_FIX4K_F0000 0x26E\r
119#define EFI_IA32_MTRR_FIX4K_F8000 0x26F\r
120\r
121#define EFI_IA32_MCG_CAP 0x179\r
122#define EFI_IA32_MCG_CTL 0x17B\r
123#define EFI_IA32_MC0_CTL 0x400\r
124#define EFI_IA32_MC0_STATUS 0x401\r
125\r
126#define EFI_IA32_PERF_STATUS 0x198\r
127#define EFI_IA32_PERF_CTL 0x199\r
128\r
129#define EFI_CACHE_UNCACHEABLE 0\r
130#define EFI_CACHE_WRITECOMBINING 1\r
131#define EFI_CACHE_WRITETHROUGH 4\r
132#define EFI_CACHE_WRITEPROTECTED 5\r
133#define EFI_CACHE_WRITEBACK 6\r
134\r
135//\r
136// Combine f(FamilyId), m(Model), s(SteppingId) to a single 32 bit number\r
137//\r
138#define EfiMakeCpuVersion(f, m, s) \\r
139 (((UINT32) (f) << 16) | ((UINT32) (m) << 8) | ((UINT32) (s)))\r
140\r
141VOID\r
142IA32API\r
143EfiHalt (\r
144 VOID\r
145 )\r
146;\r
147\r
148/*++ \r
149Routine Description: \r
150 Halt the Cpu \r
151Arguments: \r
152 None \r
153Returns: \r
154 None \r
155--*/\r
156VOID\r
157IA32API\r
158EfiWbinvd (\r
159 VOID\r
160 )\r
161;\r
162\r
163/*++ \r
164Routine Description: \r
165 Write back and invalidate the Cpu cache\r
166Arguments: \r
167 None \r
168Returns: \r
169 None \r
170--*/\r
171VOID\r
172IA32API\r
173EfiInvd (\r
174 VOID\r
175 )\r
176;\r
177\r
178/*++ \r
179Routine Description: \r
180 Invalidate the Cpu cache\r
181Arguments: \r
182 None \r
183Returns: \r
184 None \r
185--*/\r
186VOID\r
187IA32API\r
188EfiCpuid (\r
189 IN UINT32 RegisterInEax,\r
190 OUT EFI_CPUID_REGISTER *Regs\r
191 )\r
192;\r
193\r
194/*++ \r
195Routine Description: \r
196 Get the Cpu info by excute the CPUID instruction\r
197Arguments: \r
198 RegisterInEax: -The input value to put into register EAX\r
199 Regs: -The Output value \r
200Returns: \r
201 None \r
202--*/\r
203\r
204VOID\r
205IA32API\r
206EfiCpuidExt (\r
207 IN UINT32 RegisterInEax,\r
208 IN UINT32 CacheLevel,\r
209 OUT EFI_CPUID_REGISTER *Regs\r
210 )\r
211/*++ \r
212Routine Description: \r
213 When RegisterInEax != 4, the functionality is the same as EfiCpuid.\r
214 When RegisterInEax == 4, the function return the deterministic cache\r
215 parameters by excuting the CPUID instruction\r
216Arguments: \r
217 RegisterInEax: - The input value to put into register EAX\r
218 CacheLevel: - The deterministic cache level\r
219 Regs: - The Output value \r
220Returns: \r
221 None \r
222--*/\r
223;\r
224\r
225UINT64\r
226IA32API\r
227EfiReadMsr (\r
228 IN UINT32 Index\r
229 )\r
230;\r
231\r
232/*++ \r
233Routine Description: \r
234 Read Cpu MSR\r
235Arguments: \r
236 Index: -The index value to select the register\r
237 \r
238Returns: \r
239 Return the read data \r
240--*/\r
241VOID\r
242IA32API\r
243EfiWriteMsr (\r
244 IN UINT32 Index,\r
245 IN UINT64 Value\r
246 )\r
247;\r
248\r
249/*++ \r
250Routine Description: \r
251 Write Cpu MSR\r
252Arguments: \r
253 Index: -The index value to select the register\r
254 Value: -The value to write to the selected register \r
255Returns: \r
256 None \r
257--*/\r
258UINT64\r
259IA32API\r
260EfiReadTsc (\r
261 VOID\r
262 )\r
263;\r
264\r
265/*++ \r
266Routine Description: \r
267 Read Time stamp\r
268Arguments: \r
269 None \r
270Returns: \r
271 Return the read data \r
272--*/\r
273VOID\r
274IA32API\r
275EfiDisableCache (\r
276 VOID\r
277 )\r
278;\r
279\r
280/*++ \r
281Routine Description: \r
282 Writing back and invalidate the cache,then diable it\r
283Arguments: \r
284 None \r
285Returns: \r
286 None \r
287--*/\r
288VOID\r
289IA32API\r
290EfiEnableCache (\r
291 VOID\r
292 )\r
293;\r
294\r
295/*++ \r
296Routine Description: \r
297 Invalidate the cache,then Enable it\r
298Arguments: \r
299 None \r
300Returns: \r
301 None \r
302--*/\r
303UINT32\r
304IA32API\r
305EfiGetEflags (\r
306 VOID\r
307 )\r
308;\r
309\r
310/*++ \r
311Routine Description: \r
312 Get Eflags\r
313Arguments: \r
314 None \r
315Returns: \r
316 Return the Eflags value \r
317--*/\r
318VOID\r
319IA32API\r
320EfiDisableInterrupts (\r
321 VOID\r
322 )\r
323;\r
324\r
325/*++ \r
326Routine Description: \r
327 Disable Interrupts\r
328Arguments: \r
329 None \r
330Returns: \r
331 None\r
332--*/\r
333VOID\r
334IA32API\r
335EfiEnableInterrupts (\r
336 VOID\r
337 )\r
338;\r
339\r
340/*++ \r
341Routine Description: \r
342 Enable Interrupts\r
343Arguments: \r
344 None \r
345Returns: \r
346 None \r
347--*/\r
348\r
349\r
350VOID\r
351IA32API\r
352EfiCpuVersion (\r
353 IN UINT16 *FamilyId, OPTIONAL\r
354 IN UINT8 *Model, OPTIONAL\r
355 IN UINT8 *SteppingId, OPTIONAL\r
356 IN UINT8 *Processor OPTIONAL\r
357 )\r
358/*++\r
359\r
360Routine Description:\r
361 Extract CPU detail version infomation\r
362\r
363Arguments:\r
364 FamilyId - FamilyId, including ExtendedFamilyId\r
365 Model - Model, including ExtendedModel\r
366 SteppingId - SteppingId\r
367 Processor - Processor\r
368\r
369--*/\r
370;\r
371\r
372#endif\r
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