[mirror_edk2.git] / EdkCompatibilityPkg / Foundation / Efi / Protocol / PciIo / PciIo.h

/*++\r
\r
Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials                          \r
are licensed and made available under the terms and conditions of the BSD License         \r
which accompanies this distribution.  The full text of the license may be found at        \r
http://opensource.org/licenses/bsd-license.php                                            \r
                                                                                          \r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
\r
Module Name:\r
\r
    PciIo.h\r
    \r
Abstract:\r
\r
    EFI PCI I/O Protocol\r
\r
Revision History\r
\r
--*/\r
\r
#ifndef _EFI_PCI_IO_H\r
#define _EFI_PCI_IO_H\r
\r
//\r
// Global ID for the PCI I/O Protocol\r
//\r
#define EFI_PCI_IO_PROTOCOL_GUID \\r
  { \\r
    0x4cf5b200, 0x68b8, 0x4ca5, {0x9e, 0xec, 0xb2, 0x3e, 0x3f, 0x50, 0x2, 0x9a} \\r
  }\r
\r
EFI_FORWARD_DECLARATION (EFI_PCI_IO_PROTOCOL);\r
\r
//\r
// Prototypes for the PCI I/O Protocol\r
//\r
typedef enum {\r
  EfiPciIoWidthUint8      = 0,\r
  EfiPciIoWidthUint16,\r
  EfiPciIoWidthUint32,\r
  EfiPciIoWidthUint64,\r
  EfiPciIoWidthFifoUint8,\r
  EfiPciIoWidthFifoUint16,\r
  EfiPciIoWidthFifoUint32,\r
  EfiPciIoWidthFifoUint64,\r
  EfiPciIoWidthFillUint8,\r
  EfiPciIoWidthFillUint16,\r
  EfiPciIoWidthFillUint32,\r
  EfiPciIoWidthFillUint64,\r
  EfiPciIoWidthMaximum\r
} EFI_PCI_IO_PROTOCOL_WIDTH;\r
\r
//\r
// Complete PCI address generater\r
//\r
#define EFI_PCI_IO_PASS_THROUGH_BAR               0xff    // Special BAR that passes a memory or I/O cycle through unchanged\r
#define EFI_PCI_IO_ATTRIBUTE_MASK                 0x077f  // All the following I/O and Memory cycles\r
#define EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO   0x0001  // I/O cycles 0x0000-0x00FF (10 bit decode)\r
#define EFI_PCI_IO_ATTRIBUTE_ISA_IO               0x0002  // I/O cycles 0x0000-0x03FF (10 bit decode)\r
#define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO       0x0004  // I/O cycles 0x3C6, 0x3C8, 0x3C9 (10 bit decode)\r
#define EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY           0x0008  // MEM cycles 0xA0000-0xBFFFF (24 bit decode)\r
#define EFI_PCI_IO_ATTRIBUTE_VGA_IO               0x0010  // I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (10 bit decode)\r
#define EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO       0x0020  // I/O cycles 0x1F0-0x1F7, 0x3F6, 0x3F7 (10 bit decode)\r
#define EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO     0x0040  // I/O cycles 0x170-0x177, 0x376, 0x377 (10 bit decode)\r
#define EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE 0x0080  // Map a memory range so write are combined\r
#define EFI_PCI_IO_ATTRIBUTE_IO                   0x0100  // Enable the I/O decode bit in the PCI Config Header\r
#define EFI_PCI_IO_ATTRIBUTE_MEMORY               0x0200  // Enable the Memory decode bit in the PCI Config Header\r
#define EFI_PCI_IO_ATTRIBUTE_BUS_MASTER           0x0400  // Enable the DMA bit in the PCI Config Header\r
#define EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED        0x0800  // Map a memory range so all r/w accesses are cached\r
#define EFI_PCI_IO_ATTRIBUTE_MEMORY_DISABLE       0x1000  // Disable a memory range\r
#define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE      0x2000  // Clear for an add-in PCI Device\r
#define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM         0x4000  // Clear for a physical PCI Option ROM accessed through ROM BAR\r
#define EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE   0x8000  // Clear for PCI controllers that can not genrate a DAC\r
//\r
// The following definition is added in EFI1.1 spec update and UEFI2.0 spec.\r
//\r
#define EFI_PCI_IO_ATTRIBUTE_ISA_IO_16            0x10000 // I/O cycles 0x0100-0x03FF (16 bit decode)\r
#define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16    0x20000 // I/O cycles 0x3C6, 0x3C8, 0x3C9 (16 bit decode)\r
#define EFI_PCI_IO_ATTRIBUTE_VGA_IO_16            0x40000 // I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (16 bit decode)\r
\r
#define EFI_PCI_DEVICE_ENABLE                     (EFI_PCI_IO_ATTRIBUTE_IO | EFI_PCI_IO_ATTRIBUTE_MEMORY | EFI_PCI_IO_ATTRIBUTE_BUS_MASTER)\r
#define EFI_VGA_DEVICE_ENABLE                     (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY | EFI_PCI_IO_ATTRIBUTE_VGA_IO | EFI_PCI_IO_ATTRIBUTE_IO)\r
\r
//\r
// *******************************************************\r
// EFI_PCI_IO_PROTOCOL_OPERATION\r
// *******************************************************\r
//\r
typedef enum {\r
  EfiPciIoOperationBusMasterRead,\r
  EfiPciIoOperationBusMasterWrite,\r
  EfiPciIoOperationBusMasterCommonBuffer,\r
  EfiPciIoOperationMaximum\r
} EFI_PCI_IO_PROTOCOL_OPERATION;\r
\r
//\r
// *******************************************************\r
// EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION\r
// *******************************************************\r
//\r
typedef enum {\r
  EfiPciIoAttributeOperationGet,\r
  EfiPciIoAttributeOperationSet,\r
  EfiPciIoAttributeOperationEnable,\r
  EfiPciIoAttributeOperationDisable,\r
  EfiPciIoAttributeOperationSupported,\r
  EfiPciIoAttributeOperationMaximum\r
} EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION;\r
\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_IO_PROTOCOL_POLL_IO_MEM) (\r
  IN EFI_PCI_IO_PROTOCOL           * This,\r
  IN  EFI_PCI_IO_PROTOCOL_WIDTH    Width,\r
  IN  UINT8                        BarIndex,\r
  IN  UINT64                       Offset,\r
  IN  UINT64                       Mask,\r
  IN  UINT64                       Value,\r
  IN  UINT64                       Delay,\r
  OUT UINT64                       *Result\r
  );\r
\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_IO_PROTOCOL_IO_MEM) (\r
  IN EFI_PCI_IO_PROTOCOL              * This,\r
  IN     EFI_PCI_IO_PROTOCOL_WIDTH    Width,\r
  IN     UINT8                        BarIndex,\r
  IN     UINT64                       Offset,\r
  IN     UINTN                        Count,\r
  IN OUT VOID                         *Buffer\r
  );\r
\r
typedef struct {\r
  EFI_PCI_IO_PROTOCOL_IO_MEM  Read;\r
  EFI_PCI_IO_PROTOCOL_IO_MEM  Write;\r
} EFI_PCI_IO_PROTOCOL_ACCESS;\r
\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_IO_PROTOCOL_CONFIG) (\r
  IN EFI_PCI_IO_PROTOCOL              * This,\r
  IN     EFI_PCI_IO_PROTOCOL_WIDTH    Width,\r
  IN     UINT32                       Offset,\r
  IN     UINTN                        Count,\r
  IN OUT VOID                         *Buffer\r
  );\r
\r
typedef struct {\r
  EFI_PCI_IO_PROTOCOL_CONFIG  Read;\r
  EFI_PCI_IO_PROTOCOL_CONFIG  Write;\r
} EFI_PCI_IO_PROTOCOL_CONFIG_ACCESS;\r
\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_IO_PROTOCOL_COPY_MEM) (\r
  IN EFI_PCI_IO_PROTOCOL              * This,\r
  IN     EFI_PCI_IO_PROTOCOL_WIDTH    Width,\r
  IN     UINT8                        DestBarIndex,\r
  IN     UINT64                       DestOffset,\r
  IN     UINT8                        SrcBarIndex,\r
  IN     UINT64                       SrcOffset,\r
  IN     UINTN                        Count\r
  );\r
\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_IO_PROTOCOL_MAP) (\r
  IN EFI_PCI_IO_PROTOCOL                * This,\r
  IN     EFI_PCI_IO_PROTOCOL_OPERATION  Operation,\r
  IN     VOID                           *HostAddress,\r
  IN OUT UINTN                          *NumberOfBytes,\r
  OUT    EFI_PHYSICAL_ADDRESS           * DeviceAddress,\r
  OUT    VOID                           **Mapping\r
  );\r
\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_IO_PROTOCOL_UNMAP) (\r
  IN EFI_PCI_IO_PROTOCOL           * This,\r
  IN  VOID                         *Mapping\r
  );\r
\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_IO_PROTOCOL_ALLOCATE_BUFFER) (\r
  IN EFI_PCI_IO_PROTOCOL           * This,\r
  IN  EFI_ALLOCATE_TYPE            Type,\r
  IN  EFI_MEMORY_TYPE              MemoryType,\r
  IN  UINTN                        Pages,\r
  OUT VOID                         **HostAddress,\r
  IN  UINT64                       Attributes\r
  );\r
\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_IO_PROTOCOL_FREE_BUFFER) (\r
  IN EFI_PCI_IO_PROTOCOL           * This,\r
  IN  UINTN                        Pages,\r
  IN  VOID                         *HostAddress\r
  );\r
\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_IO_PROTOCOL_FLUSH) (\r
  IN EFI_PCI_IO_PROTOCOL  * This\r
  );\r
\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_IO_PROTOCOL_GET_LOCATION) (\r
  IN EFI_PCI_IO_PROTOCOL          * This,\r
  OUT UINTN                       *SegmentNumber,\r
  OUT UINTN                       *BusNumber,\r
  OUT UINTN                       *DeviceNumber,\r
  OUT UINTN                       *FunctionNumber\r
  );\r
\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_IO_PROTOCOL_ATTRIBUTES) (\r
  IN EFI_PCI_IO_PROTOCOL                       * This,\r
  IN  EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION  Operation,\r
  IN  UINT64                                   Attributes,\r
  OUT UINT64                                   *Result OPTIONAL\r
  );\r
\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_IO_PROTOCOL_GET_BAR_ATTRIBUTES) (\r
  IN EFI_PCI_IO_PROTOCOL             * This,\r
  IN  UINT8                          BarIndex,\r
  OUT UINT64                         *Supports, OPTIONAL\r
  OUT VOID                           **Resources OPTIONAL\r
  );\r
\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_IO_PROTOCOL_SET_BAR_ATTRIBUTES) (\r
  IN EFI_PCI_IO_PROTOCOL              * This,\r
  IN     UINT64                       Attributes,\r
  IN     UINT8                        BarIndex,\r
  IN OUT UINT64                       *Offset,\r
  IN OUT UINT64                       *Length\r
  );\r
\r
//\r
// Interface structure for the PCI I/O Protocol\r
//\r
struct _EFI_PCI_IO_PROTOCOL {\r
  EFI_PCI_IO_PROTOCOL_POLL_IO_MEM         PollMem;\r
  EFI_PCI_IO_PROTOCOL_POLL_IO_MEM         PollIo;\r
  EFI_PCI_IO_PROTOCOL_ACCESS              Mem;\r
  EFI_PCI_IO_PROTOCOL_ACCESS              Io;\r
  EFI_PCI_IO_PROTOCOL_CONFIG_ACCESS       Pci;\r
  EFI_PCI_IO_PROTOCOL_COPY_MEM            CopyMem;\r
  EFI_PCI_IO_PROTOCOL_MAP                 Map;\r
  EFI_PCI_IO_PROTOCOL_UNMAP               Unmap;\r
  EFI_PCI_IO_PROTOCOL_ALLOCATE_BUFFER     AllocateBuffer;\r
  EFI_PCI_IO_PROTOCOL_FREE_BUFFER         FreeBuffer;\r
  EFI_PCI_IO_PROTOCOL_FLUSH               Flush;\r
  EFI_PCI_IO_PROTOCOL_GET_LOCATION        GetLocation;\r
  EFI_PCI_IO_PROTOCOL_ATTRIBUTES          Attributes;\r
  EFI_PCI_IO_PROTOCOL_GET_BAR_ATTRIBUTES  GetBarAttributes;\r
  EFI_PCI_IO_PROTOCOL_SET_BAR_ATTRIBUTES  SetBarAttributes;\r
  UINT64                                  RomSize;\r
  VOID                                    *RomImage;\r
};\r
\r
extern EFI_GUID gEfiPciIoProtocolGuid;\r
\r
#endif\r
Commit	Line	Data
3eb9473e	1	/*++\r
3eb9473e	2	\r
f57387d5 HT	3	Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>\r
f57387d5 HT	4	This program and the accompanying materials \r
3eb9473e	5	are licensed and made available under the terms and conditions of the BSD License \r
	6	which accompanies this distribution. The full text of the license may be found at \r
	7	http://opensource.org/licenses/bsd-license.php \r
	8	\r
	9	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
	10	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
	11	\r
	12	Module Name:\r
	13	\r
	14	PciIo.h\r
	15	\r
	16	Abstract:\r
	17	\r
	18	EFI PCI I/O Protocol\r
	19	\r
	20	Revision History\r
	21	\r
	22	--*/\r
	23	\r
	24	#ifndef _EFI_PCI_IO_H\r
	25	#define _EFI_PCI_IO_H\r
	26	\r
	27	//\r
	28	// Global ID for the PCI I/O Protocol\r
	29	//\r
	30	#define EFI_PCI_IO_PROTOCOL_GUID \\r
	31	{ \\r
7ccf38a3	32	0x4cf5b200, 0x68b8, 0x4ca5, {0x9e, 0xec, 0xb2, 0x3e, 0x3f, 0x50, 0x2, 0x9a} \\r
3eb9473e	33	}\r
	34	\r
	35	EFI_FORWARD_DECLARATION (EFI_PCI_IO_PROTOCOL);\r
	36	\r
	37	//\r
	38	// Prototypes for the PCI I/O Protocol\r
	39	//\r
	40	typedef enum {\r
	41	EfiPciIoWidthUint8 = 0,\r
	42	EfiPciIoWidthUint16,\r
	43	EfiPciIoWidthUint32,\r
	44	EfiPciIoWidthUint64,\r
	45	EfiPciIoWidthFifoUint8,\r
	46	EfiPciIoWidthFifoUint16,\r
	47	EfiPciIoWidthFifoUint32,\r
	48	EfiPciIoWidthFifoUint64,\r
	49	EfiPciIoWidthFillUint8,\r
	50	EfiPciIoWidthFillUint16,\r
	51	EfiPciIoWidthFillUint32,\r
	52	EfiPciIoWidthFillUint64,\r
	53	EfiPciIoWidthMaximum\r
	54	} EFI_PCI_IO_PROTOCOL_WIDTH;\r
	55	\r
	56	//\r
	57	// Complete PCI address generater\r
	58	//\r
	59	#define EFI_PCI_IO_PASS_THROUGH_BAR 0xff // Special BAR that passes a memory or I/O cycle through unchanged\r
	60	#define EFI_PCI_IO_ATTRIBUTE_MASK 0x077f // All the following I/O and Memory cycles\r
	61	#define EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO 0x0001 // I/O cycles 0x0000-0x00FF (10 bit decode)\r
	62	#define EFI_PCI_IO_ATTRIBUTE_ISA_IO 0x0002 // I/O cycles 0x0000-0x03FF (10 bit decode)\r
	63	#define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO 0x0004 // I/O cycles 0x3C6, 0x3C8, 0x3C9 (10 bit decode)\r
	64	#define EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY 0x0008 // MEM cycles 0xA0000-0xBFFFF (24 bit decode)\r
	65	#define EFI_PCI_IO_ATTRIBUTE_VGA_IO 0x0010 // I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (10 bit decode)\r
	66	#define EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO 0x0020 // I/O cycles 0x1F0-0x1F7, 0x3F6, 0x3F7 (10 bit decode)\r
	67	#define EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO 0x0040 // I/O cycles 0x170-0x177, 0x376, 0x377 (10 bit decode)\r
	68	#define EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE 0x0080 // Map a memory range so write are combined\r
	69	#define EFI_PCI_IO_ATTRIBUTE_IO 0x0100 // Enable the I/O decode bit in the PCI Config Header\r
	70	#define EFI_PCI_IO_ATTRIBUTE_MEMORY 0x0200 // Enable the Memory decode bit in the PCI Config Header\r
	71	#define EFI_PCI_IO_ATTRIBUTE_BUS_MASTER 0x0400 // Enable the DMA bit in the PCI Config Header\r
	72	#define EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED 0x0800 // Map a memory range so all r/w accesses are cached\r
	73	#define EFI_PCI_IO_ATTRIBUTE_MEMORY_DISABLE 0x1000 // Disable a memory range\r
	74	#define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE 0x2000 // Clear for an add-in PCI Device\r
	75	#define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM 0x4000 // Clear for a physical PCI Option ROM accessed through ROM BAR\r
	76	#define EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE 0x8000 // Clear for PCI controllers that can not genrate a DAC\r
	77	//\r
	78	// The following definition is added in EFI1.1 spec update and UEFI2.0 spec.\r
	79	//\r
	80	#define EFI_PCI_IO_ATTRIBUTE_ISA_IO_16 0x10000 // I/O cycles 0x0100-0x03FF (16 bit decode)\r
	81	#define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16 0x20000 // I/O cycles 0x3C6, 0x3C8, 0x3C9 (16 bit decode)\r
	82	#define EFI_PCI_IO_ATTRIBUTE_VGA_IO_16 0x40000 // I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (16 bit decode)\r
	83	\r
	84	#define EFI_PCI_DEVICE_ENABLE (EFI_PCI_IO_ATTRIBUTE_IO \| EFI_PCI_IO_ATTRIBUTE_MEMORY \| EFI_PCI_IO_ATTRIBUTE_BUS_MASTER)\r
	85	#define EFI_VGA_DEVICE_ENABLE (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO \| EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY \| EFI_PCI_IO_ATTRIBUTE_VGA_IO \| EFI_PCI_IO_ATTRIBUTE_IO)\r
	86	\r
	87	//\r
	88	// *******************************************************\r
	89	// EFI_PCI_IO_PROTOCOL_OPERATION\r
	90	// *******************************************************\r
	91	//\r
	92	typedef enum {\r
	93	EfiPciIoOperationBusMasterRead,\r
	94	EfiPciIoOperationBusMasterWrite,\r
	95	EfiPciIoOperationBusMasterCommonBuffer,\r
	96	EfiPciIoOperationMaximum\r
97	} EFI_PCI_IO_PROTOCOL_OPERATION;\r
98	\r
99	//\r
100	// *******************************************************\r
101	// EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION\r
102	// *******************************************************\r
103	//\r
104	typedef enum {\r
105	EfiPciIoAttributeOperationGet,\r
106	EfiPciIoAttributeOperationSet,\r
107	EfiPciIoAttributeOperationEnable,\r
108	EfiPciIoAttributeOperationDisable,\r
109	EfiPciIoAttributeOperationSupported,\r
110	EfiPciIoAttributeOperationMaximum\r
111	} EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION;\r
112	\r
113	typedef\r
114	EFI_STATUS\r
115	(EFIAPI *EFI_PCI_IO_PROTOCOL_POLL_IO_MEM) (\r
116	IN EFI_PCI_IO_PROTOCOL * This,\r
117	IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
118	IN UINT8 BarIndex,\r
119	IN UINT64 Offset,\r
120	IN UINT64 Mask,\r
121	IN UINT64 Value,\r
122	IN UINT64 Delay,\r
123	OUT UINT64 *Result\r
124	);\r
125	\r
126	typedef\r
127	EFI_STATUS\r
128	(EFIAPI *EFI_PCI_IO_PROTOCOL_IO_MEM) (\r
129	IN EFI_PCI_IO_PROTOCOL * This,\r
130	IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
131	IN UINT8 BarIndex,\r
132	IN UINT64 Offset,\r
133	IN UINTN Count,\r
134	IN OUT VOID *Buffer\r
135	);\r
136	\r
137	typedef struct {\r
138	EFI_PCI_IO_PROTOCOL_IO_MEM Read;\r
139	EFI_PCI_IO_PROTOCOL_IO_MEM Write;\r
140	} EFI_PCI_IO_PROTOCOL_ACCESS;\r
141	\r
142	typedef\r
143	EFI_STATUS\r
144	(EFIAPI *EFI_PCI_IO_PROTOCOL_CONFIG) (\r
145	IN EFI_PCI_IO_PROTOCOL * This,\r
146	IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
147	IN UINT32 Offset,\r
148	IN UINTN Count,\r
149	IN OUT VOID *Buffer\r
150	);\r
151	\r
152	typedef struct {\r
153	EFI_PCI_IO_PROTOCOL_CONFIG Read;\r
154	EFI_PCI_IO_PROTOCOL_CONFIG Write;\r
155	} EFI_PCI_IO_PROTOCOL_CONFIG_ACCESS;\r
156	\r
157	typedef\r
158	EFI_STATUS\r
159	(EFIAPI *EFI_PCI_IO_PROTOCOL_COPY_MEM) (\r
160	IN EFI_PCI_IO_PROTOCOL * This,\r
161	IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
162	IN UINT8 DestBarIndex,\r
163	IN UINT64 DestOffset,\r
164	IN UINT8 SrcBarIndex,\r
165	IN UINT64 SrcOffset,\r
166	IN UINTN Count\r
167	);\r
168	\r
169	typedef\r
170	EFI_STATUS\r
171	(EFIAPI *EFI_PCI_IO_PROTOCOL_MAP) (\r
172	IN EFI_PCI_IO_PROTOCOL * This,\r
173	IN EFI_PCI_IO_PROTOCOL_OPERATION Operation,\r
174	IN VOID *HostAddress,\r
175	IN OUT UINTN *NumberOfBytes,\r
176	OUT EFI_PHYSICAL_ADDRESS * DeviceAddress,\r
177	OUT VOID **Mapping\r
178	);\r
179	\r
180	typedef\r
181	EFI_STATUS\r
182	(EFIAPI *EFI_PCI_IO_PROTOCOL_UNMAP) (\r
183	IN EFI_PCI_IO_PROTOCOL * This,\r
184	IN VOID *Mapping\r
185	);\r
186	\r
187	typedef\r
188	EFI_STATUS\r
189	(EFIAPI *EFI_PCI_IO_PROTOCOL_ALLOCATE_BUFFER) (\r
190	IN EFI_PCI_IO_PROTOCOL * This,\r
191	IN EFI_ALLOCATE_TYPE Type,\r
192	IN EFI_MEMORY_TYPE MemoryType,\r
193	IN UINTN Pages,\r
194	OUT VOID **HostAddress,\r
195	IN UINT64 Attributes\r
196	);\r
197	\r
198	typedef\r
199	EFI_STATUS\r
200	(EFIAPI *EFI_PCI_IO_PROTOCOL_FREE_BUFFER) (\r
201	IN EFI_PCI_IO_PROTOCOL * This,\r
202	IN UINTN Pages,\r
203	IN VOID *HostAddress\r
204	);\r
205	\r
206	typedef\r
207	EFI_STATUS\r
208	(EFIAPI *EFI_PCI_IO_PROTOCOL_FLUSH) (\r
209	IN EFI_PCI_IO_PROTOCOL * This\r
210	);\r
211	\r
212	typedef\r
213	EFI_STATUS\r
214	(EFIAPI *EFI_PCI_IO_PROTOCOL_GET_LOCATION) (\r
215	IN EFI_PCI_IO_PROTOCOL * This,\r
216	OUT UINTN *SegmentNumber,\r
217	OUT UINTN *BusNumber,\r
218	OUT UINTN *DeviceNumber,\r
219	OUT UINTN *FunctionNumber\r
220	);\r
221	\r
222	typedef\r
223	EFI_STATUS\r
224	(EFIAPI *EFI_PCI_IO_PROTOCOL_ATTRIBUTES) (\r
225	IN EFI_PCI_IO_PROTOCOL * This,\r
226	IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,\r
227	IN UINT64 Attributes,\r
228	OUT UINT64 *Result OPTIONAL\r
229	);\r
230	\r
231	typedef\r
232	EFI_STATUS\r
233	(EFIAPI *EFI_PCI_IO_PROTOCOL_GET_BAR_ATTRIBUTES) (\r
234	IN EFI_PCI_IO_PROTOCOL * This,\r
235	IN UINT8 BarIndex,\r
236	OUT UINT64 *Supports, OPTIONAL\r
237	OUT VOID **Resources OPTIONAL\r
238	);\r
239	\r
240	typedef\r
241	EFI_STATUS\r
242	(EFIAPI *EFI_PCI_IO_PROTOCOL_SET_BAR_ATTRIBUTES) (\r
243	IN EFI_PCI_IO_PROTOCOL * This,\r
244	IN UINT64 Attributes,\r
245	IN UINT8 BarIndex,\r
246	IN OUT UINT64 *Offset,\r
247	IN OUT UINT64 *Length\r
248	);\r
249	\r
250	//\r
251	// Interface structure for the PCI I/O Protocol\r
252	//\r
e5bce275	253	struct _EFI_PCI_IO_PROTOCOL {\r
3eb9473e	254	EFI_PCI_IO_PROTOCOL_POLL_IO_MEM PollMem;\r
	255	EFI_PCI_IO_PROTOCOL_POLL_IO_MEM PollIo;\r
	256	EFI_PCI_IO_PROTOCOL_ACCESS Mem;\r
	257	EFI_PCI_IO_PROTOCOL_ACCESS Io;\r
	258	EFI_PCI_IO_PROTOCOL_CONFIG_ACCESS Pci;\r
	259	EFI_PCI_IO_PROTOCOL_COPY_MEM CopyMem;\r
	260	EFI_PCI_IO_PROTOCOL_MAP Map;\r
	261	EFI_PCI_IO_PROTOCOL_UNMAP Unmap;\r
	262	EFI_PCI_IO_PROTOCOL_ALLOCATE_BUFFER AllocateBuffer;\r
	263	EFI_PCI_IO_PROTOCOL_FREE_BUFFER FreeBuffer;\r
	264	EFI_PCI_IO_PROTOCOL_FLUSH Flush;\r
	265	EFI_PCI_IO_PROTOCOL_GET_LOCATION GetLocation;\r
	266	EFI_PCI_IO_PROTOCOL_ATTRIBUTES Attributes;\r
	267	EFI_PCI_IO_PROTOCOL_GET_BAR_ATTRIBUTES GetBarAttributes;\r
	268	EFI_PCI_IO_PROTOCOL_SET_BAR_ATTRIBUTES SetBarAttributes;\r
	269	UINT64 RomSize;\r
	270	VOID *RomImage;\r
e5bce275	271	};\r
3eb9473e	272	\r
	273	extern EFI_GUID gEfiPciIoProtocolGuid;\r
	274	\r
	275	#endif\r