| 3eb9473e |
1 | /*++\r |
| 2 | \r |
| 3 | Copyright (c) 2004 - 2006, Intel Corporation \r |
| 4 | All rights reserved. This program and the accompanying materials \r |
| 5 | are licensed and made available under the terms and conditions of the BSD License \r |
| 6 | which accompanies this distribution. The full text of the license may be found at \r |
| 7 | http://opensource.org/licenses/bsd-license.php \r |
| 8 | \r |
| 9 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r |
| 10 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r |
| 11 | \r |
| 12 | Module name:\r |
| 13 | \r |
| 14 | EfiPxe.h\r |
| 15 | \r |
| 16 | 32/64-bit PXE specification:\r |
| 17 | \r |
| 18 | alpha-4, 99-Dec-17\r |
| 19 | \r |
| 20 | Abstract:\r |
| 21 | \r |
| 22 | This header file contains all of the PXE type definitions,\r |
| 23 | structure prototypes, global variables and constants that\r |
| 24 | are needed for porting PXE to EFI.\r |
| 25 | --*/\r |
| 26 | \r |
| 27 | #ifndef _EFIPXE_H\r |
| 28 | #define _EFIPXE_H\r |
| 29 | \r |
| 30 | #pragma pack(1)\r |
| 31 | \r |
| 32 | #define PXE_INTEL_ORDER 1 // Intel order\r |
| 33 | // #define PXE_NETWORK_ORDER 1 // network order\r |
| 34 | //\r |
| 35 | #define PXE_UINT64_SUPPORT 1 // UINT64 supported\r |
| 36 | // #define PXE_NO_UINT64_SUPPORT 1 // UINT64 not supported\r |
| 37 | //\r |
| 38 | #define PXE_BUSTYPE(a, b, c, d) \\r |
| 39 | ( \\r |
| 40 | (((UINT32) (d) & 0xFF) << 24) | (((UINT32) (c) & 0xFF) << 16) | (((UINT32) (b) & 0xFF) << 8) | \\r |
| 41 | ((UINT32) (a) & 0xFF) \\r |
| 42 | )\r |
| 43 | \r |
| 44 | //\r |
| 45 | // UNDI ROM ID and devive ID signature\r |
| 46 | //\r |
| 47 | #define PXE_BUSTYPE_PXE PXE_BUSTYPE ('!', 'P', 'X', 'E')\r |
| 48 | \r |
| 49 | //\r |
| 50 | // BUS ROM ID signatures\r |
| 51 | //\r |
| 52 | #define PXE_BUSTYPE_PCI PXE_BUSTYPE ('P', 'C', 'I', 'R')\r |
| 53 | #define PXE_BUSTYPE_PC_CARD PXE_BUSTYPE ('P', 'C', 'C', 'R')\r |
| 54 | #define PXE_BUSTYPE_USB PXE_BUSTYPE ('U', 'S', 'B', 'R')\r |
| 55 | #define PXE_BUSTYPE_1394 PXE_BUSTYPE ('1', '3', '9', '4')\r |
| 56 | \r |
| 57 | #define PXE_SWAP_UINT16(n) ((((UINT16) (n) & 0x00FF) << 8) | (((UINT16) (n) & 0xFF00) >> 8))\r |
| 58 | \r |
| 59 | #define PXE_SWAP_UINT32(n) \\r |
| 60 | ((((UINT32)(n) & 0x000000FF) << 24) | \\r |
| 61 | (((UINT32)(n) & 0x0000FF00) << 8) | \\r |
| 62 | (((UINT32)(n) & 0x00FF0000) >> 8) | \\r |
| 63 | (((UINT32)(n) & 0xFF000000) >> 24))\r |
| 64 | \r |
| 65 | #if PXE_UINT64_SUPPORT != 0\r |
| 66 | #define PXE_SWAP_UINT64(n) \\r |
| 67 | ((((UINT64)(n) & 0x00000000000000FF) << 56) | \\r |
| 68 | (((UINT64)(n) & 0x000000000000FF00) << 40) | \\r |
| 69 | (((UINT64)(n) & 0x0000000000FF0000) << 24) | \\r |
| 70 | (((UINT64)(n) & 0x00000000FF000000) << 8) | \\r |
| 71 | (((UINT64)(n) & 0x000000FF00000000) >> 8) | \\r |
| 72 | (((UINT64)(n) & 0x0000FF0000000000) >> 24) | \\r |
| 73 | (((UINT64)(n) & 0x00FF000000000000) >> 40) | \\r |
| 74 | (((UINT64)(n) & 0xFF00000000000000) >> 56))\r |
| 75 | #endif // PXE_UINT64_SUPPORT\r |
| 76 | #if PXE_NO_UINT64_SUPPORT != 0\r |
| 77 | #define PXE_SWAP_UINT64(n) { \\r |
| 78 | UINT32 tmp; \\r |
| 79 | tmp = (PXE_UINT64) (n)[1]; \\r |
| 80 | (UINT64) (n)[1] = PXE_SWAP_UINT32 ((UINT64) (n)[0]); \\r |
| 81 | (UINT64) (n)[0] = tmp; \\r |
| 82 | }\r |
| 83 | #endif // PXE_NO_UINT64_SUPPORT\r |
| 84 | #define PXE_CPBSIZE_NOT_USED 0 // zero\r |
| 85 | #define PXE_DBSIZE_NOT_USED 0 // zero\r |
| 86 | #define PXE_CPBADDR_NOT_USED (PXE_UINT64) 0 // zero\r |
| 87 | #define PXE_DBADDR_NOT_USED (PXE_UINT64) 0 // zero\r |
| 88 | #define PXE_CONST const\r |
| 89 | \r |
| 90 | #define PXE_VOLATILE volatile\r |
| 91 | \r |
| 92 | #if PXE_UINT64_SUPPORT != 0\r |
| 93 | //\r |
| 94 | // typedef unsigned long PXE_UINT64;\r |
| 95 | //\r |
| 96 | typedef UINT64 PXE_UINT64;\r |
| 97 | #endif // PXE_UINT64_SUPPORT\r |
| 98 | #if PXE_NO_UINT64_SUPPORT != 0\r |
| 99 | typedef PXE_UINT32 PXE_UINT64[2];\r |
| 100 | #endif // PXE_NO_UINT64_SUPPORT\r |
| 101 | #define PXE_FALSE 0 // zero\r |
| 102 | #define PXE_TRUE (!PXE_FALSE)\r |
| 103 | \r |
| 104 | typedef UINT16 PXE_OPCODE;\r |
| 105 | \r |
| 106 | //\r |
| 107 | // Return UNDI operational state.\r |
| 108 | //\r |
| 109 | #define PXE_OPCODE_GET_STATE 0x0000\r |
| 110 | \r |
| 111 | //\r |
| 112 | // Change UNDI operational state from Stopped to Started.\r |
| 113 | //\r |
| 114 | #define PXE_OPCODE_START 0x0001\r |
| 115 | \r |
| 116 | //\r |
| 117 | // Change UNDI operational state from Started to Stopped.\r |
| 118 | //\r |
| 119 | #define PXE_OPCODE_STOP 0x0002\r |
| 120 | \r |
| 121 | //\r |
| 122 | // Get UNDI initialization information.\r |
| 123 | //\r |
| 124 | #define PXE_OPCODE_GET_INIT_INFO 0x0003\r |
| 125 | \r |
| 126 | //\r |
| 127 | // Get NIC configuration information.\r |
| 128 | //\r |
| 129 | #define PXE_OPCODE_GET_CONFIG_INFO 0x0004\r |
| 130 | \r |
| 131 | //\r |
| 132 | // Changed UNDI operational state from Started to Initialized.\r |
| 133 | //\r |
| 134 | #define PXE_OPCODE_INITIALIZE 0x0005\r |
| 135 | \r |
| 136 | //\r |
| 137 | // Re-initialize the NIC H/W.\r |
| 138 | //\r |
| 139 | #define PXE_OPCODE_RESET 0x0006\r |
| 140 | \r |
| 141 | //\r |
| 142 | // Change the UNDI operational state from Initialized to Started.\r |
| 143 | //\r |
| 144 | #define PXE_OPCODE_SHUTDOWN 0x0007\r |
| 145 | \r |
| 146 | //\r |
| 147 | // Read & change state of external interrupt enables.\r |
| 148 | //\r |
| 149 | #define PXE_OPCODE_INTERRUPT_ENABLES 0x0008\r |
| 150 | \r |
| 151 | //\r |
| 152 | // Read & change state of packet receive filters.\r |
| 153 | //\r |
| 154 | #define PXE_OPCODE_RECEIVE_FILTERS 0x0009\r |
| 155 | \r |
| 156 | //\r |
| 157 | // Read & change station MAC address.\r |
| 158 | //\r |
| 159 | #define PXE_OPCODE_STATION_ADDRESS 0x000A\r |
| 160 | \r |
| 161 | //\r |
| 162 | // Read traffic statistics.\r |
| 163 | //\r |
| 164 | #define PXE_OPCODE_STATISTICS 0x000B\r |
| 165 | \r |
| 166 | //\r |
| 167 | // Convert multicast IP address to multicast MAC address.\r |
| 168 | //\r |
| 169 | #define PXE_OPCODE_MCAST_IP_TO_MAC 0x000C\r |
| 170 | \r |
| 171 | //\r |
| 172 | // Read or change non-volatile storage on the NIC.\r |
| 173 | //\r |
| 174 | #define PXE_OPCODE_NVDATA 0x000D\r |
| 175 | \r |
| 176 | //\r |
| 177 | // Get & clear interrupt status.\r |
| 178 | //\r |
| 179 | #define PXE_OPCODE_GET_STATUS 0x000E\r |
| 180 | \r |
| 181 | //\r |
| 182 | // Fill media header in packet for transmit.\r |
| 183 | //\r |
| 184 | #define PXE_OPCODE_FILL_HEADER 0x000F\r |
| 185 | \r |
| 186 | //\r |
| 187 | // Transmit packet(s).\r |
| 188 | //\r |
| 189 | #define PXE_OPCODE_TRANSMIT 0x0010\r |
| 190 | \r |
| 191 | //\r |
| 192 | // Receive packet.\r |
| 193 | //\r |
| 194 | #define PXE_OPCODE_RECEIVE 0x0011\r |
| 195 | \r |
| 196 | //\r |
| 197 | // last valid opcode:\r |
| 198 | //\r |
| 199 | #define PXE_OPCODE_VALID_MAX 0x0011\r |
| 200 | \r |
| 201 | //\r |
| 202 | // Last valid PXE UNDI OpCode number.\r |
| 203 | //\r |
| 204 | #define PXE_OPCODE_LAST_VALID 0x0011\r |
| 205 | \r |
| 206 | typedef UINT16 PXE_OPFLAGS;\r |
| 207 | \r |
| 208 | #define PXE_OPFLAGS_NOT_USED 0x0000\r |
| 209 | \r |
| 210 | //\r |
| 211 | // //////////////////////////////////////\r |
| 212 | // UNDI Get State\r |
| 213 | //\r |
| 214 | // No OpFlags\r |
| 215 | \r |
| 216 | ////////////////////////////////////////\r |
| 217 | // UNDI Start\r |
| 218 | //\r |
| 219 | // No OpFlags\r |
| 220 | \r |
| 221 | ////////////////////////////////////////\r |
| 222 | // UNDI Stop\r |
| 223 | //\r |
| 224 | // No OpFlags\r |
| 225 | \r |
| 226 | ////////////////////////////////////////\r |
| 227 | // UNDI Get Init Info\r |
| 228 | //\r |
| 229 | // No Opflags\r |
| 230 | \r |
| 231 | ////////////////////////////////////////\r |
| 232 | // UNDI Get Config Info\r |
| 233 | //\r |
| 234 | // No Opflags\r |
| 235 | \r |
| 236 | ////////////////////////////////////////\r |
| 237 | // UNDI Initialize\r |
| 238 | //\r |
| 239 | #define PXE_OPFLAGS_INITIALIZE_CABLE_DETECT_MASK 0x0001\r |
| 240 | #define PXE_OPFLAGS_INITIALIZE_DETECT_CABLE 0x0000\r |
| 241 | #define PXE_OPFLAGS_INITIALIZE_DO_NOT_DETECT_CABLE 0x0001\r |
| 242 | \r |
| 243 | //\r |
| 244 | // //////////////////////////////////////\r |
| 245 | // UNDI Reset\r |
| 246 | //\r |
| 247 | #define PXE_OPFLAGS_RESET_DISABLE_INTERRUPTS 0x0001\r |
| 248 | #define PXE_OPFLAGS_RESET_DISABLE_FILTERS 0x0002\r |
| 249 | \r |
| 250 | //\r |
| 251 | // //////////////////////////////////////\r |
| 252 | // UNDI Shutdown\r |
| 253 | //\r |
| 254 | // No OpFlags\r |
| 255 | \r |
| 256 | ////////////////////////////////////////\r |
| 257 | // UNDI Interrupt Enables\r |
| 258 | //\r |
| 259 | //\r |
| 260 | // Select whether to enable or disable external interrupt signals.\r |
| 261 | // Setting both enable and disable will return PXE_STATCODE_INVALID_OPFLAGS.\r |
| 262 | //\r |
| 263 | #define PXE_OPFLAGS_INTERRUPT_OPMASK 0xC000\r |
| 264 | #define PXE_OPFLAGS_INTERRUPT_ENABLE 0x8000\r |
| 265 | #define PXE_OPFLAGS_INTERRUPT_DISABLE 0x4000\r |
| 266 | #define PXE_OPFLAGS_INTERRUPT_READ 0x0000\r |
| 267 | \r |
| 268 | //\r |
| 269 | // Enable receive interrupts. An external interrupt will be generated\r |
| 270 | // after a complete non-error packet has been received.\r |
| 271 | //\r |
| 272 | #define PXE_OPFLAGS_INTERRUPT_RECEIVE 0x0001\r |
| 273 | \r |
| 274 | //\r |
| 275 | // Enable transmit interrupts. An external interrupt will be generated\r |
| 276 | // after a complete non-error packet has been transmitted.\r |
| 277 | //\r |
| 278 | #define PXE_OPFLAGS_INTERRUPT_TRANSMIT 0x0002\r |
| 279 | \r |
| 280 | //\r |
| 281 | // Enable command interrupts. An external interrupt will be generated\r |
| 282 | // when command execution stops.\r |
| 283 | //\r |
| 284 | #define PXE_OPFLAGS_INTERRUPT_COMMAND 0x0004\r |
| 285 | \r |
| 286 | //\r |
| 287 | // Generate software interrupt. Setting this bit generates an external\r |
| 288 | // interrupt, if it is supported by the hardware.\r |
| 289 | //\r |
| 290 | #define PXE_OPFLAGS_INTERRUPT_SOFTWARE 0x0008\r |
| 291 | \r |
| 292 | //\r |
| 293 | // //////////////////////////////////////\r |
| 294 | // UNDI Receive Filters\r |
| 295 | //\r |
| 296 | //\r |
| 297 | // Select whether to enable or disable receive filters.\r |
| 298 | // Setting both enable and disable will return PXE_STATCODE_INVALID_OPCODE.\r |
| 299 | //\r |
| 300 | #define PXE_OPFLAGS_RECEIVE_FILTER_OPMASK 0xC000\r |
| 301 | #define PXE_OPFLAGS_RECEIVE_FILTER_ENABLE 0x8000\r |
| 302 | #define PXE_OPFLAGS_RECEIVE_FILTER_DISABLE 0x4000\r |
| 303 | #define PXE_OPFLAGS_RECEIVE_FILTER_READ 0x0000\r |
| 304 | \r |
| 305 | //\r |
| 306 | // To reset the contents of the multicast MAC address filter list,\r |
| 307 | // set this OpFlag:\r |
| 308 | //\r |
| 309 | #define PXE_OPFLAGS_RECEIVE_FILTER_RESET_MCAST_LIST 0x2000\r |
| 310 | \r |
| 311 | //\r |
| 312 | // Enable unicast packet receiving. Packets sent to the current station\r |
| 313 | // MAC address will be received.\r |
| 314 | //\r |
| 315 | #define PXE_OPFLAGS_RECEIVE_FILTER_UNICAST 0x0001\r |
| 316 | \r |
| 317 | //\r |
| 318 | // Enable broadcast packet receiving. Packets sent to the broadcast\r |
| 319 | // MAC address will be received.\r |
| 320 | //\r |
| 321 | #define PXE_OPFLAGS_RECEIVE_FILTER_BROADCAST 0x0002\r |
| 322 | \r |
| 323 | //\r |
| 324 | // Enable filtered multicast packet receiving. Packets sent to any\r |
| 325 | // of the multicast MAC addresses in the multicast MAC address filter\r |
| 326 | // list will be received. If the filter list is empty, no multicast\r |
| 327 | //\r |
| 328 | #define PXE_OPFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST 0x0004\r |
| 329 | \r |
| 330 | //\r |
| 331 | // Enable promiscuous packet receiving. All packets will be received.\r |
| 332 | //\r |
| 333 | #define PXE_OPFLAGS_RECEIVE_FILTER_PROMISCUOUS 0x0008\r |
| 334 | \r |
| 335 | //\r |
| 336 | // Enable promiscuous multicast packet receiving. All multicast\r |
| 337 | // packets will be received.\r |
| 338 | //\r |
| 339 | #define PXE_OPFLAGS_RECEIVE_FILTER_ALL_MULTICAST 0x0010\r |
| 340 | \r |
| 341 | //\r |
| 342 | // //////////////////////////////////////\r |
| 343 | // UNDI Station Address\r |
| 344 | //\r |
| 345 | #define PXE_OPFLAGS_STATION_ADDRESS_READ 0x0000\r |
| 346 | #define PXE_OPFLAGS_STATION_ADDRESS_WRITE 0x0000\r |
| 347 | #define PXE_OPFLAGS_STATION_ADDRESS_RESET 0x0001\r |
| 348 | \r |
| 349 | //\r |
| 350 | // //////////////////////////////////////\r |
| 351 | // UNDI Statistics\r |
| 352 | //\r |
| 353 | #define PXE_OPFLAGS_STATISTICS_READ 0x0000\r |
| 354 | #define PXE_OPFLAGS_STATISTICS_RESET 0x0001\r |
| 355 | \r |
| 356 | //\r |
| 357 | // //////////////////////////////////////\r |
| 358 | // UNDI MCast IP to MAC\r |
| 359 | //\r |
| 360 | //\r |
| 361 | // Identify the type of IP address in the CPB.\r |
| 362 | //\r |
| 363 | #define PXE_OPFLAGS_MCAST_IP_TO_MAC_OPMASK 0x0003\r |
| 364 | #define PXE_OPFLAGS_MCAST_IPV4_TO_MAC 0x0000\r |
| 365 | #define PXE_OPFLAGS_MCAST_IPV6_TO_MAC 0x0001\r |
| 366 | \r |
| 367 | //\r |
| 368 | // //////////////////////////////////////\r |
| 369 | // UNDI NvData\r |
| 370 | //\r |
| 371 | //\r |
| 372 | // Select the type of non-volatile data operation.\r |
| 373 | //\r |
| 374 | #define PXE_OPFLAGS_NVDATA_OPMASK 0x0001\r |
| 375 | #define PXE_OPFLAGS_NVDATA_READ 0x0000\r |
| 376 | #define PXE_OPFLAGS_NVDATA_WRITE 0x0001\r |
| 377 | \r |
| 378 | //\r |
| 379 | // //////////////////////////////////////\r |
| 380 | // UNDI Get Status\r |
| 381 | //\r |
| 382 | //\r |
| 383 | // Return current interrupt status. This will also clear any interrupts\r |
| 384 | // that are currently set. This can be used in a polling routine. The\r |
| 385 | // interrupt flags are still set and cleared even when the interrupts\r |
| 386 | // are disabled.\r |
| 387 | //\r |
| 388 | #define PXE_OPFLAGS_GET_INTERRUPT_STATUS 0x0001\r |
| 389 | \r |
| 390 | //\r |
| 391 | // Return list of transmitted buffers for recycling. Transmit buffers\r |
| 392 | // must not be changed or unallocated until they have recycled. After\r |
| 393 | // issuing a transmit command, wait for a transmit complete interrupt.\r |
| 394 | // When a transmit complete interrupt is received, read the transmitted\r |
| 395 | // buffers. Do not plan on getting one buffer per interrupt. Some\r |
| 396 | // NICs and UNDIs may transmit multiple buffers per interrupt.\r |
| 397 | //\r |
| 398 | #define PXE_OPFLAGS_GET_TRANSMITTED_BUFFERS 0x0002\r |
| 399 | \r |
| 400 | //\r |
| 401 | // //////////////////////////////////////\r |
| 402 | // UNDI Fill Header\r |
| 403 | //\r |
| 404 | #define PXE_OPFLAGS_FILL_HEADER_OPMASK 0x0001\r |
| 405 | #define PXE_OPFLAGS_FILL_HEADER_FRAGMENTED 0x0001\r |
| 406 | #define PXE_OPFLAGS_FILL_HEADER_WHOLE 0x0000\r |
| 407 | \r |
| 408 | //\r |
| 409 | // //////////////////////////////////////\r |
| 410 | // UNDI Transmit\r |
| 411 | //\r |
| 412 | //\r |
| 413 | // S/W UNDI only. Return after the packet has been transmitted. A\r |
| 414 | // transmit complete interrupt will still be generated and the transmit\r |
| 415 | // buffer will have to be recycled.\r |
| 416 | //\r |
| 417 | #define PXE_OPFLAGS_SWUNDI_TRANSMIT_OPMASK 0x0001\r |
| 418 | #define PXE_OPFLAGS_TRANSMIT_BLOCK 0x0001\r |
| 419 | #define PXE_OPFLAGS_TRANSMIT_DONT_BLOCK 0x0000\r |
| 420 | \r |
| 421 | //\r |
| 422 | //\r |
| 423 | //\r |
| 424 | #define PXE_OPFLAGS_TRANSMIT_OPMASK 0x0002\r |
| 425 | #define PXE_OPFLAGS_TRANSMIT_FRAGMENTED 0x0002\r |
| 426 | #define PXE_OPFLAGS_TRANSMIT_WHOLE 0x0000\r |
| 427 | \r |
| 428 | //\r |
| 429 | // //////////////////////////////////////\r |
| 430 | // UNDI Receive\r |
| 431 | //\r |
| 432 | // No OpFlags\r |
| 433 | //\r |
| 434 | typedef UINT16 PXE_STATFLAGS;\r |
| 435 | \r |
| 436 | #define PXE_STATFLAGS_INITIALIZE 0x0000\r |
| 437 | \r |
| 438 | //\r |
| 439 | // //////////////////////////////////////\r |
| 440 | // Common StatFlags that can be returned by all commands.\r |
| 441 | //\r |
| 442 | //\r |
| 443 | // The COMMAND_COMPLETE and COMMAND_FAILED status flags must be\r |
| 444 | // implemented by all UNDIs. COMMAND_QUEUED is only needed by UNDIs\r |
| 445 | // that support command queuing.\r |
| 446 | //\r |
| 447 | #define PXE_STATFLAGS_STATUS_MASK 0xC000\r |
| 448 | #define PXE_STATFLAGS_COMMAND_COMPLETE 0xC000\r |
| 449 | #define PXE_STATFLAGS_COMMAND_FAILED 0x8000\r |
| 450 | #define PXE_STATFLAGS_COMMAND_QUEUED 0x4000\r |
| 451 | //\r |
| 452 | // #define PXE_STATFLAGS_INITIALIZE 0x0000\r |
| 453 | //\r |
| 454 | #define PXE_STATFLAGS_DB_WRITE_TRUNCATED 0x2000\r |
| 455 | \r |
| 456 | //\r |
| 457 | // //////////////////////////////////////\r |
| 458 | // UNDI Get State\r |
| 459 | //\r |
| 460 | #define PXE_STATFLAGS_GET_STATE_MASK 0x0003\r |
| 461 | #define PXE_STATFLAGS_GET_STATE_INITIALIZED 0x0002\r |
| 462 | #define PXE_STATFLAGS_GET_STATE_STARTED 0x0001\r |
| 463 | #define PXE_STATFLAGS_GET_STATE_STOPPED 0x0000\r |
| 464 | \r |
| 465 | //\r |
| 466 | // //////////////////////////////////////\r |
| 467 | // UNDI Start\r |
| 468 | //\r |
| 469 | // No additional StatFlags\r |
| 470 | \r |
| 471 | ////////////////////////////////////////\r |
| 472 | // UNDI Get Init Info\r |
| 473 | //\r |
| 474 | #define PXE_STATFLAGS_CABLE_DETECT_MASK 0x0001\r |
| 475 | #define PXE_STATFLAGS_CABLE_DETECT_NOT_SUPPORTED 0x0000\r |
| 476 | #define PXE_STATFLAGS_CABLE_DETECT_SUPPORTED 0x0001\r |
| 477 | \r |
| 478 | //\r |
| 479 | // //////////////////////////////////////\r |
| 480 | // UNDI Initialize\r |
| 481 | //\r |
| 482 | #define PXE_STATFLAGS_INITIALIZED_NO_MEDIA 0x0001\r |
| 483 | \r |
| 484 | //\r |
| 485 | // //////////////////////////////////////\r |
| 486 | // UNDI Reset\r |
| 487 | //\r |
| 488 | #define PXE_STATFLAGS_RESET_NO_MEDIA 0x0001\r |
| 489 | \r |
| 490 | //\r |
| 491 | // //////////////////////////////////////\r |
| 492 | // UNDI Shutdown\r |
| 493 | //\r |
| 494 | // No additional StatFlags\r |
| 495 | \r |
| 496 | ////////////////////////////////////////\r |
| 497 | // UNDI Interrupt Enables\r |
| 498 | //\r |
| 499 | //\r |
| 500 | // If set, receive interrupts are enabled.\r |
| 501 | //\r |
| 502 | #define PXE_STATFLAGS_INTERRUPT_RECEIVE 0x0001\r |
| 503 | \r |
| 504 | //\r |
| 505 | // If set, transmit interrupts are enabled.\r |
| 506 | //\r |
| 507 | #define PXE_STATFLAGS_INTERRUPT_TRANSMIT 0x0002\r |
| 508 | \r |
| 509 | //\r |
| 510 | // If set, command interrupts are enabled.\r |
| 511 | //\r |
| 512 | #define PXE_STATFLAGS_INTERRUPT_COMMAND 0x0004\r |
| 513 | \r |
| 514 | //\r |
| 515 | // //////////////////////////////////////\r |
| 516 | // UNDI Receive Filters\r |
| 517 | //\r |
| 518 | //\r |
| 519 | // If set, unicast packets will be received.\r |
| 520 | //\r |
| 521 | #define PXE_STATFLAGS_RECEIVE_FILTER_UNICAST 0x0001\r |
| 522 | \r |
| 523 | //\r |
| 524 | // If set, broadcast packets will be received.\r |
| 525 | //\r |
| 526 | #define PXE_STATFLAGS_RECEIVE_FILTER_BROADCAST 0x0002\r |
| 527 | \r |
| 528 | //\r |
| 529 | // If set, multicast packets that match up with the multicast address\r |
| 530 | // filter list will be received.\r |
| 531 | //\r |
| 532 | #define PXE_STATFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST 0x0004\r |
| 533 | \r |
| 534 | //\r |
| 535 | // If set, all packets will be received.\r |
| 536 | //\r |
| 537 | #define PXE_STATFLAGS_RECEIVE_FILTER_PROMISCUOUS 0x0008\r |
| 538 | \r |
| 539 | //\r |
| 540 | // If set, all multicast packets will be received.\r |
| 541 | //\r |
| 542 | #define PXE_STATFLAGS_RECEIVE_FILTER_ALL_MULTICAST 0x0010\r |
| 543 | \r |
| 544 | //\r |
| 545 | // //////////////////////////////////////\r |
| 546 | // UNDI Station Address\r |
| 547 | //\r |
| 548 | // No additional StatFlags\r |
| 549 | \r |
| 550 | ////////////////////////////////////////\r |
| 551 | // UNDI Statistics\r |
| 552 | //\r |
| 553 | // No additional StatFlags\r |
| 554 | \r |
| 555 | ////////////////////////////////////////\r |
| 556 | // UNDI MCast IP to MAC\r |
| 557 | //\r |
| 558 | // No additional StatFlags\r |
| 559 | \r |
| 560 | ////////////////////////////////////////\r |
| 561 | // UNDI NvData\r |
| 562 | //\r |
| 563 | // No additional StatFlags\r |
| 564 | \r |
| 565 | \r |
| 566 | ////////////////////////////////////////\r |
| 567 | // UNDI Get Status\r |
| 568 | //\r |
| 569 | //\r |
| 570 | // Use to determine if an interrupt has occurred.\r |
| 571 | //\r |
| 572 | #define PXE_STATFLAGS_GET_STATUS_INTERRUPT_MASK 0x000F\r |
| 573 | #define PXE_STATFLAGS_GET_STATUS_NO_INTERRUPTS 0x0000\r |
| 574 | \r |
| 575 | //\r |
| 576 | // If set, at least one receive interrupt occurred.\r |
| 577 | //\r |
| 578 | #define PXE_STATFLAGS_GET_STATUS_RECEIVE 0x0001\r |
| 579 | \r |
| 580 | //\r |
| 581 | // If set, at least one transmit interrupt occurred.\r |
| 582 | //\r |
| 583 | #define PXE_STATFLAGS_GET_STATUS_TRANSMIT 0x0002\r |
| 584 | \r |
| 585 | //\r |
| 586 | // If set, at least one command interrupt occurred.\r |
| 587 | //\r |
| 588 | #define PXE_STATFLAGS_GET_STATUS_COMMAND 0x0004\r |
| 589 | \r |
| 590 | //\r |
| 591 | // If set, at least one software interrupt occurred.\r |
| 592 | //\r |
| 593 | #define PXE_STATFLAGS_GET_STATUS_SOFTWARE 0x0008\r |
| 594 | \r |
| 595 | //\r |
| 596 | // This flag is set if the transmitted buffer queue is empty. This flag\r |
| 597 | // will be set if all transmitted buffer addresses get written into the DB.\r |
| 598 | //\r |
| 599 | #define PXE_STATFLAGS_GET_STATUS_TXBUF_QUEUE_EMPTY 0x0010\r |
| 600 | \r |
| 601 | //\r |
| 602 | // This flag is set if no transmitted buffer addresses were written\r |
| 603 | // into the DB. (This could be because DBsize was too small.)\r |
| 604 | //\r |
| 605 | #define PXE_STATFLAGS_GET_STATUS_NO_TXBUFS_WRITTEN 0x0020\r |
| 606 | \r |
| 607 | //\r |
| 608 | // //////////////////////////////////////\r |
| 609 | // UNDI Fill Header\r |
| 610 | //\r |
| 611 | // No additional StatFlags\r |
| 612 | \r |
| 613 | ////////////////////////////////////////\r |
| 614 | // UNDI Transmit\r |
| 615 | //\r |
| 616 | // No additional StatFlags.\r |
| 617 | \r |
| 618 | ////////////////////////////////////////\r |
| 619 | // UNDI Receive\r |
| 620 | //\r |
| 621 | // No additional StatFlags.\r |
| 622 | //\r |
| 623 | typedef UINT16 PXE_STATCODE;\r |
| 624 | \r |
| 625 | #define PXE_STATCODE_INITIALIZE 0x0000\r |
| 626 | \r |
| 627 | //\r |
| 628 | // //////////////////////////////////////\r |
| 629 | // Common StatCodes returned by all UNDI commands, UNDI protocol functions\r |
| 630 | // and BC protocol functions.\r |
| 631 | //\r |
| 632 | #define PXE_STATCODE_SUCCESS 0x0000\r |
| 633 | \r |
| 634 | #define PXE_STATCODE_INVALID_CDB 0x0001\r |
| 635 | #define PXE_STATCODE_INVALID_CPB 0x0002\r |
| 636 | #define PXE_STATCODE_BUSY 0x0003\r |
| 637 | #define PXE_STATCODE_QUEUE_FULL 0x0004\r |
| 638 | #define PXE_STATCODE_ALREADY_STARTED 0x0005\r |
| 639 | #define PXE_STATCODE_NOT_STARTED 0x0006\r |
| 640 | #define PXE_STATCODE_NOT_SHUTDOWN 0x0007\r |
| 641 | #define PXE_STATCODE_ALREADY_INITIALIZED 0x0008\r |
| 642 | #define PXE_STATCODE_NOT_INITIALIZED 0x0009\r |
| 643 | #define PXE_STATCODE_DEVICE_FAILURE 0x000A\r |
| 644 | #define PXE_STATCODE_NVDATA_FAILURE 0x000B\r |
| 645 | #define PXE_STATCODE_UNSUPPORTED 0x000C\r |
| 646 | #define PXE_STATCODE_BUFFER_FULL 0x000D\r |
| 647 | #define PXE_STATCODE_INVALID_PARAMETER 0x000E\r |
| 648 | #define PXE_STATCODE_INVALID_UNDI 0x000F\r |
| 649 | #define PXE_STATCODE_IPV4_NOT_SUPPORTED 0x0010\r |
| 650 | #define PXE_STATCODE_IPV6_NOT_SUPPORTED 0x0011\r |
| 651 | #define PXE_STATCODE_NOT_ENOUGH_MEMORY 0x0012\r |
| 652 | #define PXE_STATCODE_NO_DATA 0x0013\r |
| 653 | \r |
| 654 | typedef UINT16 PXE_IFNUM;\r |
| 655 | \r |
| 656 | //\r |
| 657 | // This interface number must be passed to the S/W UNDI Start command.\r |
| 658 | //\r |
| 659 | #define PXE_IFNUM_START 0x0000\r |
| 660 | \r |
| 661 | //\r |
| 662 | // This interface number is returned by the S/W UNDI Get State and\r |
| 663 | // Start commands if information in the CDB, CPB or DB is invalid.\r |
| 664 | //\r |
| 665 | #define PXE_IFNUM_INVALID 0x0000\r |
| 666 | \r |
| 667 | typedef UINT16 PXE_CONTROL;\r |
| 668 | \r |
| 669 | //\r |
| 670 | // Setting this flag directs the UNDI to queue this command for later\r |
| 671 | // execution if the UNDI is busy and it supports command queuing.\r |
| 672 | // If queuing is not supported, a PXE_STATCODE_INVALID_CONTROL error\r |
| 673 | // is returned. If the queue is full, a PXE_STATCODE_CDB_QUEUE_FULL\r |
| 674 | // error is returned.\r |
| 675 | //\r |
| 676 | #define PXE_CONTROL_QUEUE_IF_BUSY 0x0002\r |
| 677 | \r |
| 678 | //\r |
| 679 | // These two bit values are used to determine if there are more UNDI\r |
| 680 | // CDB structures following this one. If the link bit is set, there\r |
| 681 | // must be a CDB structure following this one. Execution will start\r |
| 682 | // on the next CDB structure as soon as this one completes successfully.\r |
| 683 | // If an error is generated by this command, execution will stop.\r |
| 684 | //\r |
| 685 | #define PXE_CONTROL_LINK 0x0001\r |
| 686 | #define PXE_CONTROL_LAST_CDB_IN_LIST 0x0000\r |
| 687 | \r |
| 688 | typedef UINT8 PXE_FRAME_TYPE;\r |
| 689 | \r |
| 690 | #define PXE_FRAME_TYPE_NONE 0x00\r |
| 691 | #define PXE_FRAME_TYPE_UNICAST 0x01\r |
| 692 | #define PXE_FRAME_TYPE_BROADCAST 0x02\r |
| 693 | #define PXE_FRAME_TYPE_MULTICAST 0x03\r |
| 694 | #define PXE_FRAME_TYPE_PROMISCUOUS 0x04\r |
| 695 | \r |
| 696 | typedef UINT32 PXE_IPV4;\r |
| 697 | \r |
| 698 | typedef UINT32 PXE_IPV6[4];\r |
| 699 | #define PXE_MAC_LENGTH 32\r |
| 700 | \r |
| 701 | typedef UINT8 PXE_MAC_ADDR[PXE_MAC_LENGTH];\r |
| 702 | \r |
| 703 | typedef UINT8 PXE_IFTYPE;\r |
| 704 | typedef UINT16 PXE_MEDIA_PROTOCOL;\r |
| 705 | \r |
| 706 | //\r |
| 707 | // This information is from the ARP section of RFC 1700.\r |
| 708 | //\r |
| 709 | // 1 Ethernet (10Mb) [JBP]\r |
| 710 | // 2 Experimental Ethernet (3Mb) [JBP]\r |
| 711 | // 3 Amateur Radio AX.25 [PXK]\r |
| 712 | // 4 Proteon ProNET Token Ring [JBP]\r |
| 713 | // 5 Chaos [GXP]\r |
| 714 | // 6 IEEE 802 Networks [JBP]\r |
| 715 | // 7 ARCNET [JBP]\r |
| 716 | // 8 Hyperchannel [JBP]\r |
| 717 | // 9 Lanstar [TU]\r |
| 718 | // 10 Autonet Short Address [MXB1]\r |
| 719 | // 11 LocalTalk [JKR1]\r |
| 720 | // 12 LocalNet (IBM* PCNet or SYTEK* LocalNET) [JXM]\r |
| 721 | // 13 Ultra link [RXD2]\r |
| 722 | // 14 SMDS [GXC1]\r |
| 723 | // 15 Frame Relay [AGM]\r |
| 724 | // 16 Asynchronous Transmission Mode (ATM) [JXB2]\r |
| 725 | // 17 HDLC [JBP]\r |
| 726 | // 18 Fibre Channel [Yakov Rekhter]\r |
| 727 | // 19 Asynchronous Transmission Mode (ATM) [Mark Laubach]\r |
| 728 | // 20 Serial Line [JBP]\r |
| 729 | // 21 Asynchronous Transmission Mode (ATM) [MXB1]\r |
| 730 | //\r |
| 731 | // * Other names and brands may be claimed as the property of others.\r |
| 732 | //\r |
| 733 | #define PXE_IFTYPE_ETHERNET 0x01\r |
| 734 | #define PXE_IFTYPE_TOKENRING 0x04\r |
| 735 | #define PXE_IFTYPE_FIBRE_CHANNEL 0x12\r |
| 736 | \r |
| 737 | typedef struct s_pxe_hw_undi {\r |
| 738 | UINT32 Signature; // PXE_ROMID_SIGNATURE\r |
| 739 | UINT8 Len; // sizeof(PXE_HW_UNDI)\r |
| 740 | UINT8 Fudge; // makes 8-bit cksum equal zero\r |
| 741 | UINT8 Rev; // PXE_ROMID_REV\r |
| 742 | UINT8 IFcnt; // physical connector count\r |
| 743 | UINT8 MajorVer; // PXE_ROMID_MAJORVER\r |
| 744 | UINT8 MinorVer; // PXE_ROMID_MINORVER\r |
| 745 | UINT16 reserved; // zero, not used\r |
| 746 | UINT32 Implementation; // implementation flags\r |
| 747 | // reserved // vendor use\r |
| 748 | // UINT32 Status; // status port\r |
| 749 | // UINT32 Command; // command port\r |
| 750 | // UINT64 CDBaddr; // CDB address port\r |
| 751 | //\r |
| 752 | } PXE_HW_UNDI;\r |
| 753 | \r |
| 754 | //\r |
| 755 | // Status port bit definitions\r |
| 756 | //\r |
| 757 | //\r |
| 758 | // UNDI operation state\r |
| 759 | //\r |
| 760 | #define PXE_HWSTAT_STATE_MASK 0xC0000000\r |
| 761 | #define PXE_HWSTAT_BUSY 0xC0000000\r |
| 762 | #define PXE_HWSTAT_INITIALIZED 0x80000000\r |
| 763 | #define PXE_HWSTAT_STARTED 0x40000000\r |
| 764 | #define PXE_HWSTAT_STOPPED 0x00000000\r |
| 765 | \r |
| 766 | //\r |
| 767 | // If set, last command failed\r |
| 768 | //\r |
| 769 | #define PXE_HWSTAT_COMMAND_FAILED 0x20000000\r |
| 770 | \r |
| 771 | //\r |
| 772 | // If set, identifies enabled receive filters\r |
| 773 | //\r |
| 774 | #define PXE_HWSTAT_PROMISCUOUS_MULTICAST_RX_ENABLED 0x00001000\r |
| 775 | #define PXE_HWSTAT_PROMISCUOUS_RX_ENABLED 0x00000800\r |
| 776 | #define PXE_HWSTAT_BROADCAST_RX_ENABLED 0x00000400\r |
| 777 | #define PXE_HWSTAT_MULTICAST_RX_ENABLED 0x00000200\r |
| 778 | #define PXE_HWSTAT_UNICAST_RX_ENABLED 0x00000100\r |
| 779 | \r |
| 780 | //\r |
| 781 | // If set, identifies enabled external interrupts\r |
| 782 | //\r |
| 783 | #define PXE_HWSTAT_SOFTWARE_INT_ENABLED 0x00000080\r |
| 784 | #define PXE_HWSTAT_TX_COMPLETE_INT_ENABLED 0x00000040\r |
| 785 | #define PXE_HWSTAT_PACKET_RX_INT_ENABLED 0x00000020\r |
| 786 | #define PXE_HWSTAT_CMD_COMPLETE_INT_ENABLED 0x00000010\r |
| 787 | \r |
| 788 | //\r |
| 789 | // If set, identifies pending interrupts\r |
| 790 | //\r |
| 791 | #define PXE_HWSTAT_SOFTWARE_INT_PENDING 0x00000008\r |
| 792 | #define PXE_HWSTAT_TX_COMPLETE_INT_PENDING 0x00000004\r |
| 793 | #define PXE_HWSTAT_PACKET_RX_INT_PENDING 0x00000002\r |
| 794 | #define PXE_HWSTAT_CMD_COMPLETE_INT_PENDING 0x00000001\r |
| 795 | \r |
| 796 | //\r |
| 797 | // Command port definitions\r |
| 798 | //\r |
| 799 | //\r |
| 800 | // If set, CDB identified in CDBaddr port is given to UNDI.\r |
| 801 | // If not set, other bits in this word will be processed.\r |
| 802 | //\r |
| 803 | #define PXE_HWCMD_ISSUE_COMMAND 0x80000000\r |
| 804 | #define PXE_HWCMD_INTS_AND_FILTS 0x00000000\r |
| 805 | \r |
| 806 | //\r |
| 807 | // Use these to enable/disable receive filters.\r |
| 808 | //\r |
| 809 | #define PXE_HWCMD_PROMISCUOUS_MULTICAST_RX_ENABLE 0x00001000\r |
| 810 | #define PXE_HWCMD_PROMISCUOUS_RX_ENABLE 0x00000800\r |
| 811 | #define PXE_HWCMD_BROADCAST_RX_ENABLE 0x00000400\r |
| 812 | #define PXE_HWCMD_MULTICAST_RX_ENABLE 0x00000200\r |
| 813 | #define PXE_HWCMD_UNICAST_RX_ENABLE 0x00000100\r |
| 814 | \r |
| 815 | //\r |
| 816 | // Use these to enable/disable external interrupts\r |
| 817 | //\r |
| 818 | #define PXE_HWCMD_SOFTWARE_INT_ENABLE 0x00000080\r |
| 819 | #define PXE_HWCMD_TX_COMPLETE_INT_ENABLE 0x00000040\r |
| 820 | #define PXE_HWCMD_PACKET_RX_INT_ENABLE 0x00000020\r |
| 821 | #define PXE_HWCMD_CMD_COMPLETE_INT_ENABLE 0x00000010\r |
| 822 | \r |
| 823 | //\r |
| 824 | // Use these to clear pending external interrupts\r |
| 825 | //\r |
| 826 | #define PXE_HWCMD_CLEAR_SOFTWARE_INT 0x00000008\r |
| 827 | #define PXE_HWCMD_CLEAR_TX_COMPLETE_INT 0x00000004\r |
| 828 | #define PXE_HWCMD_CLEAR_PACKET_RX_INT 0x00000002\r |
| 829 | #define PXE_HWCMD_CLEAR_CMD_COMPLETE_INT 0x00000001\r |
| 830 | \r |
| 831 | typedef struct s_pxe_sw_undi {\r |
| 832 | UINT32 Signature; // PXE_ROMID_SIGNATURE\r |
| 833 | UINT8 Len; // sizeof(PXE_SW_UNDI)\r |
| 834 | UINT8 Fudge; // makes 8-bit cksum zero\r |
| 835 | UINT8 Rev; // PXE_ROMID_REV\r |
| 836 | UINT8 IFcnt; // physical connector count\r |
| 837 | UINT8 MajorVer; // PXE_ROMID_MAJORVER\r |
| 838 | UINT8 MinorVer; // PXE_ROMID_MINORVER\r |
| 839 | UINT16 reserved1; // zero, not used\r |
| 840 | UINT32 Implementation; // Implementation flags\r |
| 841 | UINT64 EntryPoint; // API entry point\r |
| 842 | UINT8 reserved2[3]; // zero, not used\r |
| 843 | UINT8 BusCnt; // number of bustypes supported\r |
| 844 | UINT32 BusType[1]; // list of supported bustypes\r |
| 845 | } PXE_SW_UNDI;\r |
| 846 | \r |
| 847 | typedef union u_pxe_undi {\r |
| 848 | PXE_HW_UNDI hw;\r |
| 849 | PXE_SW_UNDI sw;\r |
| 850 | } PXE_UNDI;\r |
| 851 | \r |
| 852 | //\r |
| 853 | // Signature of !PXE structure\r |
| 854 | //\r |
| 855 | #define PXE_ROMID_SIGNATURE PXE_BUSTYPE ('!', 'P', 'X', 'E')\r |
| 856 | \r |
| 857 | //\r |
| 858 | // !PXE structure format revision\r |
| 859 | //\r |
| 860 | #define PXE_ROMID_REV 0x02\r |
| 861 | \r |
| 862 | //\r |
| 863 | // UNDI command interface revision. These are the values that get sent\r |
| 864 | // in option 94 (Client Network Interface Identifier) in the DHCP Discover\r |
| 865 | // and PXE Boot Server Request packets.\r |
| 866 | //\r |
| 867 | #define PXE_ROMID_MAJORVER 0x03\r |
| 868 | #define PXE_ROMID_MINORVER 0x00\r |
| 869 | #define PXE_ROMID_MINORVER_31 0x10\r |
| 870 | \r |
| 871 | //\r |
| 872 | // Implementation flags\r |
| 873 | //\r |
| 874 | #define PXE_ROMID_IMP_HW_UNDI 0x80000000\r |
| 875 | #define PXE_ROMID_IMP_SW_VIRT_ADDR 0x40000000\r |
| 876 | #define PXE_ROMID_IMP_64BIT_DEVICE 0x00010000\r |
| 877 | #define PXE_ROMID_IMP_FRAG_SUPPORTED 0x00008000\r |
| 878 | #define PXE_ROMID_IMP_CMD_LINK_SUPPORTED 0x00004000\r |
| 879 | #define PXE_ROMID_IMP_CMD_QUEUE_SUPPORTED 0x00002000\r |
| 880 | #define PXE_ROMID_IMP_MULTI_FRAME_SUPPORTED 0x00001000\r |
| 881 | #define PXE_ROMID_IMP_NVDATA_SUPPORT_MASK 0x00000C00\r |
| 882 | #define PXE_ROMID_IMP_NVDATA_BULK_WRITABLE 0x00000C00\r |
| 883 | #define PXE_ROMID_IMP_NVDATA_SPARSE_WRITABLE 0x00000800\r |
| 884 | #define PXE_ROMID_IMP_NVDATA_READ_ONLY 0x00000400\r |
| 885 | #define PXE_ROMID_IMP_NVDATA_NOT_AVAILABLE 0x00000000\r |
| 886 | #define PXE_ROMID_IMP_STATISTICS_SUPPORTED 0x00000200\r |
| 887 | #define PXE_ROMID_IMP_STATION_ADDR_SETTABLE 0x00000100\r |
| 888 | #define PXE_ROMID_IMP_PROMISCUOUS_MULTICAST_RX_SUPPORTED 0x00000080\r |
| 889 | #define PXE_ROMID_IMP_PROMISCUOUS_RX_SUPPORTED 0x00000040\r |
| 890 | #define PXE_ROMID_IMP_BROADCAST_RX_SUPPORTED 0x00000020\r |
| 891 | #define PXE_ROMID_IMP_FILTERED_MULTICAST_RX_SUPPORTED 0x00000010\r |
| 892 | #define PXE_ROMID_IMP_SOFTWARE_INT_SUPPORTED 0x00000008\r |
| 893 | #define PXE_ROMID_IMP_TX_COMPLETE_INT_SUPPORTED 0x00000004\r |
| 894 | #define PXE_ROMID_IMP_PACKET_RX_INT_SUPPORTED 0x00000002\r |
| 895 | #define PXE_ROMID_IMP_CMD_COMPLETE_INT_SUPPORTED 0x00000001\r |
| 896 | \r |
| 897 | typedef struct s_pxe_cdb {\r |
| 898 | PXE_OPCODE OpCode;\r |
| 899 | PXE_OPFLAGS OpFlags;\r |
| 900 | UINT16 CPBsize;\r |
| 901 | UINT16 DBsize;\r |
| 902 | UINT64 CPBaddr;\r |
| 903 | UINT64 DBaddr;\r |
| 904 | PXE_STATCODE StatCode;\r |
| 905 | PXE_STATFLAGS StatFlags;\r |
| 906 | UINT16 IFnum;\r |
| 907 | PXE_CONTROL Control;\r |
| 908 | } PXE_CDB;\r |
| 909 | \r |
| 910 | typedef union u_pxe_ip_addr {\r |
| 911 | PXE_IPV6 IPv6;\r |
| 912 | PXE_IPV4 IPv4;\r |
| 913 | } PXE_IP_ADDR;\r |
| 914 | \r |
| 915 | typedef union pxe_device {\r |
| 916 | //\r |
| 917 | // PCI and PC Card NICs are both identified using bus, device\r |
| 918 | // and function numbers. For PC Card, this may require PC\r |
| 919 | // Card services to be loaded in the BIOS or preboot\r |
| 920 | // environment.\r |
| 921 | //\r |
| 922 | struct {\r |
| 923 | //\r |
| 924 | // See S/W UNDI ROMID structure definition for PCI and\r |
| 925 | // PCC BusType definitions.\r |
| 926 | //\r |
| 927 | UINT32 BusType;\r |
| 928 | \r |
| 929 | //\r |
| 930 | // Bus, device & function numbers that locate this device.\r |
| 931 | //\r |
| 932 | UINT16 Bus;\r |
| 933 | UINT8 Device;\r |
| 934 | UINT8 Function;\r |
| 935 | }\r |
| 936 | PCI, PCC;\r |
| 937 | \r |
| 938 | //\r |
| 939 | // %%TBD - More information is needed about enumerating\r |
| 940 | // USB and 1394 devices.\r |
| 941 | //\r |
| 942 | struct {\r |
| 943 | UINT32 BusType;\r |
| 944 | UINT32 tdb;\r |
| 945 | }\r |
| 946 | USB, _1394;\r |
| 947 | } PXE_DEVICE;\r |
| 948 | \r |
| 949 | //\r |
| 950 | // cpb and db definitions\r |
| 951 | //\r |
| 952 | #define MAX_PCI_CONFIG_LEN 64 // # of dwords\r |
| 953 | #define MAX_EEPROM_LEN 128 // #of dwords\r |
| 954 | #define MAX_XMIT_BUFFERS 32 // recycling Q length for xmit_done\r |
| 955 | #define MAX_MCAST_ADDRESS_CNT 8\r |
| 956 | \r |
| 957 | typedef struct s_pxe_cpb_start {\r |
| 958 | //\r |
| 959 | // PXE_VOID Delay(UINTN microseconds);\r |
| 960 | //\r |
| 961 | // UNDI will never request a delay smaller than 10 microseconds\r |
| 962 | // and will always request delays in increments of 10 microseconds.\r |
| 963 | // The Delay() CallBack routine must delay between n and n + 10\r |
| 964 | // microseconds before returning control to the UNDI.\r |
| 965 | //\r |
| 966 | // This field cannot be set to zero.\r |
| 967 | //\r |
| 968 | UINT64 Delay;\r |
| 969 | \r |
| 970 | //\r |
| 971 | // PXE_VOID Block(UINT32 enable);\r |
| 972 | //\r |
| 973 | // UNDI may need to block multi-threaded/multi-processor access to\r |
| 974 | // critical code sections when programming or accessing the network\r |
| 975 | // device. To this end, a blocking service is needed by the UNDI.\r |
| 976 | // When UNDI needs a block, it will call Block() passing a non-zero\r |
| 977 | // value. When UNDI no longer needs a block, it will call Block()\r |
| 978 | // with a zero value. When called, if the Block() is already enabled,\r |
| 979 | // do not return control to the UNDI until the previous Block() is\r |
| 980 | // disabled.\r |
| 981 | //\r |
| 982 | // This field cannot be set to zero.\r |
| 983 | //\r |
| 984 | UINT64 Block;\r |
| 985 | \r |
| 986 | //\r |
| 987 | // PXE_VOID Virt2Phys(UINT64 virtual, UINT64 physical_ptr);\r |
| 988 | //\r |
| 989 | // UNDI will pass the virtual address of a buffer and the virtual\r |
| 990 | // address of a 64-bit physical buffer. Convert the virtual address\r |
| 991 | // to a physical address and write the result to the physical address\r |
| 992 | // buffer. If virtual and physical addresses are the same, just\r |
| 993 | // copy the virtual address to the physical address buffer.\r |
| 994 | //\r |
| 995 | // This field can be set to zero if virtual and physical addresses\r |
| 996 | // are equal.\r |
| 997 | //\r |
| 998 | UINT64 Virt2Phys;\r |
| 999 | //\r |
| 1000 | // PXE_VOID Mem_IO(UINT8 read_write, UINT8 len, UINT64 port,\r |
| 1001 | // UINT64 buf_addr);\r |
| 1002 | //\r |
| 1003 | // UNDI will read or write the device io space using this call back\r |
| 1004 | // function. It passes the number of bytes as the len parameter and it\r |
| 1005 | // will be either 1,2,4 or 8.\r |
| 1006 | //\r |
| 1007 | // This field can not be set to zero.\r |
| 1008 | //\r |
| 1009 | UINT64 Mem_IO;\r |
| 1010 | } PXE_CPB_START;\r |
| 1011 | \r |
| 1012 | typedef struct s_pxe_cpb_start_31 {\r |
| 1013 | //\r |
| 1014 | // PXE_VOID Delay(UINT64 UnqId, UINTN microseconds);\r |
| 1015 | //\r |
| 1016 | // UNDI will never request a delay smaller than 10 microseconds\r |
| 1017 | // and will always request delays in increments of 10 microseconds.\r |
| 1018 | // The Delay() CallBack routine must delay between n and n + 10\r |
| 1019 | // microseconds before returning control to the UNDI.\r |
| 1020 | //\r |
| 1021 | // This field cannot be set to zero.\r |
| 1022 | //\r |
| 1023 | UINT64 Delay;\r |
| 1024 | \r |
| 1025 | //\r |
| 1026 | // PXE_VOID Block(UINT64 unq_id, UINT32 enable);\r |
| 1027 | //\r |
| 1028 | // UNDI may need to block multi-threaded/multi-processor access to\r |
| 1029 | // critical code sections when programming or accessing the network\r |
| 1030 | // device. To this end, a blocking service is needed by the UNDI.\r |
| 1031 | // When UNDI needs a block, it will call Block() passing a non-zero\r |
| 1032 | // value. When UNDI no longer needs a block, it will call Block()\r |
| 1033 | // with a zero value. When called, if the Block() is already enabled,\r |
| 1034 | // do not return control to the UNDI until the previous Block() is\r |
| 1035 | // disabled.\r |
| 1036 | //\r |
| 1037 | // This field cannot be set to zero.\r |
| 1038 | //\r |
| 1039 | UINT64 Block;\r |
| 1040 | \r |
| 1041 | //\r |
| 1042 | // PXE_VOID Virt2Phys(UINT64 UnqId, UINT64 virtual, UINT64 physical_ptr);\r |
| 1043 | //\r |
| 1044 | // UNDI will pass the virtual address of a buffer and the virtual\r |
| 1045 | // address of a 64-bit physical buffer. Convert the virtual address\r |
| 1046 | // to a physical address and write the result to the physical address\r |
| 1047 | // buffer. If virtual and physical addresses are the same, just\r |
| 1048 | // copy the virtual address to the physical address buffer.\r |
| 1049 | //\r |
| 1050 | // This field can be set to zero if virtual and physical addresses\r |
| 1051 | // are equal.\r |
| 1052 | //\r |
| 1053 | UINT64 Virt2Phys;\r |
| 1054 | //\r |
| 1055 | // PXE_VOID Mem_IO(UINT64 UnqId, UINT8 read_write, UINT8 len, UINT64 port,\r |
| 1056 | // UINT64 buf_addr);\r |
| 1057 | //\r |
| 1058 | // UNDI will read or write the device io space using this call back\r |
| 1059 | // function. It passes the number of bytes as the len parameter and it\r |
| 1060 | // will be either 1,2,4 or 8.\r |
| 1061 | //\r |
| 1062 | // This field can not be set to zero.\r |
| 1063 | //\r |
| 1064 | UINT64 Mem_IO;\r |
| 1065 | //\r |
| 1066 | // PXE_VOID Map_Mem(UINT64 unq_id, UINT64 virtual_addr, UINT32 size,\r |
| 1067 | // UINT32 Direction, UINT64 mapped_addr);\r |
| 1068 | //\r |
| 1069 | // UNDI will pass the virtual address of a buffer, direction of the data\r |
| 1070 | // flow from/to the mapped buffer (the constants are defined below)\r |
| 1071 | // and a place holder (pointer) for the mapped address.\r |
| 1072 | // This call will Map the given address to a physical DMA address and write\r |
| 1073 | // the result to the mapped_addr pointer. If there is no need to\r |
| 1074 | // map the given address to a lower address (i.e. the given address is\r |
| 1075 | // associated with a physical address that is already compatible to be\r |
| 1076 | // used with the DMA, it converts the given virtual address to it's\r |
| 1077 | // physical address and write that in the mapped address pointer.\r |
| 1078 | //\r |
| 1079 | // This field can be set to zero if there is no mapping service available\r |
| 1080 | //\r |
| 1081 | UINT64 Map_Mem;\r |
| 1082 | \r |
| 1083 | //\r |
| 1084 | // PXE_VOID UnMap_Mem(UINT64 unq_id, UINT64 virtual_addr, UINT32 size,\r |
| 1085 | // UINT32 Direction, UINT64 mapped_addr);\r |
| 1086 | //\r |
| 1087 | // UNDI will pass the virtual and mapped addresses of a buffer\r |
| 1088 | // This call will un map the given address\r |
| 1089 | //\r |
| 1090 | // This field can be set to zero if there is no unmapping service available\r |
| 1091 | //\r |
| 1092 | UINT64 UnMap_Mem;\r |
| 1093 | \r |
| 1094 | //\r |
| 1095 | // PXE_VOID Sync_Mem(UINT64 unq_id, UINT64 virtual,\r |
| 1096 | // UINT32 size, UINT32 Direction, UINT64 mapped_addr);\r |
| 1097 | //\r |
| 1098 | // UNDI will pass the virtual and mapped addresses of a buffer\r |
| 1099 | // This call will synchronize the contents of both the virtual and mapped\r |
| 1100 | // buffers for the given Direction.\r |
| 1101 | //\r |
| 1102 | // This field can be set to zero if there is no service available\r |
| 1103 | //\r |
| 1104 | UINT64 Sync_Mem;\r |
| 1105 | \r |
| 1106 | //\r |
| 1107 | // protocol driver can provide anything for this Unique_ID, UNDI remembers\r |
| 1108 | // that as just a 64bit value assocaited to the interface specified by\r |
| 1109 | // the ifnum and gives it back as a parameter to all the call-back routines\r |
| 1110 | // when calling for that interface!\r |
| 1111 | //\r |
| 1112 | UINT64 Unique_ID;\r |
| 1113 | //\r |
| 1114 | } PXE_CPB_START_31;\r |
| 1115 | \r |
| 1116 | #define TO_AND_FROM_DEVICE 0\r |
| 1117 | #define FROM_DEVICE 1\r |
| 1118 | #define TO_DEVICE 2\r |
| 1119 | \r |
| 1120 | #define PXE_DELAY_MILLISECOND 1000\r |
| 1121 | #define PXE_DELAY_SECOND 1000000\r |
| 1122 | #define PXE_IO_READ 0\r |
| 1123 | #define PXE_IO_WRITE 1\r |
| 1124 | #define PXE_MEM_READ 2\r |
| 1125 | #define PXE_MEM_WRITE 4\r |
| 1126 | \r |
| 1127 | typedef struct s_pxe_db_get_init_info {\r |
| 1128 | //\r |
| 1129 | // Minimum length of locked memory buffer that must be given to\r |
| 1130 | // the Initialize command. Giving UNDI more memory will generally\r |
| 1131 | // give better performance.\r |
| 1132 | //\r |
| 1133 | // If MemoryRequired is zero, the UNDI does not need and will not\r |
| 1134 | // use system memory to receive and transmit packets.\r |
| 1135 | //\r |
| 1136 | UINT32 MemoryRequired;\r |
| 1137 | \r |
| 1138 | //\r |
| 1139 | // Maximum frame data length for Tx/Rx excluding the media header.\r |
| 1140 | //\r |
| 1141 | UINT32 FrameDataLen;\r |
| 1142 | \r |
| 1143 | //\r |
| 1144 | // Supported link speeds are in units of mega bits. Common ethernet\r |
| 1145 | // values are 10, 100 and 1000. Unused LinkSpeeds[] entries are zero\r |
| 1146 | // filled.\r |
| 1147 | //\r |
| 1148 | UINT32 LinkSpeeds[4];\r |
| 1149 | \r |
| 1150 | //\r |
| 1151 | // Number of non-volatile storage items.\r |
| 1152 | //\r |
| 1153 | UINT32 NvCount;\r |
| 1154 | \r |
| 1155 | //\r |
| 1156 | // Width of non-volatile storage item in bytes. 0, 1, 2 or 4\r |
| 1157 | //\r |
| 1158 | UINT16 NvWidth;\r |
| 1159 | \r |
| 1160 | //\r |
| 1161 | // Media header length. This is the typical media header length for\r |
| 1162 | // this UNDI. This information is needed when allocating receive\r |
| 1163 | // and transmit buffers.\r |
| 1164 | //\r |
| 1165 | UINT16 MediaHeaderLen;\r |
| 1166 | \r |
| 1167 | //\r |
| 1168 | // Number of bytes in the NIC hardware (MAC) address.\r |
| 1169 | //\r |
| 1170 | UINT16 HWaddrLen;\r |
| 1171 | \r |
| 1172 | //\r |
| 1173 | // Maximum number of multicast MAC addresses in the multicast\r |
| 1174 | // MAC address filter list.\r |
| 1175 | //\r |
| 1176 | UINT16 MCastFilterCnt;\r |
| 1177 | \r |
| 1178 | //\r |
| 1179 | // Default number and size of transmit and receive buffers that will\r |
| 1180 | // be allocated by the UNDI. If MemoryRequired is non-zero, this\r |
| 1181 | // allocation will come out of the memory buffer given to the Initialize\r |
| 1182 | // command. If MemoryRequired is zero, this allocation will come out of\r |
| 1183 | // memory on the NIC.\r |
| 1184 | //\r |
| 1185 | UINT16 TxBufCnt;\r |
| 1186 | UINT16 TxBufSize;\r |
| 1187 | UINT16 RxBufCnt;\r |
| 1188 | UINT16 RxBufSize;\r |
| 1189 | \r |
| 1190 | //\r |
| 1191 | // Hardware interface types defined in the Assigned Numbers RFC\r |
| 1192 | // and used in DHCP and ARP packets.\r |
| 1193 | // See the PXE_IFTYPE typedef and PXE_IFTYPE_xxx macros.\r |
| 1194 | //\r |
| 1195 | UINT8 IFtype;\r |
| 1196 | \r |
| 1197 | //\r |
| 1198 | // Supported duplex. See PXE_DUPLEX_xxxxx #defines below.\r |
| 1199 | //\r |
| 1200 | UINT8 Duplex;\r |
| 1201 | \r |
| 1202 | //\r |
| 1203 | // Supported loopback options. See PXE_LOOPBACK_xxxxx #defines below.\r |
| 1204 | //\r |
| 1205 | UINT8 LoopBack;\r |
| 1206 | } PXE_DB_GET_INIT_INFO;\r |
| 1207 | \r |
| 1208 | #define PXE_MAX_TXRX_UNIT_ETHER 1500\r |
| 1209 | \r |
| 1210 | #define PXE_HWADDR_LEN_ETHER 0x0006\r |
| 1211 | #define PXE_MAC_HEADER_LEN_ETHER 0x000E\r |
| 1212 | \r |
| 1213 | #define PXE_DUPLEX_ENABLE_FULL_SUPPORTED 1\r |
| 1214 | #define PXE_DUPLEX_FORCE_FULL_SUPPORTED 2\r |
| 1215 | \r |
| 1216 | #define PXE_LOOPBACK_INTERNAL_SUPPORTED 1\r |
| 1217 | #define PXE_LOOPBACK_EXTERNAL_SUPPORTED 2\r |
| 1218 | \r |
| 1219 | typedef struct s_pxe_pci_config_info {\r |
| 1220 | //\r |
| 1221 | // This is the flag field for the PXE_DB_GET_CONFIG_INFO union.\r |
| 1222 | // For PCI bus devices, this field is set to PXE_BUSTYPE_PCI.\r |
| 1223 | //\r |
| 1224 | UINT32 BusType;\r |
| 1225 | \r |
| 1226 | //\r |
| 1227 | // This identifies the PCI network device that this UNDI interface\r |
| 1228 | // is bound to.\r |
| 1229 | //\r |
| 1230 | UINT16 Bus;\r |
| 1231 | UINT8 Device;\r |
| 1232 | UINT8 Function;\r |
| 1233 | \r |
| 1234 | //\r |
| 1235 | // This is a copy of the PCI configuration space for this\r |
| 1236 | // network device.\r |
| 1237 | //\r |
| 1238 | union {\r |
| 1239 | UINT8 Byte[256];\r |
| 1240 | UINT16 Word[128];\r |
| 1241 | UINT32 Dword[64];\r |
| 1242 | } Config;\r |
| 1243 | } PXE_PCI_CONFIG_INFO;\r |
| 1244 | \r |
| 1245 | typedef struct s_pxe_pcc_config_info {\r |
| 1246 | //\r |
| 1247 | // This is the flag field for the PXE_DB_GET_CONFIG_INFO union.\r |
| 1248 | // For PCC bus devices, this field is set to PXE_BUSTYPE_PCC.\r |
| 1249 | //\r |
| 1250 | UINT32 BusType;\r |
| 1251 | \r |
| 1252 | //\r |
| 1253 | // This identifies the PCC network device that this UNDI interface\r |
| 1254 | // is bound to.\r |
| 1255 | //\r |
| 1256 | UINT16 Bus;\r |
| 1257 | UINT8 Device;\r |
| 1258 | UINT8 Function;\r |
| 1259 | \r |
| 1260 | //\r |
| 1261 | // This is a copy of the PCC configuration space for this\r |
| 1262 | // network device.\r |
| 1263 | //\r |
| 1264 | union {\r |
| 1265 | UINT8 Byte[256];\r |
| 1266 | UINT16 Word[128];\r |
| 1267 | UINT32 Dword[64];\r |
| 1268 | } Config;\r |
| 1269 | } PXE_PCC_CONFIG_INFO;\r |
| 1270 | \r |
| 1271 | typedef struct s_pxe_usb_config_info {\r |
| 1272 | UINT32 BusType;\r |
| 1273 | //\r |
| 1274 | // %%TBD What should we return here...\r |
| 1275 | //\r |
| 1276 | } PXE_USB_CONFIG_INFO;\r |
| 1277 | \r |
| 1278 | typedef struct s_pxe_1394_config_info {\r |
| 1279 | UINT32 BusType;\r |
| 1280 | //\r |
| 1281 | // %%TBD What should we return here...\r |
| 1282 | //\r |
| 1283 | } PXE_1394_CONFIG_INFO;\r |
| 1284 | \r |
| 1285 | typedef union u_pxe_db_get_config_info {\r |
| 1286 | PXE_PCI_CONFIG_INFO pci;\r |
| 1287 | PXE_PCC_CONFIG_INFO pcc;\r |
| 1288 | PXE_USB_CONFIG_INFO usb;\r |
| 1289 | PXE_1394_CONFIG_INFO _1394;\r |
| 1290 | } PXE_DB_GET_CONFIG_INFO;\r |
| 1291 | \r |
| 1292 | typedef struct s_pxe_cpb_initialize {\r |
| 1293 | //\r |
| 1294 | // Address of first (lowest) byte of the memory buffer. This buffer must\r |
| 1295 | // be in contiguous physical memory and cannot be swapped out. The UNDI\r |
| 1296 | // will be using this for transmit and receive buffering.\r |
| 1297 | //\r |
| 1298 | UINT64 MemoryAddr;\r |
| 1299 | \r |
| 1300 | //\r |
| 1301 | // MemoryLength must be greater than or equal to MemoryRequired\r |
| 1302 | // returned by the Get Init Info command.\r |
| 1303 | //\r |
| 1304 | UINT32 MemoryLength;\r |
| 1305 | \r |
| 1306 | //\r |
| 1307 | // Desired link speed in Mbit/sec. Common ethernet values are 10, 100\r |
| 1308 | // and 1000. Setting a value of zero will auto-detect and/or use the\r |
| 1309 | // default link speed (operation depends on UNDI/NIC functionality).\r |
| 1310 | //\r |
| 1311 | UINT32 LinkSpeed;\r |
| 1312 | \r |
| 1313 | //\r |
| 1314 | // Suggested number and size of receive and transmit buffers to\r |
| 1315 | // allocate. If MemoryAddr and MemoryLength are non-zero, this\r |
| 1316 | // allocation comes out of the supplied memory buffer. If MemoryAddr\r |
| 1317 | // and MemoryLength are zero, this allocation comes out of memory\r |
| 1318 | // on the NIC.\r |
| 1319 | //\r |
| 1320 | // If these fields are set to zero, the UNDI will allocate buffer\r |
| 1321 | // counts and sizes as it sees fit.\r |
| 1322 | //\r |
| 1323 | UINT16 TxBufCnt;\r |
| 1324 | UINT16 TxBufSize;\r |
| 1325 | UINT16 RxBufCnt;\r |
| 1326 | UINT16 RxBufSize;\r |
| 1327 | \r |
| 1328 | //\r |
| 1329 | // The following configuration parameters are optional and must be zero\r |
| 1330 | // to use the default values.\r |
| 1331 | //\r |
| 1332 | UINT8 Duplex;\r |
| 1333 | \r |
| 1334 | UINT8 LoopBack;\r |
| 1335 | } PXE_CPB_INITIALIZE;\r |
| 1336 | \r |
| 1337 | #define PXE_DUPLEX_DEFAULT 0x00\r |
| 1338 | #define PXE_FORCE_FULL_DUPLEX 0x01\r |
| 1339 | #define PXE_ENABLE_FULL_DUPLEX 0x02\r |
| 1340 | #define PXE_FORCE_HALF_DUPLEX 0x04\r |
| 1341 | #define PXE_DISABLE_FULL_DUPLEX 0x08\r |
| 1342 | \r |
| 1343 | #define LOOPBACK_NORMAL 0\r |
| 1344 | #define LOOPBACK_INTERNAL 1\r |
| 1345 | #define LOOPBACK_EXTERNAL 2\r |
| 1346 | \r |
| 1347 | typedef struct s_pxe_db_initialize {\r |
| 1348 | //\r |
| 1349 | // Actual amount of memory used from the supplied memory buffer. This\r |
| 1350 | // may be less that the amount of memory suppllied and may be zero if\r |
| 1351 | // the UNDI and network device do not use external memory buffers.\r |
| 1352 | //\r |
| 1353 | // Memory used by the UNDI and network device is allocated from the\r |
| 1354 | // lowest memory buffer address.\r |
| 1355 | //\r |
| 1356 | UINT32 MemoryUsed;\r |
| 1357 | \r |
| 1358 | //\r |
| 1359 | // Actual number and size of receive and transmit buffers that were\r |
| 1360 | // allocated.\r |
| 1361 | //\r |
| 1362 | UINT16 TxBufCnt;\r |
| 1363 | UINT16 TxBufSize;\r |
| 1364 | UINT16 RxBufCnt;\r |
| 1365 | UINT16 RxBufSize;\r |
| 1366 | } PXE_DB_INITIALIZE;\r |
| 1367 | \r |
| 1368 | typedef struct s_pxe_cpb_receive_filters {\r |
| 1369 | //\r |
| 1370 | // List of multicast MAC addresses. This list, if present, will\r |
| 1371 | // replace the existing multicast MAC address filter list.\r |
| 1372 | //\r |
| 1373 | PXE_MAC_ADDR MCastList[MAX_MCAST_ADDRESS_CNT];\r |
| 1374 | } PXE_CPB_RECEIVE_FILTERS;\r |
| 1375 | \r |
| 1376 | typedef struct s_pxe_db_receive_filters {\r |
| 1377 | //\r |
| 1378 | // Filtered multicast MAC address list.\r |
| 1379 | //\r |
| 1380 | PXE_MAC_ADDR MCastList[MAX_MCAST_ADDRESS_CNT];\r |
| 1381 | } PXE_DB_RECEIVE_FILTERS;\r |
| 1382 | \r |
| 1383 | typedef struct s_pxe_cpb_station_address {\r |
| 1384 | //\r |
| 1385 | // If supplied and supported, the current station MAC address\r |
| 1386 | // will be changed.\r |
| 1387 | //\r |
| 1388 | PXE_MAC_ADDR StationAddr;\r |
| 1389 | } PXE_CPB_STATION_ADDRESS;\r |
| 1390 | \r |
| 1391 | typedef struct s_pxe_dpb_station_address {\r |
| 1392 | //\r |
| 1393 | // Current station MAC address.\r |
| 1394 | //\r |
| 1395 | PXE_MAC_ADDR StationAddr;\r |
| 1396 | \r |
| 1397 | //\r |
| 1398 | // Station broadcast MAC address.\r |
| 1399 | //\r |
| 1400 | PXE_MAC_ADDR BroadcastAddr;\r |
| 1401 | \r |
| 1402 | //\r |
| 1403 | // Permanent station MAC address.\r |
| 1404 | //\r |
| 1405 | PXE_MAC_ADDR PermanentAddr;\r |
| 1406 | } PXE_DB_STATION_ADDRESS;\r |
| 1407 | \r |
| 1408 | typedef struct s_pxe_db_statistics {\r |
| 1409 | //\r |
| 1410 | // Bit field identifying what statistic data is collected by the\r |
| 1411 | // UNDI/NIC.\r |
| 1412 | // If bit 0x00 is set, Data[0x00] is collected.\r |
| 1413 | // If bit 0x01 is set, Data[0x01] is collected.\r |
| 1414 | // If bit 0x20 is set, Data[0x20] is collected.\r |
| 1415 | // If bit 0x21 is set, Data[0x21] is collected.\r |
| 1416 | // Etc.\r |
| 1417 | //\r |
| 1418 | UINT64 Supported;\r |
| 1419 | \r |
| 1420 | //\r |
| 1421 | // Statistic data.\r |
| 1422 | //\r |
| 1423 | UINT64 Data[64];\r |
| 1424 | } PXE_DB_STATISTICS;\r |
| 1425 | \r |
| 1426 | //\r |
| 1427 | // Total number of frames received. Includes frames with errors and\r |
| 1428 | // dropped frames.\r |
| 1429 | //\r |
| 1430 | #define PXE_STATISTICS_RX_TOTAL_FRAMES 0x00\r |
| 1431 | \r |
| 1432 | //\r |
| 1433 | // Number of valid frames received and copied into receive buffers.\r |
| 1434 | //\r |
| 1435 | #define PXE_STATISTICS_RX_GOOD_FRAMES 0x01\r |
| 1436 | \r |
| 1437 | //\r |
| 1438 | // Number of frames below the minimum length for the media.\r |
| 1439 | // This would be <64 for ethernet.\r |
| 1440 | //\r |
| 1441 | #define PXE_STATISTICS_RX_UNDERSIZE_FRAMES 0x02\r |
| 1442 | \r |
| 1443 | //\r |
| 1444 | // Number of frames longer than the maxminum length for the\r |
| 1445 | // media. This would be >1500 for ethernet.\r |
| 1446 | //\r |
| 1447 | #define PXE_STATISTICS_RX_OVERSIZE_FRAMES 0x03\r |
| 1448 | \r |
| 1449 | //\r |
| 1450 | // Valid frames that were dropped because receive buffers were full.\r |
| 1451 | //\r |
| 1452 | #define PXE_STATISTICS_RX_DROPPED_FRAMES 0x04\r |
| 1453 | \r |
| 1454 | //\r |
| 1455 | // Number of valid unicast frames received and not dropped.\r |
| 1456 | //\r |
| 1457 | #define PXE_STATISTICS_RX_UNICAST_FRAMES 0x05\r |
| 1458 | \r |
| 1459 | //\r |
| 1460 | // Number of valid broadcast frames received and not dropped.\r |
| 1461 | //\r |
| 1462 | #define PXE_STATISTICS_RX_BROADCAST_FRAMES 0x06\r |
| 1463 | \r |
| 1464 | //\r |
| 1465 | // Number of valid mutlicast frames received and not dropped.\r |
| 1466 | //\r |
| 1467 | #define PXE_STATISTICS_RX_MULTICAST_FRAMES 0x07\r |
| 1468 | \r |
| 1469 | //\r |
| 1470 | // Number of frames w/ CRC or alignment errors.\r |
| 1471 | //\r |
| 1472 | #define PXE_STATISTICS_RX_CRC_ERROR_FRAMES 0x08\r |
| 1473 | \r |
| 1474 | //\r |
| 1475 | // Total number of bytes received. Includes frames with errors\r |
| 1476 | // and dropped frames.\r |
| 1477 | //\r |
| 1478 | #define PXE_STATISTICS_RX_TOTAL_BYTES 0x09\r |
| 1479 | \r |
| 1480 | //\r |
| 1481 | // Transmit statistics.\r |
| 1482 | //\r |
| 1483 | #define PXE_STATISTICS_TX_TOTAL_FRAMES 0x0A\r |
| 1484 | #define PXE_STATISTICS_TX_GOOD_FRAMES 0x0B\r |
| 1485 | #define PXE_STATISTICS_TX_UNDERSIZE_FRAMES 0x0C\r |
| 1486 | #define PXE_STATISTICS_TX_OVERSIZE_FRAMES 0x0D\r |
| 1487 | #define PXE_STATISTICS_TX_DROPPED_FRAMES 0x0E\r |
| 1488 | #define PXE_STATISTICS_TX_UNICAST_FRAMES 0x0F\r |
| 1489 | #define PXE_STATISTICS_TX_BROADCAST_FRAMES 0x10\r |
| 1490 | #define PXE_STATISTICS_TX_MULTICAST_FRAMES 0x11\r |
| 1491 | #define PXE_STATISTICS_TX_CRC_ERROR_FRAMES 0x12\r |
| 1492 | #define PXE_STATISTICS_TX_TOTAL_BYTES 0x13\r |
| 1493 | \r |
| 1494 | //\r |
| 1495 | // Number of collisions detection on this subnet.\r |
| 1496 | //\r |
| 1497 | #define PXE_STATISTICS_COLLISIONS 0x14\r |
| 1498 | \r |
| 1499 | //\r |
| 1500 | // Number of frames destined for unsupported protocol.\r |
| 1501 | //\r |
| 1502 | #define PXE_STATISTICS_UNSUPPORTED_PROTOCOL 0x15\r |
| 1503 | \r |
| 1504 | typedef struct s_pxe_cpb_mcast_ip_to_mac {\r |
| 1505 | //\r |
| 1506 | // Multicast IP address to be converted to multicast MAC address.\r |
| 1507 | //\r |
| 1508 | PXE_IP_ADDR IP;\r |
| 1509 | } PXE_CPB_MCAST_IP_TO_MAC;\r |
| 1510 | \r |
| 1511 | typedef struct s_pxe_db_mcast_ip_to_mac {\r |
| 1512 | //\r |
| 1513 | // Multicast MAC address.\r |
| 1514 | //\r |
| 1515 | PXE_MAC_ADDR MAC;\r |
| 1516 | } PXE_DB_MCAST_IP_TO_MAC;\r |
| 1517 | \r |
| 1518 | typedef struct s_pxe_cpb_nvdata_sparse {\r |
| 1519 | //\r |
| 1520 | // NvData item list. Only items in this list will be updated.\r |
| 1521 | //\r |
| 1522 | struct {\r |
| 1523 | //\r |
| 1524 | // Non-volatile storage address to be changed.\r |
| 1525 | //\r |
| 1526 | UINT32 Addr;\r |
| 1527 | \r |
| 1528 | //\r |
| 1529 | // Data item to write into above storage address.\r |
| 1530 | //\r |
| 1531 | union {\r |
| 1532 | UINT8 Byte;\r |
| 1533 | UINT16 Word;\r |
| 1534 | UINT32 Dword;\r |
| 1535 | } Data;\r |
| 1536 | } Item[MAX_EEPROM_LEN];\r |
| 1537 | }\r |
| 1538 | PXE_CPB_NVDATA_SPARSE;\r |
| 1539 | \r |
| 1540 | //\r |
| 1541 | // When using bulk update, the size of the CPB structure must be\r |
| 1542 | // the same size as the non-volatile NIC storage.\r |
| 1543 | //\r |
| 1544 | typedef union u_pxe_cpb_nvdata_bulk {\r |
| 1545 | //\r |
| 1546 | // Array of byte-wide data items.\r |
| 1547 | //\r |
| 1548 | UINT8 Byte[MAX_EEPROM_LEN << 2];\r |
| 1549 | \r |
| 1550 | //\r |
| 1551 | // Array of word-wide data items.\r |
| 1552 | //\r |
| 1553 | UINT16 Word[MAX_EEPROM_LEN << 1];\r |
| 1554 | \r |
| 1555 | //\r |
| 1556 | // Array of dword-wide data items.\r |
| 1557 | //\r |
| 1558 | UINT32 Dword[MAX_EEPROM_LEN];\r |
| 1559 | } PXE_CPB_NVDATA_BULK;\r |
| 1560 | \r |
| 1561 | typedef struct s_pxe_db_nvdata {\r |
| 1562 | //\r |
| 1563 | // Arrays of data items from non-volatile storage.\r |
| 1564 | //\r |
| 1565 | union {\r |
| 1566 | //\r |
| 1567 | // Array of byte-wide data items.\r |
| 1568 | //\r |
| 1569 | UINT8 Byte[MAX_EEPROM_LEN << 2];\r |
| 1570 | \r |
| 1571 | //\r |
| 1572 | // Array of word-wide data items.\r |
| 1573 | //\r |
| 1574 | UINT16 Word[MAX_EEPROM_LEN << 1];\r |
| 1575 | \r |
| 1576 | //\r |
| 1577 | // Array of dword-wide data items.\r |
| 1578 | //\r |
| 1579 | UINT32 Dword[MAX_EEPROM_LEN];\r |
| 1580 | } Data;\r |
| 1581 | } PXE_DB_NVDATA;\r |
| 1582 | \r |
| 1583 | typedef struct s_pxe_db_get_status {\r |
| 1584 | //\r |
| 1585 | // Length of next receive frame (header + data). If this is zero,\r |
| 1586 | // there is no next receive frame available.\r |
| 1587 | //\r |
| 1588 | UINT32 RxFrameLen;\r |
| 1589 | \r |
| 1590 | //\r |
| 1591 | // Reserved, set to zero.\r |
| 1592 | //\r |
| 1593 | UINT32 reserved;\r |
| 1594 | \r |
| 1595 | //\r |
| 1596 | // Addresses of transmitted buffers that need to be recycled.\r |
| 1597 | //\r |
| 1598 | UINT64 TxBuffer[MAX_XMIT_BUFFERS];\r |
| 1599 | } PXE_DB_GET_STATUS;\r |
| 1600 | \r |
| 1601 | typedef struct s_pxe_cpb_fill_header {\r |
| 1602 | //\r |
| 1603 | // Source and destination MAC addresses. These will be copied into\r |
| 1604 | // the media header without doing byte swapping.\r |
| 1605 | //\r |
| 1606 | PXE_MAC_ADDR SrcAddr;\r |
| 1607 | PXE_MAC_ADDR DestAddr;\r |
| 1608 | \r |
| 1609 | //\r |
| 1610 | // Address of first byte of media header. The first byte of packet data\r |
| 1611 | // follows the last byte of the media header.\r |
| 1612 | //\r |
| 1613 | UINT64 MediaHeader;\r |
| 1614 | \r |
| 1615 | //\r |
| 1616 | // Length of packet data in bytes (not including the media header).\r |
| 1617 | //\r |
| 1618 | UINT32 PacketLen;\r |
| 1619 | \r |
| 1620 | //\r |
| 1621 | // Protocol type. This will be copied into the media header without\r |
| 1622 | // doing byte swapping. Protocol type numbers can be obtained from\r |
| 1623 | // the Assigned Numbers RFC 1700.\r |
| 1624 | //\r |
| 1625 | UINT16 Protocol;\r |
| 1626 | \r |
| 1627 | //\r |
| 1628 | // Length of the media header in bytes.\r |
| 1629 | //\r |
| 1630 | UINT16 MediaHeaderLen;\r |
| 1631 | } PXE_CPB_FILL_HEADER;\r |
| 1632 | \r |
| 1633 | #define PXE_PROTOCOL_ETHERNET_IP 0x0800\r |
| 1634 | #define PXE_PROTOCOL_ETHERNET_ARP 0x0806\r |
| 1635 | #define MAX_XMIT_FRAGMENTS 16\r |
| 1636 | \r |
| 1637 | typedef struct s_pxe_cpb_fill_header_fragmented {\r |
| 1638 | //\r |
| 1639 | // Source and destination MAC addresses. These will be copied into\r |
| 1640 | // the media header without doing byte swapping.\r |
| 1641 | //\r |
| 1642 | PXE_MAC_ADDR SrcAddr;\r |
| 1643 | PXE_MAC_ADDR DestAddr;\r |
| 1644 | \r |
| 1645 | //\r |
| 1646 | // Length of packet data in bytes (not including the media header).\r |
| 1647 | //\r |
| 1648 | UINT32 PacketLen;\r |
| 1649 | \r |
| 1650 | //\r |
| 1651 | // Protocol type. This will be copied into the media header without\r |
| 1652 | // doing byte swapping. Protocol type numbers can be obtained from\r |
| 1653 | // the Assigned Numbers RFC 1700.\r |
| 1654 | //\r |
| 1655 | PXE_MEDIA_PROTOCOL Protocol;\r |
| 1656 | \r |
| 1657 | //\r |
| 1658 | // Length of the media header in bytes.\r |
| 1659 | //\r |
| 1660 | UINT16 MediaHeaderLen;\r |
| 1661 | \r |
| 1662 | //\r |
| 1663 | // Number of packet fragment descriptors.\r |
| 1664 | //\r |
| 1665 | UINT16 FragCnt;\r |
| 1666 | \r |
| 1667 | //\r |
| 1668 | // Reserved, must be set to zero.\r |
| 1669 | //\r |
| 1670 | UINT16 reserved;\r |
| 1671 | \r |
| 1672 | //\r |
| 1673 | // Array of packet fragment descriptors. The first byte of the media\r |
| 1674 | // header is the first byte of the first fragment.\r |
| 1675 | //\r |
| 1676 | struct {\r |
| 1677 | //\r |
| 1678 | // Address of this packet fragment.\r |
| 1679 | //\r |
| 1680 | UINT64 FragAddr;\r |
| 1681 | \r |
| 1682 | //\r |
| 1683 | // Length of this packet fragment.\r |
| 1684 | //\r |
| 1685 | UINT32 FragLen;\r |
| 1686 | \r |
| 1687 | //\r |
| 1688 | // Reserved, must be set to zero.\r |
| 1689 | //\r |
| 1690 | UINT32 reserved;\r |
| 1691 | } FragDesc[MAX_XMIT_FRAGMENTS];\r |
| 1692 | }\r |
| 1693 | PXE_CPB_FILL_HEADER_FRAGMENTED;\r |
| 1694 | \r |
| 1695 | typedef struct s_pxe_cpb_transmit {\r |
| 1696 | //\r |
| 1697 | // Address of first byte of frame buffer. This is also the first byte\r |
| 1698 | // of the media header.\r |
| 1699 | //\r |
| 1700 | UINT64 FrameAddr;\r |
| 1701 | \r |
| 1702 | //\r |
| 1703 | // Length of the data portion of the frame buffer in bytes. Do not\r |
| 1704 | // include the length of the media header.\r |
| 1705 | //\r |
| 1706 | UINT32 DataLen;\r |
| 1707 | \r |
| 1708 | //\r |
| 1709 | // Length of the media header in bytes.\r |
| 1710 | //\r |
| 1711 | UINT16 MediaheaderLen;\r |
| 1712 | \r |
| 1713 | //\r |
| 1714 | // Reserved, must be zero.\r |
| 1715 | //\r |
| 1716 | UINT16 reserved;\r |
| 1717 | } PXE_CPB_TRANSMIT;\r |
| 1718 | \r |
| 1719 | typedef struct s_pxe_cpb_transmit_fragments {\r |
| 1720 | //\r |
| 1721 | // Length of packet data in bytes (not including the media header).\r |
| 1722 | //\r |
| 1723 | UINT32 FrameLen;\r |
| 1724 | \r |
| 1725 | //\r |
| 1726 | // Length of the media header in bytes.\r |
| 1727 | //\r |
| 1728 | UINT16 MediaheaderLen;\r |
| 1729 | \r |
| 1730 | //\r |
| 1731 | // Number of packet fragment descriptors.\r |
| 1732 | //\r |
| 1733 | UINT16 FragCnt;\r |
| 1734 | \r |
| 1735 | //\r |
| 1736 | // Array of frame fragment descriptors. The first byte of the first\r |
| 1737 | // fragment is also the first byte of the media header.\r |
| 1738 | //\r |
| 1739 | struct {\r |
| 1740 | //\r |
| 1741 | // Address of this frame fragment.\r |
| 1742 | //\r |
| 1743 | UINT64 FragAddr;\r |
| 1744 | \r |
| 1745 | //\r |
| 1746 | // Length of this frame fragment.\r |
| 1747 | //\r |
| 1748 | UINT32 FragLen;\r |
| 1749 | \r |
| 1750 | //\r |
| 1751 | // Reserved, must be set to zero.\r |
| 1752 | //\r |
| 1753 | UINT32 reserved;\r |
| 1754 | } FragDesc[MAX_XMIT_FRAGMENTS];\r |
| 1755 | }\r |
| 1756 | PXE_CPB_TRANSMIT_FRAGMENTS;\r |
| 1757 | \r |
| 1758 | typedef struct s_pxe_cpb_receive {\r |
| 1759 | //\r |
| 1760 | // Address of first byte of receive buffer. This is also the first byte\r |
| 1761 | // of the frame header.\r |
| 1762 | //\r |
| 1763 | UINT64 BufferAddr;\r |
| 1764 | \r |
| 1765 | //\r |
| 1766 | // Length of receive buffer. This must be large enough to hold the\r |
| 1767 | // received frame (media header + data). If the length of smaller than\r |
| 1768 | // the received frame, data will be lost.\r |
| 1769 | //\r |
| 1770 | UINT32 BufferLen;\r |
| 1771 | \r |
| 1772 | //\r |
| 1773 | // Reserved, must be set to zero.\r |
| 1774 | //\r |
| 1775 | UINT32 reserved;\r |
| 1776 | } PXE_CPB_RECEIVE;\r |
| 1777 | \r |
| 1778 | typedef struct s_pxe_db_receive {\r |
| 1779 | //\r |
| 1780 | // Source and destination MAC addresses from media header.\r |
| 1781 | //\r |
| 1782 | PXE_MAC_ADDR SrcAddr;\r |
| 1783 | PXE_MAC_ADDR DestAddr;\r |
| 1784 | \r |
| 1785 | //\r |
| 1786 | // Length of received frame. May be larger than receive buffer size.\r |
| 1787 | // The receive buffer will not be overwritten. This is how to tell\r |
| 1788 | // if data was lost because the receive buffer was too small.\r |
| 1789 | //\r |
| 1790 | UINT32 FrameLen;\r |
| 1791 | \r |
| 1792 | //\r |
| 1793 | // Protocol type from media header.\r |
| 1794 | //\r |
| 1795 | PXE_MEDIA_PROTOCOL Protocol;\r |
| 1796 | \r |
| 1797 | //\r |
| 1798 | // Length of media header in received frame.\r |
| 1799 | //\r |
| 1800 | UINT16 MediaHeaderLen;\r |
| 1801 | \r |
| 1802 | //\r |
| 1803 | // Type of receive frame.\r |
| 1804 | //\r |
| 1805 | PXE_FRAME_TYPE Type;\r |
| 1806 | \r |
| 1807 | //\r |
| 1808 | // Reserved, must be zero.\r |
| 1809 | //\r |
| 1810 | UINT8 reserved[7];\r |
| 1811 | \r |
| 1812 | } PXE_DB_RECEIVE;\r |
| 1813 | \r |
| 1814 | #pragma pack()\r |
| 1815 | \r |
| 1816 | #endif\r |
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