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fixed memcpy link issue.
[mirror_edk2.git] / EdkCompatibilityPkg / Foundation / Include / EfiPxe.h
1 /*++
2
3 Copyright (c) 2004 - 2006, Intel Corporation
4 All rights reserved. This program and the accompanying materials
5 are licensed and made available under the terms and conditions of the BSD License
6 which accompanies this distribution. The full text of the license may be found at
7 http://opensource.org/licenses/bsd-license.php
8
9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
11
12 Module name:
13
14 EfiPxe.h
15
16 32/64-bit PXE specification:
17
18 alpha-4, 99-Dec-17
19
20 Abstract:
21
22 This header file contains all of the PXE type definitions,
23 structure prototypes, global variables and constants that
24 are needed for porting PXE to EFI.
25 --*/
26
27 #ifndef _EFIPXE_H
28 #define _EFIPXE_H
29
30 #pragma pack(1)
31
32 #define PXE_INTEL_ORDER 1 // Intel order
33 // #define PXE_NETWORK_ORDER 1 // network order
34 //
35 #define PXE_UINT64_SUPPORT 1 // UINT64 supported
36 // #define PXE_NO_UINT64_SUPPORT 1 // UINT64 not supported
37 //
38 #define PXE_BUSTYPE(a, b, c, d) \
39 ( \
40 (((UINT32) (d) & 0xFF) << 24) | (((UINT32) (c) & 0xFF) << 16) | (((UINT32) (b) & 0xFF) << 8) | \
41 ((UINT32) (a) & 0xFF) \
42 )
43
44 //
45 // UNDI ROM ID and devive ID signature
46 //
47 #define PXE_BUSTYPE_PXE PXE_BUSTYPE ('!', 'P', 'X', 'E')
48
49 //
50 // BUS ROM ID signatures
51 //
52 #define PXE_BUSTYPE_PCI PXE_BUSTYPE ('P', 'C', 'I', 'R')
53 #define PXE_BUSTYPE_PC_CARD PXE_BUSTYPE ('P', 'C', 'C', 'R')
54 #define PXE_BUSTYPE_USB PXE_BUSTYPE ('U', 'S', 'B', 'R')
55 #define PXE_BUSTYPE_1394 PXE_BUSTYPE ('1', '3', '9', '4')
56
57 #define PXE_SWAP_UINT16(n) ((((UINT16) (n) & 0x00FF) << 8) | (((UINT16) (n) & 0xFF00) >> 8))
58
59 #define PXE_SWAP_UINT32(n) \
60 ((((UINT32)(n) & 0x000000FF) << 24) | \
61 (((UINT32)(n) & 0x0000FF00) << 8) | \
62 (((UINT32)(n) & 0x00FF0000) >> 8) | \
63 (((UINT32)(n) & 0xFF000000) >> 24))
64
65 #if PXE_UINT64_SUPPORT != 0
66 #define PXE_SWAP_UINT64(n) \
67 ((((UINT64)(n) & 0x00000000000000FF) << 56) | \
68 (((UINT64)(n) & 0x000000000000FF00) << 40) | \
69 (((UINT64)(n) & 0x0000000000FF0000) << 24) | \
70 (((UINT64)(n) & 0x00000000FF000000) << 8) | \
71 (((UINT64)(n) & 0x000000FF00000000) >> 8) | \
72 (((UINT64)(n) & 0x0000FF0000000000) >> 24) | \
73 (((UINT64)(n) & 0x00FF000000000000) >> 40) | \
74 (((UINT64)(n) & 0xFF00000000000000) >> 56))
75 #endif // PXE_UINT64_SUPPORT
76 #if PXE_NO_UINT64_SUPPORT != 0
77 #define PXE_SWAP_UINT64(n) { \
78 UINT32 tmp; \
79 tmp = (PXE_UINT64) (n)[1]; \
80 (UINT64) (n)[1] = PXE_SWAP_UINT32 ((UINT64) (n)[0]); \
81 (UINT64) (n)[0] = tmp; \
82 }
83 #endif // PXE_NO_UINT64_SUPPORT
84 #define PXE_CPBSIZE_NOT_USED 0 // zero
85 #define PXE_DBSIZE_NOT_USED 0 // zero
86 #define PXE_CPBADDR_NOT_USED (PXE_UINT64) 0 // zero
87 #define PXE_DBADDR_NOT_USED (PXE_UINT64) 0 // zero
88 #define PXE_CONST const
89
90 #define PXE_VOLATILE volatile
91
92 #if PXE_UINT64_SUPPORT != 0
93 //
94 // typedef unsigned long PXE_UINT64;
95 //
96 typedef UINT64 PXE_UINT64;
97 #endif // PXE_UINT64_SUPPORT
98 #if PXE_NO_UINT64_SUPPORT != 0
99 typedef PXE_UINT32 PXE_UINT64[2];
100 #endif // PXE_NO_UINT64_SUPPORT
101 #define PXE_FALSE 0 // zero
102 #define PXE_TRUE (!PXE_FALSE)
103
104 typedef UINT16 PXE_OPCODE;
105
106 //
107 // Return UNDI operational state.
108 //
109 #define PXE_OPCODE_GET_STATE 0x0000
110
111 //
112 // Change UNDI operational state from Stopped to Started.
113 //
114 #define PXE_OPCODE_START 0x0001
115
116 //
117 // Change UNDI operational state from Started to Stopped.
118 //
119 #define PXE_OPCODE_STOP 0x0002
120
121 //
122 // Get UNDI initialization information.
123 //
124 #define PXE_OPCODE_GET_INIT_INFO 0x0003
125
126 //
127 // Get NIC configuration information.
128 //
129 #define PXE_OPCODE_GET_CONFIG_INFO 0x0004
130
131 //
132 // Changed UNDI operational state from Started to Initialized.
133 //
134 #define PXE_OPCODE_INITIALIZE 0x0005
135
136 //
137 // Re-initialize the NIC H/W.
138 //
139 #define PXE_OPCODE_RESET 0x0006
140
141 //
142 // Change the UNDI operational state from Initialized to Started.
143 //
144 #define PXE_OPCODE_SHUTDOWN 0x0007
145
146 //
147 // Read & change state of external interrupt enables.
148 //
149 #define PXE_OPCODE_INTERRUPT_ENABLES 0x0008
150
151 //
152 // Read & change state of packet receive filters.
153 //
154 #define PXE_OPCODE_RECEIVE_FILTERS 0x0009
155
156 //
157 // Read & change station MAC address.
158 //
159 #define PXE_OPCODE_STATION_ADDRESS 0x000A
160
161 //
162 // Read traffic statistics.
163 //
164 #define PXE_OPCODE_STATISTICS 0x000B
165
166 //
167 // Convert multicast IP address to multicast MAC address.
168 //
169 #define PXE_OPCODE_MCAST_IP_TO_MAC 0x000C
170
171 //
172 // Read or change non-volatile storage on the NIC.
173 //
174 #define PXE_OPCODE_NVDATA 0x000D
175
176 //
177 // Get & clear interrupt status.
178 //
179 #define PXE_OPCODE_GET_STATUS 0x000E
180
181 //
182 // Fill media header in packet for transmit.
183 //
184 #define PXE_OPCODE_FILL_HEADER 0x000F
185
186 //
187 // Transmit packet(s).
188 //
189 #define PXE_OPCODE_TRANSMIT 0x0010
190
191 //
192 // Receive packet.
193 //
194 #define PXE_OPCODE_RECEIVE 0x0011
195
196 //
197 // last valid opcode:
198 //
199 #define PXE_OPCODE_VALID_MAX 0x0011
200
201 //
202 // Last valid PXE UNDI OpCode number.
203 //
204 #define PXE_OPCODE_LAST_VALID 0x0011
205
206 typedef UINT16 PXE_OPFLAGS;
207
208 #define PXE_OPFLAGS_NOT_USED 0x0000
209
210 //
211 // //////////////////////////////////////
212 // UNDI Get State
213 //
214 // No OpFlags
215
216 ////////////////////////////////////////
217 // UNDI Start
218 //
219 // No OpFlags
220
221 ////////////////////////////////////////
222 // UNDI Stop
223 //
224 // No OpFlags
225
226 ////////////////////////////////////////
227 // UNDI Get Init Info
228 //
229 // No Opflags
230
231 ////////////////////////////////////////
232 // UNDI Get Config Info
233 //
234 // No Opflags
235
236 ////////////////////////////////////////
237 // UNDI Initialize
238 //
239 #define PXE_OPFLAGS_INITIALIZE_CABLE_DETECT_MASK 0x0001
240 #define PXE_OPFLAGS_INITIALIZE_DETECT_CABLE 0x0000
241 #define PXE_OPFLAGS_INITIALIZE_DO_NOT_DETECT_CABLE 0x0001
242
243 //
244 // //////////////////////////////////////
245 // UNDI Reset
246 //
247 #define PXE_OPFLAGS_RESET_DISABLE_INTERRUPTS 0x0001
248 #define PXE_OPFLAGS_RESET_DISABLE_FILTERS 0x0002
249
250 //
251 // //////////////////////////////////////
252 // UNDI Shutdown
253 //
254 // No OpFlags
255
256 ////////////////////////////////////////
257 // UNDI Interrupt Enables
258 //
259 //
260 // Select whether to enable or disable external interrupt signals.
261 // Setting both enable and disable will return PXE_STATCODE_INVALID_OPFLAGS.
262 //
263 #define PXE_OPFLAGS_INTERRUPT_OPMASK 0xC000
264 #define PXE_OPFLAGS_INTERRUPT_ENABLE 0x8000
265 #define PXE_OPFLAGS_INTERRUPT_DISABLE 0x4000
266 #define PXE_OPFLAGS_INTERRUPT_READ 0x0000
267
268 //
269 // Enable receive interrupts. An external interrupt will be generated
270 // after a complete non-error packet has been received.
271 //
272 #define PXE_OPFLAGS_INTERRUPT_RECEIVE 0x0001
273
274 //
275 // Enable transmit interrupts. An external interrupt will be generated
276 // after a complete non-error packet has been transmitted.
277 //
278 #define PXE_OPFLAGS_INTERRUPT_TRANSMIT 0x0002
279
280 //
281 // Enable command interrupts. An external interrupt will be generated
282 // when command execution stops.
283 //
284 #define PXE_OPFLAGS_INTERRUPT_COMMAND 0x0004
285
286 //
287 // Generate software interrupt. Setting this bit generates an external
288 // interrupt, if it is supported by the hardware.
289 //
290 #define PXE_OPFLAGS_INTERRUPT_SOFTWARE 0x0008
291
292 //
293 // //////////////////////////////////////
294 // UNDI Receive Filters
295 //
296 //
297 // Select whether to enable or disable receive filters.
298 // Setting both enable and disable will return PXE_STATCODE_INVALID_OPCODE.
299 //
300 #define PXE_OPFLAGS_RECEIVE_FILTER_OPMASK 0xC000
301 #define PXE_OPFLAGS_RECEIVE_FILTER_ENABLE 0x8000
302 #define PXE_OPFLAGS_RECEIVE_FILTER_DISABLE 0x4000
303 #define PXE_OPFLAGS_RECEIVE_FILTER_READ 0x0000
304
305 //
306 // To reset the contents of the multicast MAC address filter list,
307 // set this OpFlag:
308 //
309 #define PXE_OPFLAGS_RECEIVE_FILTER_RESET_MCAST_LIST 0x2000
310
311 //
312 // Enable unicast packet receiving. Packets sent to the current station
313 // MAC address will be received.
314 //
315 #define PXE_OPFLAGS_RECEIVE_FILTER_UNICAST 0x0001
316
317 //
318 // Enable broadcast packet receiving. Packets sent to the broadcast
319 // MAC address will be received.
320 //
321 #define PXE_OPFLAGS_RECEIVE_FILTER_BROADCAST 0x0002
322
323 //
324 // Enable filtered multicast packet receiving. Packets sent to any
325 // of the multicast MAC addresses in the multicast MAC address filter
326 // list will be received. If the filter list is empty, no multicast
327 //
328 #define PXE_OPFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST 0x0004
329
330 //
331 // Enable promiscuous packet receiving. All packets will be received.
332 //
333 #define PXE_OPFLAGS_RECEIVE_FILTER_PROMISCUOUS 0x0008
334
335 //
336 // Enable promiscuous multicast packet receiving. All multicast
337 // packets will be received.
338 //
339 #define PXE_OPFLAGS_RECEIVE_FILTER_ALL_MULTICAST 0x0010
340
341 //
342 // //////////////////////////////////////
343 // UNDI Station Address
344 //
345 #define PXE_OPFLAGS_STATION_ADDRESS_READ 0x0000
346 #define PXE_OPFLAGS_STATION_ADDRESS_WRITE 0x0000
347 #define PXE_OPFLAGS_STATION_ADDRESS_RESET 0x0001
348
349 //
350 // //////////////////////////////////////
351 // UNDI Statistics
352 //
353 #define PXE_OPFLAGS_STATISTICS_READ 0x0000
354 #define PXE_OPFLAGS_STATISTICS_RESET 0x0001
355
356 //
357 // //////////////////////////////////////
358 // UNDI MCast IP to MAC
359 //
360 //
361 // Identify the type of IP address in the CPB.
362 //
363 #define PXE_OPFLAGS_MCAST_IP_TO_MAC_OPMASK 0x0003
364 #define PXE_OPFLAGS_MCAST_IPV4_TO_MAC 0x0000
365 #define PXE_OPFLAGS_MCAST_IPV6_TO_MAC 0x0001
366
367 //
368 // //////////////////////////////////////
369 // UNDI NvData
370 //
371 //
372 // Select the type of non-volatile data operation.
373 //
374 #define PXE_OPFLAGS_NVDATA_OPMASK 0x0001
375 #define PXE_OPFLAGS_NVDATA_READ 0x0000
376 #define PXE_OPFLAGS_NVDATA_WRITE 0x0001
377
378 //
379 // //////////////////////////////////////
380 // UNDI Get Status
381 //
382 //
383 // Return current interrupt status. This will also clear any interrupts
384 // that are currently set. This can be used in a polling routine. The
385 // interrupt flags are still set and cleared even when the interrupts
386 // are disabled.
387 //
388 #define PXE_OPFLAGS_GET_INTERRUPT_STATUS 0x0001
389
390 //
391 // Return list of transmitted buffers for recycling. Transmit buffers
392 // must not be changed or unallocated until they have recycled. After
393 // issuing a transmit command, wait for a transmit complete interrupt.
394 // When a transmit complete interrupt is received, read the transmitted
395 // buffers. Do not plan on getting one buffer per interrupt. Some
396 // NICs and UNDIs may transmit multiple buffers per interrupt.
397 //
398 #define PXE_OPFLAGS_GET_TRANSMITTED_BUFFERS 0x0002
399
400 //
401 // //////////////////////////////////////
402 // UNDI Fill Header
403 //
404 #define PXE_OPFLAGS_FILL_HEADER_OPMASK 0x0001
405 #define PXE_OPFLAGS_FILL_HEADER_FRAGMENTED 0x0001
406 #define PXE_OPFLAGS_FILL_HEADER_WHOLE 0x0000
407
408 //
409 // //////////////////////////////////////
410 // UNDI Transmit
411 //
412 //
413 // S/W UNDI only. Return after the packet has been transmitted. A
414 // transmit complete interrupt will still be generated and the transmit
415 // buffer will have to be recycled.
416 //
417 #define PXE_OPFLAGS_SWUNDI_TRANSMIT_OPMASK 0x0001
418 #define PXE_OPFLAGS_TRANSMIT_BLOCK 0x0001
419 #define PXE_OPFLAGS_TRANSMIT_DONT_BLOCK 0x0000
420
421 //
422 //
423 //
424 #define PXE_OPFLAGS_TRANSMIT_OPMASK 0x0002
425 #define PXE_OPFLAGS_TRANSMIT_FRAGMENTED 0x0002
426 #define PXE_OPFLAGS_TRANSMIT_WHOLE 0x0000
427
428 //
429 // //////////////////////////////////////
430 // UNDI Receive
431 //
432 // No OpFlags
433 //
434 typedef UINT16 PXE_STATFLAGS;
435
436 #define PXE_STATFLAGS_INITIALIZE 0x0000
437
438 //
439 // //////////////////////////////////////
440 // Common StatFlags that can be returned by all commands.
441 //
442 //
443 // The COMMAND_COMPLETE and COMMAND_FAILED status flags must be
444 // implemented by all UNDIs. COMMAND_QUEUED is only needed by UNDIs
445 // that support command queuing.
446 //
447 #define PXE_STATFLAGS_STATUS_MASK 0xC000
448 #define PXE_STATFLAGS_COMMAND_COMPLETE 0xC000
449 #define PXE_STATFLAGS_COMMAND_FAILED 0x8000
450 #define PXE_STATFLAGS_COMMAND_QUEUED 0x4000
451 //
452 // #define PXE_STATFLAGS_INITIALIZE 0x0000
453 //
454 #define PXE_STATFLAGS_DB_WRITE_TRUNCATED 0x2000
455
456 //
457 // //////////////////////////////////////
458 // UNDI Get State
459 //
460 #define PXE_STATFLAGS_GET_STATE_MASK 0x0003
461 #define PXE_STATFLAGS_GET_STATE_INITIALIZED 0x0002
462 #define PXE_STATFLAGS_GET_STATE_STARTED 0x0001
463 #define PXE_STATFLAGS_GET_STATE_STOPPED 0x0000
464
465 //
466 // //////////////////////////////////////
467 // UNDI Start
468 //
469 // No additional StatFlags
470
471 ////////////////////////////////////////
472 // UNDI Get Init Info
473 //
474 #define PXE_STATFLAGS_CABLE_DETECT_MASK 0x0001
475 #define PXE_STATFLAGS_CABLE_DETECT_NOT_SUPPORTED 0x0000
476 #define PXE_STATFLAGS_CABLE_DETECT_SUPPORTED 0x0001
477
478 //
479 // //////////////////////////////////////
480 // UNDI Initialize
481 //
482 #define PXE_STATFLAGS_INITIALIZED_NO_MEDIA 0x0001
483
484 //
485 // //////////////////////////////////////
486 // UNDI Reset
487 //
488 #define PXE_STATFLAGS_RESET_NO_MEDIA 0x0001
489
490 //
491 // //////////////////////////////////////
492 // UNDI Shutdown
493 //
494 // No additional StatFlags
495
496 ////////////////////////////////////////
497 // UNDI Interrupt Enables
498 //
499 //
500 // If set, receive interrupts are enabled.
501 //
502 #define PXE_STATFLAGS_INTERRUPT_RECEIVE 0x0001
503
504 //
505 // If set, transmit interrupts are enabled.
506 //
507 #define PXE_STATFLAGS_INTERRUPT_TRANSMIT 0x0002
508
509 //
510 // If set, command interrupts are enabled.
511 //
512 #define PXE_STATFLAGS_INTERRUPT_COMMAND 0x0004
513
514 //
515 // //////////////////////////////////////
516 // UNDI Receive Filters
517 //
518 //
519 // If set, unicast packets will be received.
520 //
521 #define PXE_STATFLAGS_RECEIVE_FILTER_UNICAST 0x0001
522
523 //
524 // If set, broadcast packets will be received.
525 //
526 #define PXE_STATFLAGS_RECEIVE_FILTER_BROADCAST 0x0002
527
528 //
529 // If set, multicast packets that match up with the multicast address
530 // filter list will be received.
531 //
532 #define PXE_STATFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST 0x0004
533
534 //
535 // If set, all packets will be received.
536 //
537 #define PXE_STATFLAGS_RECEIVE_FILTER_PROMISCUOUS 0x0008
538
539 //
540 // If set, all multicast packets will be received.
541 //
542 #define PXE_STATFLAGS_RECEIVE_FILTER_ALL_MULTICAST 0x0010
543
544 //
545 // //////////////////////////////////////
546 // UNDI Station Address
547 //
548 // No additional StatFlags
549
550 ////////////////////////////////////////
551 // UNDI Statistics
552 //
553 // No additional StatFlags
554
555 ////////////////////////////////////////
556 // UNDI MCast IP to MAC
557 //
558 // No additional StatFlags
559
560 ////////////////////////////////////////
561 // UNDI NvData
562 //
563 // No additional StatFlags
564
565
566 ////////////////////////////////////////
567 // UNDI Get Status
568 //
569 //
570 // Use to determine if an interrupt has occurred.
571 //
572 #define PXE_STATFLAGS_GET_STATUS_INTERRUPT_MASK 0x000F
573 #define PXE_STATFLAGS_GET_STATUS_NO_INTERRUPTS 0x0000
574
575 //
576 // If set, at least one receive interrupt occurred.
577 //
578 #define PXE_STATFLAGS_GET_STATUS_RECEIVE 0x0001
579
580 //
581 // If set, at least one transmit interrupt occurred.
582 //
583 #define PXE_STATFLAGS_GET_STATUS_TRANSMIT 0x0002
584
585 //
586 // If set, at least one command interrupt occurred.
587 //
588 #define PXE_STATFLAGS_GET_STATUS_COMMAND 0x0004
589
590 //
591 // If set, at least one software interrupt occurred.
592 //
593 #define PXE_STATFLAGS_GET_STATUS_SOFTWARE 0x0008
594
595 //
596 // This flag is set if the transmitted buffer queue is empty. This flag
597 // will be set if all transmitted buffer addresses get written into the DB.
598 //
599 #define PXE_STATFLAGS_GET_STATUS_TXBUF_QUEUE_EMPTY 0x0010
600
601 //
602 // This flag is set if no transmitted buffer addresses were written
603 // into the DB. (This could be because DBsize was too small.)
604 //
605 #define PXE_STATFLAGS_GET_STATUS_NO_TXBUFS_WRITTEN 0x0020
606
607 //
608 // //////////////////////////////////////
609 // UNDI Fill Header
610 //
611 // No additional StatFlags
612
613 ////////////////////////////////////////
614 // UNDI Transmit
615 //
616 // No additional StatFlags.
617
618 ////////////////////////////////////////
619 // UNDI Receive
620 //
621 // No additional StatFlags.
622 //
623 typedef UINT16 PXE_STATCODE;
624
625 #define PXE_STATCODE_INITIALIZE 0x0000
626
627 //
628 // //////////////////////////////////////
629 // Common StatCodes returned by all UNDI commands, UNDI protocol functions
630 // and BC protocol functions.
631 //
632 #define PXE_STATCODE_SUCCESS 0x0000
633
634 #define PXE_STATCODE_INVALID_CDB 0x0001
635 #define PXE_STATCODE_INVALID_CPB 0x0002
636 #define PXE_STATCODE_BUSY 0x0003
637 #define PXE_STATCODE_QUEUE_FULL 0x0004
638 #define PXE_STATCODE_ALREADY_STARTED 0x0005
639 #define PXE_STATCODE_NOT_STARTED 0x0006
640 #define PXE_STATCODE_NOT_SHUTDOWN 0x0007
641 #define PXE_STATCODE_ALREADY_INITIALIZED 0x0008
642 #define PXE_STATCODE_NOT_INITIALIZED 0x0009
643 #define PXE_STATCODE_DEVICE_FAILURE 0x000A
644 #define PXE_STATCODE_NVDATA_FAILURE 0x000B
645 #define PXE_STATCODE_UNSUPPORTED 0x000C
646 #define PXE_STATCODE_BUFFER_FULL 0x000D
647 #define PXE_STATCODE_INVALID_PARAMETER 0x000E
648 #define PXE_STATCODE_INVALID_UNDI 0x000F
649 #define PXE_STATCODE_IPV4_NOT_SUPPORTED 0x0010
650 #define PXE_STATCODE_IPV6_NOT_SUPPORTED 0x0011
651 #define PXE_STATCODE_NOT_ENOUGH_MEMORY 0x0012
652 #define PXE_STATCODE_NO_DATA 0x0013
653
654 typedef UINT16 PXE_IFNUM;
655
656 //
657 // This interface number must be passed to the S/W UNDI Start command.
658 //
659 #define PXE_IFNUM_START 0x0000
660
661 //
662 // This interface number is returned by the S/W UNDI Get State and
663 // Start commands if information in the CDB, CPB or DB is invalid.
664 //
665 #define PXE_IFNUM_INVALID 0x0000
666
667 typedef UINT16 PXE_CONTROL;
668
669 //
670 // Setting this flag directs the UNDI to queue this command for later
671 // execution if the UNDI is busy and it supports command queuing.
672 // If queuing is not supported, a PXE_STATCODE_INVALID_CONTROL error
673 // is returned. If the queue is full, a PXE_STATCODE_CDB_QUEUE_FULL
674 // error is returned.
675 //
676 #define PXE_CONTROL_QUEUE_IF_BUSY 0x0002
677
678 //
679 // These two bit values are used to determine if there are more UNDI
680 // CDB structures following this one. If the link bit is set, there
681 // must be a CDB structure following this one. Execution will start
682 // on the next CDB structure as soon as this one completes successfully.
683 // If an error is generated by this command, execution will stop.
684 //
685 #define PXE_CONTROL_LINK 0x0001
686 #define PXE_CONTROL_LAST_CDB_IN_LIST 0x0000
687
688 typedef UINT8 PXE_FRAME_TYPE;
689
690 #define PXE_FRAME_TYPE_NONE 0x00
691 #define PXE_FRAME_TYPE_UNICAST 0x01
692 #define PXE_FRAME_TYPE_BROADCAST 0x02
693 #define PXE_FRAME_TYPE_MULTICAST 0x03
694 #define PXE_FRAME_TYPE_PROMISCUOUS 0x04
695
696 typedef UINT32 PXE_IPV4;
697
698 typedef UINT32 PXE_IPV6[4];
699 #define PXE_MAC_LENGTH 32
700
701 typedef UINT8 PXE_MAC_ADDR[PXE_MAC_LENGTH];
702
703 typedef UINT8 PXE_IFTYPE;
704 typedef UINT16 PXE_MEDIA_PROTOCOL;
705
706 //
707 // This information is from the ARP section of RFC 1700.
708 //
709 // 1 Ethernet (10Mb) [JBP]
710 // 2 Experimental Ethernet (3Mb) [JBP]
711 // 3 Amateur Radio AX.25 [PXK]
712 // 4 Proteon ProNET Token Ring [JBP]
713 // 5 Chaos [GXP]
714 // 6 IEEE 802 Networks [JBP]
715 // 7 ARCNET [JBP]
716 // 8 Hyperchannel [JBP]
717 // 9 Lanstar [TU]
718 // 10 Autonet Short Address [MXB1]
719 // 11 LocalTalk [JKR1]
720 // 12 LocalNet (IBM* PCNet or SYTEK* LocalNET) [JXM]
721 // 13 Ultra link [RXD2]
722 // 14 SMDS [GXC1]
723 // 15 Frame Relay [AGM]
724 // 16 Asynchronous Transmission Mode (ATM) [JXB2]
725 // 17 HDLC [JBP]
726 // 18 Fibre Channel [Yakov Rekhter]
727 // 19 Asynchronous Transmission Mode (ATM) [Mark Laubach]
728 // 20 Serial Line [JBP]
729 // 21 Asynchronous Transmission Mode (ATM) [MXB1]
730 //
731 // * Other names and brands may be claimed as the property of others.
732 //
733 #define PXE_IFTYPE_ETHERNET 0x01
734 #define PXE_IFTYPE_TOKENRING 0x04
735 #define PXE_IFTYPE_FIBRE_CHANNEL 0x12
736
737 typedef struct s_pxe_hw_undi {
738 UINT32 Signature; // PXE_ROMID_SIGNATURE
739 UINT8 Len; // sizeof(PXE_HW_UNDI)
740 UINT8 Fudge; // makes 8-bit cksum equal zero
741 UINT8 Rev; // PXE_ROMID_REV
742 UINT8 IFcnt; // physical connector count
743 UINT8 MajorVer; // PXE_ROMID_MAJORVER
744 UINT8 MinorVer; // PXE_ROMID_MINORVER
745 UINT16 reserved; // zero, not used
746 UINT32 Implementation; // implementation flags
747 // reserved // vendor use
748 // UINT32 Status; // status port
749 // UINT32 Command; // command port
750 // UINT64 CDBaddr; // CDB address port
751 //
752 } PXE_HW_UNDI;
753
754 //
755 // Status port bit definitions
756 //
757 //
758 // UNDI operation state
759 //
760 #define PXE_HWSTAT_STATE_MASK 0xC0000000
761 #define PXE_HWSTAT_BUSY 0xC0000000
762 #define PXE_HWSTAT_INITIALIZED 0x80000000
763 #define PXE_HWSTAT_STARTED 0x40000000
764 #define PXE_HWSTAT_STOPPED 0x00000000
765
766 //
767 // If set, last command failed
768 //
769 #define PXE_HWSTAT_COMMAND_FAILED 0x20000000
770
771 //
772 // If set, identifies enabled receive filters
773 //
774 #define PXE_HWSTAT_PROMISCUOUS_MULTICAST_RX_ENABLED 0x00001000
775 #define PXE_HWSTAT_PROMISCUOUS_RX_ENABLED 0x00000800
776 #define PXE_HWSTAT_BROADCAST_RX_ENABLED 0x00000400
777 #define PXE_HWSTAT_MULTICAST_RX_ENABLED 0x00000200
778 #define PXE_HWSTAT_UNICAST_RX_ENABLED 0x00000100
779
780 //
781 // If set, identifies enabled external interrupts
782 //
783 #define PXE_HWSTAT_SOFTWARE_INT_ENABLED 0x00000080
784 #define PXE_HWSTAT_TX_COMPLETE_INT_ENABLED 0x00000040
785 #define PXE_HWSTAT_PACKET_RX_INT_ENABLED 0x00000020
786 #define PXE_HWSTAT_CMD_COMPLETE_INT_ENABLED 0x00000010
787
788 //
789 // If set, identifies pending interrupts
790 //
791 #define PXE_HWSTAT_SOFTWARE_INT_PENDING 0x00000008
792 #define PXE_HWSTAT_TX_COMPLETE_INT_PENDING 0x00000004
793 #define PXE_HWSTAT_PACKET_RX_INT_PENDING 0x00000002
794 #define PXE_HWSTAT_CMD_COMPLETE_INT_PENDING 0x00000001
795
796 //
797 // Command port definitions
798 //
799 //
800 // If set, CDB identified in CDBaddr port is given to UNDI.
801 // If not set, other bits in this word will be processed.
802 //
803 #define PXE_HWCMD_ISSUE_COMMAND 0x80000000
804 #define PXE_HWCMD_INTS_AND_FILTS 0x00000000
805
806 //
807 // Use these to enable/disable receive filters.
808 //
809 #define PXE_HWCMD_PROMISCUOUS_MULTICAST_RX_ENABLE 0x00001000
810 #define PXE_HWCMD_PROMISCUOUS_RX_ENABLE 0x00000800
811 #define PXE_HWCMD_BROADCAST_RX_ENABLE 0x00000400
812 #define PXE_HWCMD_MULTICAST_RX_ENABLE 0x00000200
813 #define PXE_HWCMD_UNICAST_RX_ENABLE 0x00000100
814
815 //
816 // Use these to enable/disable external interrupts
817 //
818 #define PXE_HWCMD_SOFTWARE_INT_ENABLE 0x00000080
819 #define PXE_HWCMD_TX_COMPLETE_INT_ENABLE 0x00000040
820 #define PXE_HWCMD_PACKET_RX_INT_ENABLE 0x00000020
821 #define PXE_HWCMD_CMD_COMPLETE_INT_ENABLE 0x00000010
822
823 //
824 // Use these to clear pending external interrupts
825 //
826 #define PXE_HWCMD_CLEAR_SOFTWARE_INT 0x00000008
827 #define PXE_HWCMD_CLEAR_TX_COMPLETE_INT 0x00000004
828 #define PXE_HWCMD_CLEAR_PACKET_RX_INT 0x00000002
829 #define PXE_HWCMD_CLEAR_CMD_COMPLETE_INT 0x00000001
830
831 typedef struct s_pxe_sw_undi {
832 UINT32 Signature; // PXE_ROMID_SIGNATURE
833 UINT8 Len; // sizeof(PXE_SW_UNDI)
834 UINT8 Fudge; // makes 8-bit cksum zero
835 UINT8 Rev; // PXE_ROMID_REV
836 UINT8 IFcnt; // physical connector count
837 UINT8 MajorVer; // PXE_ROMID_MAJORVER
838 UINT8 MinorVer; // PXE_ROMID_MINORVER
839 UINT16 reserved1; // zero, not used
840 UINT32 Implementation; // Implementation flags
841 UINT64 EntryPoint; // API entry point
842 UINT8 reserved2[3]; // zero, not used
843 UINT8 BusCnt; // number of bustypes supported
844 UINT32 BusType[1]; // list of supported bustypes
845 } PXE_SW_UNDI;
846
847 typedef union u_pxe_undi {
848 PXE_HW_UNDI hw;
849 PXE_SW_UNDI sw;
850 } PXE_UNDI;
851
852 //
853 // Signature of !PXE structure
854 //
855 #define PXE_ROMID_SIGNATURE PXE_BUSTYPE ('!', 'P', 'X', 'E')
856
857 //
858 // !PXE structure format revision
859 //
860 #define PXE_ROMID_REV 0x02
861
862 //
863 // UNDI command interface revision. These are the values that get sent
864 // in option 94 (Client Network Interface Identifier) in the DHCP Discover
865 // and PXE Boot Server Request packets.
866 //
867 #define PXE_ROMID_MAJORVER 0x03
868 #define PXE_ROMID_MINORVER 0x00
869 #define PXE_ROMID_MINORVER_31 0x10
870
871 //
872 // Implementation flags
873 //
874 #define PXE_ROMID_IMP_HW_UNDI 0x80000000
875 #define PXE_ROMID_IMP_SW_VIRT_ADDR 0x40000000
876 #define PXE_ROMID_IMP_64BIT_DEVICE 0x00010000
877 #define PXE_ROMID_IMP_FRAG_SUPPORTED 0x00008000
878 #define PXE_ROMID_IMP_CMD_LINK_SUPPORTED 0x00004000
879 #define PXE_ROMID_IMP_CMD_QUEUE_SUPPORTED 0x00002000
880 #define PXE_ROMID_IMP_MULTI_FRAME_SUPPORTED 0x00001000
881 #define PXE_ROMID_IMP_NVDATA_SUPPORT_MASK 0x00000C00
882 #define PXE_ROMID_IMP_NVDATA_BULK_WRITABLE 0x00000C00
883 #define PXE_ROMID_IMP_NVDATA_SPARSE_WRITABLE 0x00000800
884 #define PXE_ROMID_IMP_NVDATA_READ_ONLY 0x00000400
885 #define PXE_ROMID_IMP_NVDATA_NOT_AVAILABLE 0x00000000
886 #define PXE_ROMID_IMP_STATISTICS_SUPPORTED 0x00000200
887 #define PXE_ROMID_IMP_STATION_ADDR_SETTABLE 0x00000100
888 #define PXE_ROMID_IMP_PROMISCUOUS_MULTICAST_RX_SUPPORTED 0x00000080
889 #define PXE_ROMID_IMP_PROMISCUOUS_RX_SUPPORTED 0x00000040
890 #define PXE_ROMID_IMP_BROADCAST_RX_SUPPORTED 0x00000020
891 #define PXE_ROMID_IMP_FILTERED_MULTICAST_RX_SUPPORTED 0x00000010
892 #define PXE_ROMID_IMP_SOFTWARE_INT_SUPPORTED 0x00000008
893 #define PXE_ROMID_IMP_TX_COMPLETE_INT_SUPPORTED 0x00000004
894 #define PXE_ROMID_IMP_PACKET_RX_INT_SUPPORTED 0x00000002
895 #define PXE_ROMID_IMP_CMD_COMPLETE_INT_SUPPORTED 0x00000001
896
897 typedef struct s_pxe_cdb {
898 PXE_OPCODE OpCode;
899 PXE_OPFLAGS OpFlags;
900 UINT16 CPBsize;
901 UINT16 DBsize;
902 UINT64 CPBaddr;
903 UINT64 DBaddr;
904 PXE_STATCODE StatCode;
905 PXE_STATFLAGS StatFlags;
906 UINT16 IFnum;
907 PXE_CONTROL Control;
908 } PXE_CDB;
909
910 typedef union u_pxe_ip_addr {
911 PXE_IPV6 IPv6;
912 PXE_IPV4 IPv4;
913 } PXE_IP_ADDR;
914
915 typedef union pxe_device {
916 //
917 // PCI and PC Card NICs are both identified using bus, device
918 // and function numbers. For PC Card, this may require PC
919 // Card services to be loaded in the BIOS or preboot
920 // environment.
921 //
922 struct {
923 //
924 // See S/W UNDI ROMID structure definition for PCI and
925 // PCC BusType definitions.
926 //
927 UINT32 BusType;
928
929 //
930 // Bus, device & function numbers that locate this device.
931 //
932 UINT16 Bus;
933 UINT8 Device;
934 UINT8 Function;
935 }
936 PCI, PCC;
937
938 //
939 // %%TBD - More information is needed about enumerating
940 // USB and 1394 devices.
941 //
942 struct {
943 UINT32 BusType;
944 UINT32 tdb;
945 }
946 USB, _1394;
947 } PXE_DEVICE;
948
949 //
950 // cpb and db definitions
951 //
952 #define MAX_PCI_CONFIG_LEN 64 // # of dwords
953 #define MAX_EEPROM_LEN 128 // #of dwords
954 #define MAX_XMIT_BUFFERS 32 // recycling Q length for xmit_done
955 #define MAX_MCAST_ADDRESS_CNT 8
956
957 typedef struct s_pxe_cpb_start {
958 //
959 // PXE_VOID Delay(UINTN microseconds);
960 //
961 // UNDI will never request a delay smaller than 10 microseconds
962 // and will always request delays in increments of 10 microseconds.
963 // The Delay() CallBack routine must delay between n and n + 10
964 // microseconds before returning control to the UNDI.
965 //
966 // This field cannot be set to zero.
967 //
968 UINT64 Delay;
969
970 //
971 // PXE_VOID Block(UINT32 enable);
972 //
973 // UNDI may need to block multi-threaded/multi-processor access to
974 // critical code sections when programming or accessing the network
975 // device. To this end, a blocking service is needed by the UNDI.
976 // When UNDI needs a block, it will call Block() passing a non-zero
977 // value. When UNDI no longer needs a block, it will call Block()
978 // with a zero value. When called, if the Block() is already enabled,
979 // do not return control to the UNDI until the previous Block() is
980 // disabled.
981 //
982 // This field cannot be set to zero.
983 //
984 UINT64 Block;
985
986 //
987 // PXE_VOID Virt2Phys(UINT64 virtual, UINT64 physical_ptr);
988 //
989 // UNDI will pass the virtual address of a buffer and the virtual
990 // address of a 64-bit physical buffer. Convert the virtual address
991 // to a physical address and write the result to the physical address
992 // buffer. If virtual and physical addresses are the same, just
993 // copy the virtual address to the physical address buffer.
994 //
995 // This field can be set to zero if virtual and physical addresses
996 // are equal.
997 //
998 UINT64 Virt2Phys;
999 //
1000 // PXE_VOID Mem_IO(UINT8 read_write, UINT8 len, UINT64 port,
1001 // UINT64 buf_addr);
1002 //
1003 // UNDI will read or write the device io space using this call back
1004 // function. It passes the number of bytes as the len parameter and it
1005 // will be either 1,2,4 or 8.
1006 //
1007 // This field can not be set to zero.
1008 //
1009 UINT64 Mem_IO;
1010 } PXE_CPB_START;
1011
1012 typedef struct s_pxe_cpb_start_31 {
1013 //
1014 // PXE_VOID Delay(UINT64 UnqId, UINTN microseconds);
1015 //
1016 // UNDI will never request a delay smaller than 10 microseconds
1017 // and will always request delays in increments of 10 microseconds.
1018 // The Delay() CallBack routine must delay between n and n + 10
1019 // microseconds before returning control to the UNDI.
1020 //
1021 // This field cannot be set to zero.
1022 //
1023 UINT64 Delay;
1024
1025 //
1026 // PXE_VOID Block(UINT64 unq_id, UINT32 enable);
1027 //
1028 // UNDI may need to block multi-threaded/multi-processor access to
1029 // critical code sections when programming or accessing the network
1030 // device. To this end, a blocking service is needed by the UNDI.
1031 // When UNDI needs a block, it will call Block() passing a non-zero
1032 // value. When UNDI no longer needs a block, it will call Block()
1033 // with a zero value. When called, if the Block() is already enabled,
1034 // do not return control to the UNDI until the previous Block() is
1035 // disabled.
1036 //
1037 // This field cannot be set to zero.
1038 //
1039 UINT64 Block;
1040
1041 //
1042 // PXE_VOID Virt2Phys(UINT64 UnqId, UINT64 virtual, UINT64 physical_ptr);
1043 //
1044 // UNDI will pass the virtual address of a buffer and the virtual
1045 // address of a 64-bit physical buffer. Convert the virtual address
1046 // to a physical address and write the result to the physical address
1047 // buffer. If virtual and physical addresses are the same, just
1048 // copy the virtual address to the physical address buffer.
1049 //
1050 // This field can be set to zero if virtual and physical addresses
1051 // are equal.
1052 //
1053 UINT64 Virt2Phys;
1054 //
1055 // PXE_VOID Mem_IO(UINT64 UnqId, UINT8 read_write, UINT8 len, UINT64 port,
1056 // UINT64 buf_addr);
1057 //
1058 // UNDI will read or write the device io space using this call back
1059 // function. It passes the number of bytes as the len parameter and it
1060 // will be either 1,2,4 or 8.
1061 //
1062 // This field can not be set to zero.
1063 //
1064 UINT64 Mem_IO;
1065 //
1066 // PXE_VOID Map_Mem(UINT64 unq_id, UINT64 virtual_addr, UINT32 size,
1067 // UINT32 Direction, UINT64 mapped_addr);
1068 //
1069 // UNDI will pass the virtual address of a buffer, direction of the data
1070 // flow from/to the mapped buffer (the constants are defined below)
1071 // and a place holder (pointer) for the mapped address.
1072 // This call will Map the given address to a physical DMA address and write
1073 // the result to the mapped_addr pointer. If there is no need to
1074 // map the given address to a lower address (i.e. the given address is
1075 // associated with a physical address that is already compatible to be
1076 // used with the DMA, it converts the given virtual address to it's
1077 // physical address and write that in the mapped address pointer.
1078 //
1079 // This field can be set to zero if there is no mapping service available
1080 //
1081 UINT64 Map_Mem;
1082
1083 //
1084 // PXE_VOID UnMap_Mem(UINT64 unq_id, UINT64 virtual_addr, UINT32 size,
1085 // UINT32 Direction, UINT64 mapped_addr);
1086 //
1087 // UNDI will pass the virtual and mapped addresses of a buffer
1088 // This call will un map the given address
1089 //
1090 // This field can be set to zero if there is no unmapping service available
1091 //
1092 UINT64 UnMap_Mem;
1093
1094 //
1095 // PXE_VOID Sync_Mem(UINT64 unq_id, UINT64 virtual,
1096 // UINT32 size, UINT32 Direction, UINT64 mapped_addr);
1097 //
1098 // UNDI will pass the virtual and mapped addresses of a buffer
1099 // This call will synchronize the contents of both the virtual and mapped
1100 // buffers for the given Direction.
1101 //
1102 // This field can be set to zero if there is no service available
1103 //
1104 UINT64 Sync_Mem;
1105
1106 //
1107 // protocol driver can provide anything for this Unique_ID, UNDI remembers
1108 // that as just a 64bit value assocaited to the interface specified by
1109 // the ifnum and gives it back as a parameter to all the call-back routines
1110 // when calling for that interface!
1111 //
1112 UINT64 Unique_ID;
1113 //
1114 } PXE_CPB_START_31;
1115
1116 #define TO_AND_FROM_DEVICE 0
1117 #define FROM_DEVICE 1
1118 #define TO_DEVICE 2
1119
1120 #define PXE_DELAY_MILLISECOND 1000
1121 #define PXE_DELAY_SECOND 1000000
1122 #define PXE_IO_READ 0
1123 #define PXE_IO_WRITE 1
1124 #define PXE_MEM_READ 2
1125 #define PXE_MEM_WRITE 4
1126
1127 typedef struct s_pxe_db_get_init_info {
1128 //
1129 // Minimum length of locked memory buffer that must be given to
1130 // the Initialize command. Giving UNDI more memory will generally
1131 // give better performance.
1132 //
1133 // If MemoryRequired is zero, the UNDI does not need and will not
1134 // use system memory to receive and transmit packets.
1135 //
1136 UINT32 MemoryRequired;
1137
1138 //
1139 // Maximum frame data length for Tx/Rx excluding the media header.
1140 //
1141 UINT32 FrameDataLen;
1142
1143 //
1144 // Supported link speeds are in units of mega bits. Common ethernet
1145 // values are 10, 100 and 1000. Unused LinkSpeeds[] entries are zero
1146 // filled.
1147 //
1148 UINT32 LinkSpeeds[4];
1149
1150 //
1151 // Number of non-volatile storage items.
1152 //
1153 UINT32 NvCount;
1154
1155 //
1156 // Width of non-volatile storage item in bytes. 0, 1, 2 or 4
1157 //
1158 UINT16 NvWidth;
1159
1160 //
1161 // Media header length. This is the typical media header length for
1162 // this UNDI. This information is needed when allocating receive
1163 // and transmit buffers.
1164 //
1165 UINT16 MediaHeaderLen;
1166
1167 //
1168 // Number of bytes in the NIC hardware (MAC) address.
1169 //
1170 UINT16 HWaddrLen;
1171
1172 //
1173 // Maximum number of multicast MAC addresses in the multicast
1174 // MAC address filter list.
1175 //
1176 UINT16 MCastFilterCnt;
1177
1178 //
1179 // Default number and size of transmit and receive buffers that will
1180 // be allocated by the UNDI. If MemoryRequired is non-zero, this
1181 // allocation will come out of the memory buffer given to the Initialize
1182 // command. If MemoryRequired is zero, this allocation will come out of
1183 // memory on the NIC.
1184 //
1185 UINT16 TxBufCnt;
1186 UINT16 TxBufSize;
1187 UINT16 RxBufCnt;
1188 UINT16 RxBufSize;
1189
1190 //
1191 // Hardware interface types defined in the Assigned Numbers RFC
1192 // and used in DHCP and ARP packets.
1193 // See the PXE_IFTYPE typedef and PXE_IFTYPE_xxx macros.
1194 //
1195 UINT8 IFtype;
1196
1197 //
1198 // Supported duplex. See PXE_DUPLEX_xxxxx #defines below.
1199 //
1200 UINT8 Duplex;
1201
1202 //
1203 // Supported loopback options. See PXE_LOOPBACK_xxxxx #defines below.
1204 //
1205 UINT8 LoopBack;
1206 } PXE_DB_GET_INIT_INFO;
1207
1208 #define PXE_MAX_TXRX_UNIT_ETHER 1500
1209
1210 #define PXE_HWADDR_LEN_ETHER 0x0006
1211 #define PXE_MAC_HEADER_LEN_ETHER 0x000E
1212
1213 #define PXE_DUPLEX_ENABLE_FULL_SUPPORTED 1
1214 #define PXE_DUPLEX_FORCE_FULL_SUPPORTED 2
1215
1216 #define PXE_LOOPBACK_INTERNAL_SUPPORTED 1
1217 #define PXE_LOOPBACK_EXTERNAL_SUPPORTED 2
1218
1219 typedef struct s_pxe_pci_config_info {
1220 //
1221 // This is the flag field for the PXE_DB_GET_CONFIG_INFO union.
1222 // For PCI bus devices, this field is set to PXE_BUSTYPE_PCI.
1223 //
1224 UINT32 BusType;
1225
1226 //
1227 // This identifies the PCI network device that this UNDI interface
1228 // is bound to.
1229 //
1230 UINT16 Bus;
1231 UINT8 Device;
1232 UINT8 Function;
1233
1234 //
1235 // This is a copy of the PCI configuration space for this
1236 // network device.
1237 //
1238 union {
1239 UINT8 Byte[256];
1240 UINT16 Word[128];
1241 UINT32 Dword[64];
1242 } Config;
1243 } PXE_PCI_CONFIG_INFO;
1244
1245 typedef struct s_pxe_pcc_config_info {
1246 //
1247 // This is the flag field for the PXE_DB_GET_CONFIG_INFO union.
1248 // For PCC bus devices, this field is set to PXE_BUSTYPE_PCC.
1249 //
1250 UINT32 BusType;
1251
1252 //
1253 // This identifies the PCC network device that this UNDI interface
1254 // is bound to.
1255 //
1256 UINT16 Bus;
1257 UINT8 Device;
1258 UINT8 Function;
1259
1260 //
1261 // This is a copy of the PCC configuration space for this
1262 // network device.
1263 //
1264 union {
1265 UINT8 Byte[256];
1266 UINT16 Word[128];
1267 UINT32 Dword[64];
1268 } Config;
1269 } PXE_PCC_CONFIG_INFO;
1270
1271 typedef struct s_pxe_usb_config_info {
1272 UINT32 BusType;
1273 //
1274 // %%TBD What should we return here...
1275 //
1276 } PXE_USB_CONFIG_INFO;
1277
1278 typedef struct s_pxe_1394_config_info {
1279 UINT32 BusType;
1280 //
1281 // %%TBD What should we return here...
1282 //
1283 } PXE_1394_CONFIG_INFO;
1284
1285 typedef union u_pxe_db_get_config_info {
1286 PXE_PCI_CONFIG_INFO pci;
1287 PXE_PCC_CONFIG_INFO pcc;
1288 PXE_USB_CONFIG_INFO usb;
1289 PXE_1394_CONFIG_INFO _1394;
1290 } PXE_DB_GET_CONFIG_INFO;
1291
1292 typedef struct s_pxe_cpb_initialize {
1293 //
1294 // Address of first (lowest) byte of the memory buffer. This buffer must
1295 // be in contiguous physical memory and cannot be swapped out. The UNDI
1296 // will be using this for transmit and receive buffering.
1297 //
1298 UINT64 MemoryAddr;
1299
1300 //
1301 // MemoryLength must be greater than or equal to MemoryRequired
1302 // returned by the Get Init Info command.
1303 //
1304 UINT32 MemoryLength;
1305
1306 //
1307 // Desired link speed in Mbit/sec. Common ethernet values are 10, 100
1308 // and 1000. Setting a value of zero will auto-detect and/or use the
1309 // default link speed (operation depends on UNDI/NIC functionality).
1310 //
1311 UINT32 LinkSpeed;
1312
1313 //
1314 // Suggested number and size of receive and transmit buffers to
1315 // allocate. If MemoryAddr and MemoryLength are non-zero, this
1316 // allocation comes out of the supplied memory buffer. If MemoryAddr
1317 // and MemoryLength are zero, this allocation comes out of memory
1318 // on the NIC.
1319 //
1320 // If these fields are set to zero, the UNDI will allocate buffer
1321 // counts and sizes as it sees fit.
1322 //
1323 UINT16 TxBufCnt;
1324 UINT16 TxBufSize;
1325 UINT16 RxBufCnt;
1326 UINT16 RxBufSize;
1327
1328 //
1329 // The following configuration parameters are optional and must be zero
1330 // to use the default values.
1331 //
1332 UINT8 Duplex;
1333
1334 UINT8 LoopBack;
1335 } PXE_CPB_INITIALIZE;
1336
1337 #define PXE_DUPLEX_DEFAULT 0x00
1338 #define PXE_FORCE_FULL_DUPLEX 0x01
1339 #define PXE_ENABLE_FULL_DUPLEX 0x02
1340 #define PXE_FORCE_HALF_DUPLEX 0x04
1341 #define PXE_DISABLE_FULL_DUPLEX 0x08
1342
1343 #define LOOPBACK_NORMAL 0
1344 #define LOOPBACK_INTERNAL 1
1345 #define LOOPBACK_EXTERNAL 2
1346
1347 typedef struct s_pxe_db_initialize {
1348 //
1349 // Actual amount of memory used from the supplied memory buffer. This
1350 // may be less that the amount of memory suppllied and may be zero if
1351 // the UNDI and network device do not use external memory buffers.
1352 //
1353 // Memory used by the UNDI and network device is allocated from the
1354 // lowest memory buffer address.
1355 //
1356 UINT32 MemoryUsed;
1357
1358 //
1359 // Actual number and size of receive and transmit buffers that were
1360 // allocated.
1361 //
1362 UINT16 TxBufCnt;
1363 UINT16 TxBufSize;
1364 UINT16 RxBufCnt;
1365 UINT16 RxBufSize;
1366 } PXE_DB_INITIALIZE;
1367
1368 typedef struct s_pxe_cpb_receive_filters {
1369 //
1370 // List of multicast MAC addresses. This list, if present, will
1371 // replace the existing multicast MAC address filter list.
1372 //
1373 PXE_MAC_ADDR MCastList[MAX_MCAST_ADDRESS_CNT];
1374 } PXE_CPB_RECEIVE_FILTERS;
1375
1376 typedef struct s_pxe_db_receive_filters {
1377 //
1378 // Filtered multicast MAC address list.
1379 //
1380 PXE_MAC_ADDR MCastList[MAX_MCAST_ADDRESS_CNT];
1381 } PXE_DB_RECEIVE_FILTERS;
1382
1383 typedef struct s_pxe_cpb_station_address {
1384 //
1385 // If supplied and supported, the current station MAC address
1386 // will be changed.
1387 //
1388 PXE_MAC_ADDR StationAddr;
1389 } PXE_CPB_STATION_ADDRESS;
1390
1391 typedef struct s_pxe_dpb_station_address {
1392 //
1393 // Current station MAC address.
1394 //
1395 PXE_MAC_ADDR StationAddr;
1396
1397 //
1398 // Station broadcast MAC address.
1399 //
1400 PXE_MAC_ADDR BroadcastAddr;
1401
1402 //
1403 // Permanent station MAC address.
1404 //
1405 PXE_MAC_ADDR PermanentAddr;
1406 } PXE_DB_STATION_ADDRESS;
1407
1408 typedef struct s_pxe_db_statistics {
1409 //
1410 // Bit field identifying what statistic data is collected by the
1411 // UNDI/NIC.
1412 // If bit 0x00 is set, Data[0x00] is collected.
1413 // If bit 0x01 is set, Data[0x01] is collected.
1414 // If bit 0x20 is set, Data[0x20] is collected.
1415 // If bit 0x21 is set, Data[0x21] is collected.
1416 // Etc.
1417 //
1418 UINT64 Supported;
1419
1420 //
1421 // Statistic data.
1422 //
1423 UINT64 Data[64];
1424 } PXE_DB_STATISTICS;
1425
1426 //
1427 // Total number of frames received. Includes frames with errors and
1428 // dropped frames.
1429 //
1430 #define PXE_STATISTICS_RX_TOTAL_FRAMES 0x00
1431
1432 //
1433 // Number of valid frames received and copied into receive buffers.
1434 //
1435 #define PXE_STATISTICS_RX_GOOD_FRAMES 0x01
1436
1437 //
1438 // Number of frames below the minimum length for the media.
1439 // This would be <64 for ethernet.
1440 //
1441 #define PXE_STATISTICS_RX_UNDERSIZE_FRAMES 0x02
1442
1443 //
1444 // Number of frames longer than the maxminum length for the
1445 // media. This would be >1500 for ethernet.
1446 //
1447 #define PXE_STATISTICS_RX_OVERSIZE_FRAMES 0x03
1448
1449 //
1450 // Valid frames that were dropped because receive buffers were full.
1451 //
1452 #define PXE_STATISTICS_RX_DROPPED_FRAMES 0x04
1453
1454 //
1455 // Number of valid unicast frames received and not dropped.
1456 //
1457 #define PXE_STATISTICS_RX_UNICAST_FRAMES 0x05
1458
1459 //
1460 // Number of valid broadcast frames received and not dropped.
1461 //
1462 #define PXE_STATISTICS_RX_BROADCAST_FRAMES 0x06
1463
1464 //
1465 // Number of valid mutlicast frames received and not dropped.
1466 //
1467 #define PXE_STATISTICS_RX_MULTICAST_FRAMES 0x07
1468
1469 //
1470 // Number of frames w/ CRC or alignment errors.
1471 //
1472 #define PXE_STATISTICS_RX_CRC_ERROR_FRAMES 0x08
1473
1474 //
1475 // Total number of bytes received. Includes frames with errors
1476 // and dropped frames.
1477 //
1478 #define PXE_STATISTICS_RX_TOTAL_BYTES 0x09
1479
1480 //
1481 // Transmit statistics.
1482 //
1483 #define PXE_STATISTICS_TX_TOTAL_FRAMES 0x0A
1484 #define PXE_STATISTICS_TX_GOOD_FRAMES 0x0B
1485 #define PXE_STATISTICS_TX_UNDERSIZE_FRAMES 0x0C
1486 #define PXE_STATISTICS_TX_OVERSIZE_FRAMES 0x0D
1487 #define PXE_STATISTICS_TX_DROPPED_FRAMES 0x0E
1488 #define PXE_STATISTICS_TX_UNICAST_FRAMES 0x0F
1489 #define PXE_STATISTICS_TX_BROADCAST_FRAMES 0x10
1490 #define PXE_STATISTICS_TX_MULTICAST_FRAMES 0x11
1491 #define PXE_STATISTICS_TX_CRC_ERROR_FRAMES 0x12
1492 #define PXE_STATISTICS_TX_TOTAL_BYTES 0x13
1493
1494 //
1495 // Number of collisions detection on this subnet.
1496 //
1497 #define PXE_STATISTICS_COLLISIONS 0x14
1498
1499 //
1500 // Number of frames destined for unsupported protocol.
1501 //
1502 #define PXE_STATISTICS_UNSUPPORTED_PROTOCOL 0x15
1503
1504 typedef struct s_pxe_cpb_mcast_ip_to_mac {
1505 //
1506 // Multicast IP address to be converted to multicast MAC address.
1507 //
1508 PXE_IP_ADDR IP;
1509 } PXE_CPB_MCAST_IP_TO_MAC;
1510
1511 typedef struct s_pxe_db_mcast_ip_to_mac {
1512 //
1513 // Multicast MAC address.
1514 //
1515 PXE_MAC_ADDR MAC;
1516 } PXE_DB_MCAST_IP_TO_MAC;
1517
1518 typedef struct s_pxe_cpb_nvdata_sparse {
1519 //
1520 // NvData item list. Only items in this list will be updated.
1521 //
1522 struct {
1523 //
1524 // Non-volatile storage address to be changed.
1525 //
1526 UINT32 Addr;
1527
1528 //
1529 // Data item to write into above storage address.
1530 //
1531 union {
1532 UINT8 Byte;
1533 UINT16 Word;
1534 UINT32 Dword;
1535 } Data;
1536 } Item[MAX_EEPROM_LEN];
1537 }
1538 PXE_CPB_NVDATA_SPARSE;
1539
1540 //
1541 // When using bulk update, the size of the CPB structure must be
1542 // the same size as the non-volatile NIC storage.
1543 //
1544 typedef union u_pxe_cpb_nvdata_bulk {
1545 //
1546 // Array of byte-wide data items.
1547 //
1548 UINT8 Byte[MAX_EEPROM_LEN << 2];
1549
1550 //
1551 // Array of word-wide data items.
1552 //
1553 UINT16 Word[MAX_EEPROM_LEN << 1];
1554
1555 //
1556 // Array of dword-wide data items.
1557 //
1558 UINT32 Dword[MAX_EEPROM_LEN];
1559 } PXE_CPB_NVDATA_BULK;
1560
1561 typedef struct s_pxe_db_nvdata {
1562 //
1563 // Arrays of data items from non-volatile storage.
1564 //
1565 union {
1566 //
1567 // Array of byte-wide data items.
1568 //
1569 UINT8 Byte[MAX_EEPROM_LEN << 2];
1570
1571 //
1572 // Array of word-wide data items.
1573 //
1574 UINT16 Word[MAX_EEPROM_LEN << 1];
1575
1576 //
1577 // Array of dword-wide data items.
1578 //
1579 UINT32 Dword[MAX_EEPROM_LEN];
1580 } Data;
1581 } PXE_DB_NVDATA;
1582
1583 typedef struct s_pxe_db_get_status {
1584 //
1585 // Length of next receive frame (header + data). If this is zero,
1586 // there is no next receive frame available.
1587 //
1588 UINT32 RxFrameLen;
1589
1590 //
1591 // Reserved, set to zero.
1592 //
1593 UINT32 reserved;
1594
1595 //
1596 // Addresses of transmitted buffers that need to be recycled.
1597 //
1598 UINT64 TxBuffer[MAX_XMIT_BUFFERS];
1599 } PXE_DB_GET_STATUS;
1600
1601 typedef struct s_pxe_cpb_fill_header {
1602 //
1603 // Source and destination MAC addresses. These will be copied into
1604 // the media header without doing byte swapping.
1605 //
1606 PXE_MAC_ADDR SrcAddr;
1607 PXE_MAC_ADDR DestAddr;
1608
1609 //
1610 // Address of first byte of media header. The first byte of packet data
1611 // follows the last byte of the media header.
1612 //
1613 UINT64 MediaHeader;
1614
1615 //
1616 // Length of packet data in bytes (not including the media header).
1617 //
1618 UINT32 PacketLen;
1619
1620 //
1621 // Protocol type. This will be copied into the media header without
1622 // doing byte swapping. Protocol type numbers can be obtained from
1623 // the Assigned Numbers RFC 1700.
1624 //
1625 UINT16 Protocol;
1626
1627 //
1628 // Length of the media header in bytes.
1629 //
1630 UINT16 MediaHeaderLen;
1631 } PXE_CPB_FILL_HEADER;
1632
1633 #define PXE_PROTOCOL_ETHERNET_IP 0x0800
1634 #define PXE_PROTOCOL_ETHERNET_ARP 0x0806
1635 #define MAX_XMIT_FRAGMENTS 16
1636
1637 typedef struct s_pxe_cpb_fill_header_fragmented {
1638 //
1639 // Source and destination MAC addresses. These will be copied into
1640 // the media header without doing byte swapping.
1641 //
1642 PXE_MAC_ADDR SrcAddr;
1643 PXE_MAC_ADDR DestAddr;
1644
1645 //
1646 // Length of packet data in bytes (not including the media header).
1647 //
1648 UINT32 PacketLen;
1649
1650 //
1651 // Protocol type. This will be copied into the media header without
1652 // doing byte swapping. Protocol type numbers can be obtained from
1653 // the Assigned Numbers RFC 1700.
1654 //
1655 PXE_MEDIA_PROTOCOL Protocol;
1656
1657 //
1658 // Length of the media header in bytes.
1659 //
1660 UINT16 MediaHeaderLen;
1661
1662 //
1663 // Number of packet fragment descriptors.
1664 //
1665 UINT16 FragCnt;
1666
1667 //
1668 // Reserved, must be set to zero.
1669 //
1670 UINT16 reserved;
1671
1672 //
1673 // Array of packet fragment descriptors. The first byte of the media
1674 // header is the first byte of the first fragment.
1675 //
1676 struct {
1677 //
1678 // Address of this packet fragment.
1679 //
1680 UINT64 FragAddr;
1681
1682 //
1683 // Length of this packet fragment.
1684 //
1685 UINT32 FragLen;
1686
1687 //
1688 // Reserved, must be set to zero.
1689 //
1690 UINT32 reserved;
1691 } FragDesc[MAX_XMIT_FRAGMENTS];
1692 }
1693 PXE_CPB_FILL_HEADER_FRAGMENTED;
1694
1695 typedef struct s_pxe_cpb_transmit {
1696 //
1697 // Address of first byte of frame buffer. This is also the first byte
1698 // of the media header.
1699 //
1700 UINT64 FrameAddr;
1701
1702 //
1703 // Length of the data portion of the frame buffer in bytes. Do not
1704 // include the length of the media header.
1705 //
1706 UINT32 DataLen;
1707
1708 //
1709 // Length of the media header in bytes.
1710 //
1711 UINT16 MediaheaderLen;
1712
1713 //
1714 // Reserved, must be zero.
1715 //
1716 UINT16 reserved;
1717 } PXE_CPB_TRANSMIT;
1718
1719 typedef struct s_pxe_cpb_transmit_fragments {
1720 //
1721 // Length of packet data in bytes (not including the media header).
1722 //
1723 UINT32 FrameLen;
1724
1725 //
1726 // Length of the media header in bytes.
1727 //
1728 UINT16 MediaheaderLen;
1729
1730 //
1731 // Number of packet fragment descriptors.
1732 //
1733 UINT16 FragCnt;
1734
1735 //
1736 // Array of frame fragment descriptors. The first byte of the first
1737 // fragment is also the first byte of the media header.
1738 //
1739 struct {
1740 //
1741 // Address of this frame fragment.
1742 //
1743 UINT64 FragAddr;
1744
1745 //
1746 // Length of this frame fragment.
1747 //
1748 UINT32 FragLen;
1749
1750 //
1751 // Reserved, must be set to zero.
1752 //
1753 UINT32 reserved;
1754 } FragDesc[MAX_XMIT_FRAGMENTS];
1755 }
1756 PXE_CPB_TRANSMIT_FRAGMENTS;
1757
1758 typedef struct s_pxe_cpb_receive {
1759 //
1760 // Address of first byte of receive buffer. This is also the first byte
1761 // of the frame header.
1762 //
1763 UINT64 BufferAddr;
1764
1765 //
1766 // Length of receive buffer. This must be large enough to hold the
1767 // received frame (media header + data). If the length of smaller than
1768 // the received frame, data will be lost.
1769 //
1770 UINT32 BufferLen;
1771
1772 //
1773 // Reserved, must be set to zero.
1774 //
1775 UINT32 reserved;
1776 } PXE_CPB_RECEIVE;
1777
1778 typedef struct s_pxe_db_receive {
1779 //
1780 // Source and destination MAC addresses from media header.
1781 //
1782 PXE_MAC_ADDR SrcAddr;
1783 PXE_MAC_ADDR DestAddr;
1784
1785 //
1786 // Length of received frame. May be larger than receive buffer size.
1787 // The receive buffer will not be overwritten. This is how to tell
1788 // if data was lost because the receive buffer was too small.
1789 //
1790 UINT32 FrameLen;
1791
1792 //
1793 // Protocol type from media header.
1794 //
1795 PXE_MEDIA_PROTOCOL Protocol;
1796
1797 //
1798 // Length of media header in received frame.
1799 //
1800 UINT16 MediaHeaderLen;
1801
1802 //
1803 // Type of receive frame.
1804 //
1805 PXE_FRAME_TYPE Type;
1806
1807 //
1808 // Reserved, must be zero.
1809 //
1810 UINT8 reserved[7];
1811
1812 } PXE_DB_RECEIVE;
1813
1814 #pragma pack()
1815
1816 #endif
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