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3eb9473e | 1 | /*++\r |
2 | \r | |
3 | Copyright (c) 2004, Intel Corporation \r | |
4 | All rights reserved. This program and the accompanying materials \r | |
5 | are licensed and made available under the terms and conditions of the BSD License \r | |
6 | which accompanies this distribution. The full text of the license may be found at \r | |
7 | http://opensource.org/licenses/bsd-license.php \r | |
8 | \r | |
9 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
10 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
11 | \r | |
12 | Module Name:\r | |
13 | \r | |
14 | EfiRegTableLib.h\r | |
15 | \r | |
16 | Abstract: \r | |
17 | \r | |
18 | Definitions and macros for building register tables for chipset \r | |
19 | initialization..\r | |
20 | \r | |
21 | Components linking this lib must include CpuIo, PciRootBridgeIo, and \r | |
22 | BootScriptSave protocols in their DPX.\r | |
23 | \r | |
24 | Revision History:\r | |
25 | \r | |
26 | --*/\r | |
27 | \r | |
28 | #ifndef EFI_REG_TABLE_H\r | |
29 | #define EFI_REG_TABLE_H\r | |
30 | \r | |
31 | #include "Tiano.h"\r | |
32 | #include "EfiScriptLib.h"\r | |
33 | #include EFI_PROTOCOL_CONSUMER (CpuIo)\r | |
34 | #include EFI_PROTOCOL_CONSUMER (PciRootBridgeIo)\r | |
35 | \r | |
36 | //\r | |
37 | // RegTable OpCodes are encoded as follows:\r | |
38 | //\r | |
39 | // |31----------------------------16|15---------8|7-------0|\r | |
40 | // \ \ \\r | |
41 | // \ \ \\r | |
42 | // 31:16 defined by Base OpCode---+ \ \\r | |
43 | // Opcode Flags---+ \\r | |
44 | // Base OpCode---+\r | |
45 | //\r | |
46 | #define OPCODE_BASE(OpCode) ((UINT8)((OpCode) & 0xFF))\r | |
47 | #define OPCODE_FLAGS(OpCode) ((UINT8)(((OpCode) >> 8) & 0xFF)) \r | |
48 | #define OPCODE_EXTRA_DATA(OpCode) ((UINT16)((OpCode) >> 16)) \r | |
49 | \r | |
50 | //\r | |
51 | // RegTable Base OpCodes\r | |
52 | //\r | |
53 | #define OP_TERMINATE_TABLE 0\r | |
54 | #define OP_MEM_WRITE 1\r | |
55 | #define OP_MEM_READ_MODIFY_WRITE 2\r | |
56 | #define OP_IO_WRITE 3\r | |
57 | #define OP_IO_READ_MODIFY_WRITE 4\r | |
58 | #define OP_PCI_WRITE 5\r | |
59 | #define OP_PCI_READ_MODIFY_WRITE 6\r | |
60 | #define OP_STALL 7\r | |
61 | \r | |
62 | //\r | |
63 | // RegTable OpCode Flags\r | |
64 | //\r | |
65 | #define OPCODE_FLAG_S3SAVE 1\r | |
66 | \r | |
67 | \r | |
68 | #define TERMINATE_TABLE { (UINT32) OP_TERMINATE_TABLE, (UINT32) 0, (UINT32) 0 }\r | |
69 | \r | |
70 | \r | |
71 | //\r | |
72 | // REG_TABLE_ENTRY_PCI_WRITE encodes the width in the upper bits of the OpCode\r | |
73 | // as one of the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH values\r | |
74 | //\r | |
75 | typedef struct {\r | |
76 | UINT32 OpCode;\r | |
77 | UINT32 PciAddress;\r | |
78 | UINT32 Data;\r | |
79 | } EFI_REG_TABLE_PCI_WRITE;\r | |
80 | \r | |
81 | #define PCI_WRITE(Bus, Dev, Fnc, Reg, Width, Data, S3Flag) \\r | |
82 | { \\r | |
83 | (UINT32) (OP_PCI_WRITE | ((S3Flag) << 8) | ((Width) << 16)), \\r | |
84 | (UINT32) (EFI_PCI_ADDRESS ((Bus), (Dev), (Fnc), (Reg))), \\r | |
85 | (UINT32) (Data), \\r | |
86 | (UINT32) (0) \\r | |
87 | }\r | |
88 | \r | |
89 | typedef struct {\r | |
90 | UINT32 OpCode;\r | |
91 | UINT32 PciAddress;\r | |
92 | UINT32 OrMask;\r | |
93 | UINT32 AndMask;\r | |
94 | } EFI_REG_TABLE_PCI_READ_MODIFY_WRITE;\r | |
95 | \r | |
96 | #define PCI_READ_MODIFY_WRITE(Bus, Dev, Fnc, Reg, Width, OrMask, AndMask, S3Flag) \\r | |
97 | { \\r | |
98 | (UINT32) (OP_PCI_READ_MODIFY_WRITE | ((S3Flag) << 8) | ((Width) << 16)), \\r | |
99 | (UINT32) (EFI_PCI_ADDRESS ((Bus), (Dev), (Fnc), (Reg))), \\r | |
100 | (UINT32) (OrMask), \\r | |
101 | (UINT32) (AndMask) \\r | |
102 | }\r | |
103 | \r | |
104 | typedef struct {\r | |
105 | UINT32 OpCode;\r | |
106 | UINT32 MemAddress;\r | |
107 | UINT32 OrMask;\r | |
108 | UINT32 AndMask;\r | |
109 | } EFI_REG_TABLE_MEM_READ_MODIFY_WRITE;\r | |
110 | \r | |
111 | #define MEM_READ_MODIFY_WRITE(Address, Width, OrMask, AndMask, S3Flag) \\r | |
112 | { \\r | |
113 | (UINT32) (OP_MEM_READ_MODIFY_WRITE | ((S3Flag) << 8) | ((Width) << 16)), \\r | |
114 | (UINT32) (Address), \\r | |
115 | (UINT32) (OrMask), \\r | |
116 | (UINT32) (AndMask) \\r | |
117 | }\r | |
118 | \r | |
119 | typedef struct {\r | |
120 | UINT32 OpCode;\r | |
121 | UINT32 Field2;\r | |
122 | UINT32 Field3;\r | |
123 | UINT32 Field4;\r | |
124 | } EFI_REG_TABLE_GENERIC;\r | |
125 | \r | |
126 | typedef union {\r | |
127 | EFI_REG_TABLE_GENERIC Generic;\r | |
128 | EFI_REG_TABLE_PCI_WRITE PciWrite;\r | |
129 | EFI_REG_TABLE_PCI_READ_MODIFY_WRITE PciReadModifyWrite;\r | |
130 | EFI_REG_TABLE_MEM_READ_MODIFY_WRITE MemReadModifyWrite;\r | |
131 | } EFI_REG_TABLE;\r | |
132 | \r | |
133 | VOID\r | |
134 | ProcessRegTablePci (\r | |
135 | EFI_REG_TABLE * RegTableEntry,\r | |
136 | EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL * PciRootBridgeIo,\r | |
137 | EFI_CPU_IO_PROTOCOL * CpuIo\r | |
138 | )\r | |
139 | /*++\r | |
140 | \r | |
141 | Routine Description:\r | |
142 | Processes register table assuming which may contain PCI, IO, MEM, and STALL\r | |
143 | entries.\r | |
144 | \r | |
145 | No parameter checking is done so the caller must be careful about omitting\r | |
146 | values for PciRootBridgeIo or CpuIo parameters. If the regtable does\r | |
147 | not contain any PCI accesses, it is safe to omit the PciRootBridgeIo (supply\r | |
148 | NULL). If the regtable does not contain any IO or Mem entries, it is safe to\r | |
149 | omit the CpuIo (supply NULL).\r | |
150 | \r | |
151 | The RegTableEntry parameter is not checked, but is required.\r | |
152 | \r | |
153 | gBS is assumed to have been defined and is used when processing stalls.\r | |
154 | \r | |
155 | The function processes each entry sequentially until an OP_TERMINATE_TABLE\r | |
156 | entry is encountered.\r | |
157 | \r | |
158 | Arguments:\r | |
159 | RegTableEntry - A pointer to the register table to process\r | |
160 | \r | |
161 | PciRootBridgeIo - A pointer to the instance of PciRootBridgeIo that is used\r | |
162 | when processing PCI table entries\r | |
163 | \r | |
164 | CpuIo - A pointer to the instance of CpuIo that is used when processing IO and\r | |
165 | MEM table entries\r | |
166 | \r | |
167 | Returns:\r | |
168 | Nothing. \r | |
169 | \r | |
170 | --*/\r | |
171 | ;\r | |
172 | \r | |
173 | VOID\r | |
174 | ProcessRegTableCpu (\r | |
175 | EFI_REG_TABLE * RegTableEntry,\r | |
176 | EFI_CPU_IO_PROTOCOL * CpuIo\r | |
177 | )\r | |
178 | /*++\r | |
179 | \r | |
180 | Routine Description:\r | |
181 | Processes register table assuming which may contain IO, MEM, and STALL\r | |
182 | entries, but must NOT contain any PCI entries. Any PCI entries cause an\r | |
183 | ASSERT in a DEBUG build and are skipped in a free build.\r | |
184 | \r | |
185 | No parameter checking is done. Both RegTableEntry and CpuIo parameters are\r | |
186 | required.\r | |
187 | \r | |
188 | gBS is assumed to have been defined and is used when processing stalls.\r | |
189 | \r | |
190 | The function processes each entry sequentially until an OP_TERMINATE_TABLE\r | |
191 | entry is encountered.\r | |
192 | \r | |
193 | Arguments:\r | |
194 | RegTableEntry - A pointer to the register table to process\r | |
195 | \r | |
196 | CpuIo - A pointer to the instance of CpuIo that is used when processing IO and\r | |
197 | MEM table entries\r | |
198 | \r | |
199 | Returns:\r | |
200 | Nothing. \r | |
201 | \r | |
202 | --*/\r | |
203 | ;\r | |
204 | \r | |
205 | #endif\r |