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3eb9473e | 1 | /*++\r |
2 | \r | |
3 | Copyright (c) 2004 - 2006, Intel Corporation \r | |
4 | All rights reserved. This program and the accompanying materials \r | |
5 | are licensed and made available under the terms and conditions of the BSD License \r | |
6 | which accompanies this distribution. The full text of the license may be found at \r | |
7 | http://opensource.org/licenses/bsd-license.php \r | |
8 | \r | |
9 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
10 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
11 | \r | |
12 | \r | |
13 | Module Name:\r | |
14 | \r | |
15 | x86Cache.c\r | |
16 | \r | |
17 | Abstract: \r | |
18 | \r | |
19 | Cache Maintenance Functions.\r | |
20 | \r | |
21 | --*/\r | |
22 | \r | |
23 | #include "EdkIIGlueBase.h"\r | |
24 | \r | |
25 | /**\r | |
26 | Invalidates the entire instruction cache in cache coherency domain of the\r | |
27 | calling CPU.\r | |
28 | \r | |
29 | Invalidates the entire instruction cache in cache coherency domain of the\r | |
30 | calling CPU.\r | |
31 | \r | |
32 | **/\r | |
33 | VOID\r | |
34 | EFIAPI\r | |
35 | GlueInvalidateInstructionCache (\r | |
36 | VOID\r | |
37 | )\r | |
38 | {\r | |
39 | }\r | |
40 | \r | |
41 | /**\r | |
42 | Invalidates a range of instruction cache lines in the cache coherency domain\r | |
43 | of the calling CPU.\r | |
44 | \r | |
45 | Invalidates the instruction cache lines specified by Address and Length. If\r | |
46 | Address is not aligned on a cache line boundary, then entire instruction\r | |
47 | cache line containing Address is invalidated. If Address + Length is not\r | |
48 | aligned on a cache line boundary, then the entire instruction cache line\r | |
49 | containing Address + Length -1 is invalidated. This function may choose to\r | |
50 | invalidate the entire instruction cache if that is more efficient than\r | |
51 | invalidating the specified range. If Length is 0, the no instruction cache\r | |
52 | lines are invalidated. Address is returned.\r | |
53 | \r | |
54 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
55 | \r | |
56 | @param Address The base address of the instruction cache lines to\r | |
57 | invalidate. If the CPU is in a physical addressing mode, then\r | |
58 | Address is a physical address. If the CPU is in a virtual\r | |
59 | addressing mode, then Address is a virtual address.\r | |
60 | \r | |
61 | @param Length The number of bytes to invalidate from the instruction cache.\r | |
62 | \r | |
63 | @return Address\r | |
64 | \r | |
65 | **/\r | |
66 | VOID *\r | |
67 | EFIAPI\r | |
68 | InvalidateInstructionCacheRange (\r | |
69 | IN VOID *Address,\r | |
70 | IN UINTN Length\r | |
71 | )\r | |
72 | {\r | |
73 | ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r | |
74 | return Address;\r | |
75 | }\r | |
76 | \r | |
77 | /**\r | |
78 | Writes Back and Invalidates the entire data cache in cache coherency domain\r | |
79 | of the calling CPU.\r | |
80 | \r | |
81 | Writes Back and Invalidates the entire data cache in cache coherency domain\r | |
82 | of the calling CPU. This function guarantees that all dirty cache lines are\r | |
83 | written back to system memory, and also invalidates all the data cache lines\r | |
84 | in the cache coherency domain of the calling CPU.\r | |
85 | \r | |
86 | **/\r | |
87 | VOID\r | |
88 | EFIAPI\r | |
89 | WriteBackInvalidateDataCache (\r | |
90 | VOID\r | |
91 | )\r | |
92 | {\r | |
93 | }\r | |
94 | \r | |
95 | /**\r | |
96 | Writes Back and Invalidates a range of data cache lines in the cache\r | |
97 | coherency domain of the calling CPU.\r | |
98 | \r | |
99 | Writes Back and Invalidate the data cache lines specified by Address and\r | |
100 | Length. If Address is not aligned on a cache line boundary, then entire data\r | |
101 | cache line containing Address is written back and invalidated. If Address +\r | |
102 | Length is not aligned on a cache line boundary, then the entire data cache\r | |
103 | line containing Address + Length -1 is written back and invalidated. This\r | |
104 | function may choose to write back and invalidate the entire data cache if\r | |
105 | that is more efficient than writing back and invalidating the specified\r | |
106 | range. If Length is 0, the no data cache lines are written back and\r | |
107 | invalidated. Address is returned.\r | |
108 | \r | |
109 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
110 | \r | |
111 | @param Address The base address of the data cache lines to write back and\r | |
112 | invalidate. If the CPU is in a physical addressing mode, then\r | |
113 | Address is a physical address. If the CPU is in a virtual\r | |
114 | addressing mode, then Address is a virtual address.\r | |
115 | @param Length The number of bytes to write back and invalidate from the\r | |
116 | data cache.\r | |
117 | \r | |
118 | @return Address\r | |
119 | \r | |
120 | **/\r | |
121 | VOID *\r | |
122 | EFIAPI\r | |
123 | WriteBackInvalidateDataCacheRange (\r | |
124 | IN VOID *Address,\r | |
125 | IN UINTN Length\r | |
126 | )\r | |
127 | {\r | |
128 | ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r | |
129 | return Address;\r | |
130 | }\r | |
131 | \r | |
132 | /**\r | |
133 | Writes Back the entire data cache in cache coherency domain of the calling\r | |
134 | CPU.\r | |
135 | \r | |
136 | Writes Back the entire data cache in cache coherency domain of the calling\r | |
137 | CPU. This function guarantees that all dirty cache lines are written back to\r | |
138 | system memory. This function may also invalidate all the data cache lines in\r | |
139 | the cache coherency domain of the calling CPU.\r | |
140 | \r | |
141 | **/\r | |
142 | VOID\r | |
143 | EFIAPI\r | |
144 | WriteBackDataCache (\r | |
145 | VOID\r | |
146 | )\r | |
147 | {\r | |
148 | }\r | |
149 | \r | |
150 | /**\r | |
151 | Writes Back a range of data cache lines in the cache coherency domain of the\r | |
152 | calling CPU.\r | |
153 | \r | |
154 | Writes Back the data cache lines specified by Address and Length. If Address\r | |
155 | is not aligned on a cache line boundary, then entire data cache line\r | |
156 | containing Address is written back. If Address + Length is not aligned on a\r | |
157 | cache line boundary, then the entire data cache line containing Address +\r | |
158 | Length -1 is written back. This function may choose to write back the entire\r | |
159 | data cache if that is more efficient than writing back the specified range.\r | |
160 | If Length is 0, the no data cache lines are written back. This function may\r | |
161 | also invalidate all the data cache lines in the specified range of the cache\r | |
162 | coherency domain of the calling CPU. Address is returned.\r | |
163 | \r | |
164 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
165 | \r | |
166 | @param Address The base address of the data cache lines to write back. If\r | |
167 | the CPU is in a physical addressing mode, then Address is a\r | |
168 | physical address. If the CPU is in a virtual addressing\r | |
169 | mode, then Address is a virtual address.\r | |
170 | @param Length The number of bytes to write back from the data cache.\r | |
171 | \r | |
172 | @return Address\r | |
173 | \r | |
174 | **/\r | |
175 | VOID *\r | |
176 | EFIAPI\r | |
177 | WriteBackDataCacheRange (\r | |
178 | IN VOID *Address,\r | |
179 | IN UINTN Length\r | |
180 | )\r | |
181 | {\r | |
182 | ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r | |
183 | return Address;\r | |
184 | }\r | |
185 | \r | |
186 | /**\r | |
187 | Invalidates the entire data cache in cache coherency domain of the calling\r | |
188 | CPU.\r | |
189 | \r | |
190 | Invalidates the entire data cache in cache coherency domain of the calling\r | |
191 | CPU. This function must be used with care because dirty cache lines are not\r | |
192 | written back to system memory. It is typically used for cache diagnostics. If\r | |
193 | the CPU does not support invalidation of the entire data cache, then a write\r | |
194 | back and invalidate operation should be performed on the entire data cache.\r | |
195 | \r | |
196 | **/\r | |
197 | VOID\r | |
198 | EFIAPI\r | |
199 | InvalidateDataCache (\r | |
200 | VOID\r | |
201 | )\r | |
202 | {\r | |
203 | }\r | |
204 | \r | |
205 | /**\r | |
206 | Invalidates a range of data cache lines in the cache coherency domain of the\r | |
207 | calling CPU.\r | |
208 | \r | |
209 | Invalidates the data cache lines specified by Address and Length. If Address\r | |
210 | is not aligned on a cache line boundary, then entire data cache line\r | |
211 | containing Address is invalidated. If Address + Length is not aligned on a\r | |
212 | cache line boundary, then the entire data cache line containing Address +\r | |
213 | Length -1 is invalidated. This function must never invalidate any cache lines\r | |
214 | outside the specified range. If Length is 0, the no data cache lines are\r | |
215 | invalidated. Address is returned. This function must be used with care\r | |
216 | because dirty cache lines are not written back to system memory. It is\r | |
217 | typically used for cache diagnostics. If the CPU does not support\r | |
218 | invalidation of a data cache range, then a write back and invalidate\r | |
219 | operation should be performed on the data cache range.\r | |
220 | \r | |
221 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
222 | \r | |
223 | @param Address The base address of the data cache lines to invalidate. If\r | |
224 | the CPU is in a physical addressing mode, then Address is a\r | |
225 | physical address. If the CPU is in a virtual addressing mode,\r | |
226 | then Address is a virtual address.\r | |
227 | @param Length The number of bytes to invalidate from the data cache.\r | |
228 | \r | |
229 | @return Address\r | |
230 | \r | |
231 | **/\r | |
232 | VOID *\r | |
233 | EFIAPI\r | |
234 | InvalidateDataCacheRange (\r | |
235 | IN VOID *Address,\r | |
236 | IN UINTN Length\r | |
237 | )\r | |
238 | {\r | |
239 | ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r | |
240 | return Address;\r | |
241 | }\r |