projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| dbfd80d8 OM |
1 | /** @file\r |
| 2 | \r | |
| 3 | Copyright (c) 2013-2014, ARM Ltd. All rights reserved.<BR>\r | |
| 4 | \r | |
| 5 | This program and the accompanying materials\r | |
| 6 | are licensed and made available under the terms and conditions of the BSD License\r | |
| 7 | which accompanies this distribution. The full text of the license may be found at\r | |
| 8 | http://opensource.org/licenses/bsd-license.php\r | |
| 9 | \r | |
| 10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 12 | \r | |
| 13 | **/\r | |
| 14 | \r | |
| 15 | #ifndef __ISP1761_USB_DXE_H__\r | |
| 16 | #define __ISP1761_USB_DXE_H__\r | |
| 17 | \r | |
| 18 | #define ISP1761_USB_BASE FixedPcdGet32 (PcdIsp1761BaseAddress)\r | |
| 19 | \r | |
| 20 | #define READ_REG32(Offset) MmioRead32 (ISP1761_USB_BASE + Offset)\r | |
| 21 | #define READ_REG16(Offset) (UINT16) READ_REG32 (Offset)\r | |
| 22 | #define WRITE_REG32(Offset, Val) MmioWrite32 (ISP1761_USB_BASE + Offset, Val)\r | |
| 23 | #define WRITE_REG16(Offset, Val) MmioWrite32 (ISP1761_USB_BASE + Offset, (UINT32) Val)\r | |
| 24 | #define WRITE_REG8(Offset, Val) MmioWrite32 (ISP1761_USB_BASE + Offset, (UINT32) Val)\r | |
| 25 | \r | |
| 26 | // Max packet size in bytes (For Full Speed USB 64 is the only valid value)\r | |
| 27 | #define MAX_PACKET_SIZE_CONTROL 64\r | |
| 28 | \r | |
| 29 | #define MAX_PACKET_SIZE_BULK 512\r | |
| 30 | \r | |
| 31 | // 8 Endpoints, in and out. Don't count the Endpoint 0 setup buffer\r | |
| 32 | #define ISP1761_NUM_ENDPOINTS 16\r | |
| 33 | \r | |
| 34 | // Endpoint Indexes\r | |
| 35 | #define ISP1761_EP0SETUP 0x20\r | |
| 36 | #define ISP1761_EP0RX 0x00\r | |
| 37 | #define ISP1761_EP0TX 0x01\r | |
| 38 | #define ISP1761_EP1RX 0x02\r | |
| 39 | #define ISP1761_EP1TX 0x03\r | |
| 40 | \r | |
| 41 | // DcInterrupt bits\r | |
| 42 | #define ISP1761_DC_INTERRUPT_BRESET BIT0\r | |
| 43 | #define ISP1761_DC_INTERRUPT_SOF BIT1\r | |
| 44 | #define ISP1761_DC_INTERRUPT_PSOF BIT2\r | |
| 45 | #define ISP1761_DC_INTERRUPT_SUSP BIT3\r | |
| 46 | #define ISP1761_DC_INTERRUPT_RESUME BIT4\r | |
| 47 | #define ISP1761_DC_INTERRUPT_HS_STAT BIT5\r | |
| 48 | #define ISP1761_DC_INTERRUPT_DMA BIT6\r | |
| 49 | #define ISP1761_DC_INTERRUPT_VBUS BIT7\r | |
| 50 | #define ISP1761_DC_INTERRUPT_EP0SETUP BIT8\r | |
| 51 | #define ISP1761_DC_INTERRUPT_EP0RX BIT10\r | |
| 52 | #define ISP1761_DC_INTERRUPT_EP0TX BIT11\r | |
| 53 | #define ISP1761_DC_INTERRUPT_EP1RX BIT12\r | |
| 54 | #define ISP1761_DC_INTERRUPT_EP1TX BIT13\r | |
| 55 | // All valid peripheral controller interrupts\r | |
| 56 | #define ISP1761_DC_INTERRUPT_MASK 0x003FFFDFF\r | |
| 57 | \r | |
| 58 | #define ISP1761_ADDRESS 0x200\r | |
| 59 | #define ISP1761_ADDRESS_DEVEN BIT7\r | |
| 60 | \r | |
| 61 | #define ISP1761_MODE 0x20C\r | |
| 62 | #define ISP1761_MODE_DATA_BUS_WIDTH BIT8\r | |
| 63 | #define ISP1761_MODE_CLKAON BIT7\r | |
| 64 | #define ISP1761_MODE_SFRESET BIT4\r | |
| 65 | #define ISP1761_MODE_WKUPCS BIT2\r | |
| 66 | \r | |
| 67 | #define ISP1761_ENDPOINT_MAX_PACKET_SIZE 0x204\r | |
| 68 | \r | |
| 69 | #define ISP1761_ENDPOINT_TYPE 0x208\r | |
| 70 | #define ISP1761_ENDPOINT_TYPE_NOEMPKT BIT4\r | |
| 71 | #define ISP1761_ENDPOINT_TYPE_ENABLE BIT3\r | |
| 72 | \r | |
| 73 | #define ISP1761_INTERRUPT_CONFIG 0x210\r | |
| 74 | // Interrupt config value to only interrupt on ACK of IN and OUT tokens\r | |
| 75 | #define ISP1761_INTERRUPT_CONFIG_ACK_ONLY BIT2 | BIT5 | BIT6\r | |
| 76 | \r | |
| 77 | #define ISP1761_DC_INTERRUPT 0x218\r | |
| 78 | #define ISP1761_DC_INTERRUPT_ENABLE 0x214\r | |
| 79 | \r | |
| 80 | #define ISP1761_CTRL_FUNCTION 0x228\r | |
| 81 | #define ISP1761_CTRL_FUNCTION_VENDP BIT3\r | |
| 82 | #define ISP1761_CTRL_FUNCTION_DSEN BIT2\r | |
| 83 | #define ISP1761_CTRL_FUNCTION_STATUS BIT1\r | |
| 84 | \r | |
| 85 | #define ISP1761_DEVICE_UNLOCK 0x27C\r | |
| 86 | #define ISP1761_DEVICE_UNLOCK_MAGIC 0xAA37\r | |
| 87 | \r | |
| 88 | #define ISP1761_SW_RESET_REG 0x30C\r | |
| 89 | #define ISP1761_SW_RESET_ALL BIT0\r | |
| 90 | \r | |
| 91 | #define ISP1761_DEVICE_ID 0x370\r | |
| 92 | \r | |
| 93 | #define ISP1761_OTG_CTRL_SET 0x374\r | |
| 94 | #define ISP1761_OTG_CTRL_CLR OTG_CTRL_SET + 2\r | |
| 95 | #define ISP1761_OTG_CTRL_OTG_DISABLE BIT10\r | |
| 96 | #define ISP1761_OTG_CTRL_VBUS_CHRG BIT6\r | |
| 97 | #define ISP1761_OTG_CTRL_VBUS_DISCHRG BIT5\r | |
| 98 | #define ISP1761_OTG_CTRL_DM_PULLDOWN BIT2\r | |
| 99 | #define ISP1761_OTG_CTRL_DP_PULLDOWN BIT1\r | |
| 100 | #define ISP1761_OTG_CTRL_DP_PULLUP BIT0\r | |
| 101 | \r | |
| 102 | #define ISP1761_OTG_STATUS 0x378\r | |
| 103 | #define ISP1761_OTG_STATUS_B_SESS_END BIT7\r | |
| 104 | #define ISP1761_OTG_STATUS_A_B_SESS_VLD BIT1\r | |
| 105 | \r | |
| 106 | #define ISP1761_OTG_INTERRUPT_LATCH_SET 0x37C\r | |
| 107 | #define ISP1761_OTG_INTERRUPT_LATCH_CLR 0x37E\r | |
| 108 | #define ISP1761_OTG_INTERRUPT_ENABLE_RISE 0x384\r | |
| 109 | \r | |
| 110 | #define ISP1761_DMA_ENDPOINT_INDEX 0x258\r | |
| 111 | \r | |
| 112 | #define ISP1761_ENDPOINT_INDEX 0x22c\r | |
| 113 | #define ISP1761_DATA_PORT 0x220\r | |
| 114 | #define ISP1761_BUFFER_LENGTH 0x21c\r | |
| 115 | \r | |
| 116 | // Device ID Values\r | |
| 117 | #define PHILLIPS_VENDOR_ID_VAL 0x04cc\r | |
| 118 | #define ISP1761_PRODUCT_ID_VAL 0x1761\r | |
| 119 | #define ISP1761_DEVICE_ID_VAL ((ISP1761_PRODUCT_ID_VAL << 16) |\\r | |
| 120 | PHILLIPS_VENDOR_ID_VAL)\r | |
| 121 | \r | |
| 122 | #endif //ifndef __ISP1761_USB_DXE_H__\r |