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Use the "PAY_LOAD" StatusCode definitions defined in IntelFrameworkPkg.
[mirror_edk2.git] / IntelFrameworkModulePkg / Bus / Pci / PciBus / Dxe / pcibus.h
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ead42efc 1/*++\r
2\r
3Copyright (c) 2006 - 2007, Intel Corporation\r
4All rights reserved. This program and the accompanying materials\r
5are licensed and made available under the terms and conditions of the BSD License\r
6which accompanies this distribution. The full text of the license may be found at\r
7http://opensource.org/licenses/bsd-license.php\r
8\r
9THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
10WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
11\r
12Module Name:\r
13\r
14 pcibus.h\r
15\r
16Abstract:\r
17\r
18 PCI Bus Driver\r
19\r
20Revision History\r
21\r
22--*/\r
23\r
24#ifndef _EFI_PCI_BUS_H\r
25#define _EFI_PCI_BUS_H\r
26\r
27//\r
28// The package level header files this module uses\r
29//\r
30#include <PiDxe.h>\r
31#include <Common/FrameworkStatusCode.h>\r
938f2b4f 32#include <Common/FrameworkStatusCodeDataTypeId.h>\r
ead42efc 33//\r
34// The protocols, PPI and GUID defintions for this module\r
35//\r
36#include <Protocol/LoadedImage.h>\r
37#include <Protocol/PciHostBridgeResourceAllocation.h>\r
38#include <Protocol/PciIo.h>\r
39#include <Guid/PciHotplugDevice.h>\r
40#include <Protocol/PciRootBridgeIo.h>\r
41#include <Protocol/PciHotPlugRequest.h>\r
42#include <Protocol/DevicePath.h>\r
43#include <Protocol/PciPlatform.h>\r
44#include <Protocol/PciHotPlugInit.h>\r
45#include <Protocol/Decompress.h>\r
46#include <Guid/PciOptionRomTable.h>\r
47#include <Protocol/BusSpecificDriverOverride.h>\r
48#include <Protocol/UgaIo.h>\r
49//\r
50// The Library classes this module consumes\r
51//\r
52#include <Library/DebugLib.h>\r
53#include <Library/UefiDriverEntryPoint.h>\r
54#include <Library/BaseLib.h>\r
55#include <Library/UefiLib.h>\r
56#include <Library/BaseMemoryLib.h>\r
57#include <Library/ReportStatusCodeLib.h>\r
58#include <Library/MemoryAllocationLib.h>\r
59#include <Library/UefiBootServicesTableLib.h>\r
60#include <Library/DevicePathLib.h>\r
61#include <Library/PcdLib.h>\r
62#include <Library/PciIncompatibleDeviceSupportLib.h>\r
63\r
b1ef4015 64#include <IndustryStandard/Pci23.h>\r
65#include <IndustryStandard/PeImage.h>\r
ead42efc 66#include <IndustryStandard/Acpi.h>\r
67#include "ComponentName.h"\r
68\r
b1ef4015 69///\r
70/// Device handle Extended Data. Used for many\r
71/// errors and progress codes to point to the device.\r
72///\r
73typedef struct {\r
74 EFI_HANDLE Handle;\r
75} REPORT_STATUS_CODE_LIBRARY_DEVICE_HANDLE_EXTENDED_DATA;\r
76\r
77///\r
78/// Resource Allocation Failure Extended Error Data\r
79///\r
80typedef struct {\r
81 UINT32 Bar;\r
82 UINT16 DevicePathSize;\r
83 UINT16 ReqResSize;\r
84 UINT16 AllocResSize;\r
85 UINT8 *DevicePath;\r
86 UINT8 *ReqRes;\r
87 UINT8 *AllocRes;\r
88} REPORT_STATUS_CODE_LIBRARY_RESOURCE_ALLOC_FAILURE_ERROR_DATA;\r
89\r
90\r
ead42efc 91//\r
92// Driver Produced Protocol Prototypes\r
93//\r
94\r
95#define VGABASE1 0x3B0\r
96#define VGALIMIT1 0x3BB\r
97\r
98#define VGABASE2 0x3C0\r
99#define VGALIMIT2 0x3DF\r
100\r
101#define ISABASE 0x100\r
102#define ISALIMIT 0x3FF\r
103\r
104typedef enum {\r
105 PciBarTypeUnknown = 0,\r
106 PciBarTypeIo16,\r
107 PciBarTypeIo32,\r
108 PciBarTypeMem32,\r
109 PciBarTypePMem32,\r
110 PciBarTypeMem64,\r
111 PciBarTypePMem64,\r
112 PciBarTypeIo,\r
113 PciBarTypeMem,\r
114 PciBarTypeMaxType\r
115} PCI_BAR_TYPE;\r
116\r
117typedef struct {\r
118 UINT64 BaseAddress;\r
119 UINT64 Length;\r
120 UINT64 Alignment;\r
121 PCI_BAR_TYPE BarType;\r
122 BOOLEAN Prefetchable;\r
123 UINT8 MemType;\r
124 UINT8 Offset;\r
125} PCI_BAR;\r
126\r
127#define PPB_BAR_0 0\r
128#define PPB_BAR_1 1\r
129#define PPB_IO_RANGE 2\r
130#define PPB_MEM32_RANGE 3\r
131#define PPB_PMEM32_RANGE 4\r
132#define PPB_PMEM64_RANGE 5\r
133#define PPB_MEM64_RANGE 0xFF\r
134\r
135#define P2C_BAR_0 0\r
136#define P2C_MEM_1 1\r
137#define P2C_MEM_2 2\r
138#define P2C_IO_1 3\r
139#define P2C_IO_2 4\r
140\r
141#define PCI_IO_DEVICE_SIGNATURE EFI_SIGNATURE_32 ('p', 'c', 'i', 'o')\r
142\r
143#define EFI_BRIDGE_IO32_DECODE_SUPPORTED 0x0001\r
144#define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED 0x0002\r
145#define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED 0x0004\r
146#define EFI_BRIDGE_IO16_DECODE_SUPPORTED 0x0008\r
147#define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010\r
148#define EFI_BRIDGE_MEM64_DECODE_SUPPORTED 0x0020\r
149#define EFI_BRIDGE_MEM32_DECODE_SUPPORTED 0x0040\r
150\r
151#define PCI_MAX_HOST_BRIDGE_NUM 0x0010\r
152//\r
153// Define resource status constant\r
154//\r
155#define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL\r
156#define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL\r
157#define EFI_RESOURCE_SATISFIED 0x0000000000000000ULL\r
158\r
159//\r
160// Define option for attribute\r
161//\r
162#define EFI_SET_SUPPORTS 0\r
163#define EFI_SET_ATTRIBUTES 1\r
164\r
165typedef struct _PCI_IO_DEVICE {\r
166 UINT32 Signature;\r
167 EFI_HANDLE Handle;\r
168 EFI_PCI_IO_PROTOCOL PciIo;\r
169 LIST_ENTRY Link;\r
170\r
171 EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;\r
172 EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
173 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
174\r
175 //\r
176 // PCI configuration space header type\r
177 //\r
178 PCI_TYPE00 Pci;\r
179\r
180 //\r
181 // Bus number, Device number, Function number\r
182 //\r
183 UINT8 BusNumber;\r
184 UINT8 DeviceNumber;\r
185 UINT8 FunctionNumber;\r
186\r
187 //\r
188 // BAR for this PCI Device\r
189 //\r
190 PCI_BAR PciBar[PCI_MAX_BAR];\r
191\r
192 //\r
193 // The bridge device this pci device is subject to\r
194 //\r
195 struct _PCI_IO_DEVICE *Parent;\r
196\r
197 //\r
198 // A linked list for children Pci Device if it is bridge device\r
199 //\r
200 LIST_ENTRY ChildList;\r
201\r
202 //\r
203 // TURE if the PCI bus driver creates the handle for this PCI device\r
204 //\r
205 BOOLEAN Registered;\r
206\r
207 //\r
208 // TRUE if the PCI bus driver successfully allocates the resource required by\r
209 // this PCI device\r
210 //\r
211 BOOLEAN Allocated;\r
212\r
213 //\r
214 // The attribute this PCI device currently set\r
215 //\r
216 UINT64 Attributes;\r
217\r
218 //\r
219 // The attributes this PCI device actually supports\r
220 //\r
221 UINT64 Supports;\r
222\r
223 //\r
224 // The resource decode the bridge supports\r
225 //\r
226 UINT32 Decodes;\r
227\r
228 //\r
229 // The OptionRom Size\r
230 //\r
231 UINT64 RomSize;\r
232\r
233 //\r
234 // The OptionRom Size\r
235 //\r
236 UINT64 RomBase;\r
237\r
238 //\r
239 // TRUE if all OpROM (in device or in platform specific position) have been processed\r
240 //\r
241 BOOLEAN AllOpRomProcessed;\r
242\r
243 //\r
244 // TRUE if there is any EFI driver in the OptionRom\r
245 //\r
246 BOOLEAN BusOverride;\r
247\r
248 //\r
249 // A list tracking reserved resource on a bridge device\r
250 //\r
251 LIST_ENTRY ReservedResourceList;\r
252\r
253 //\r
254 // A list tracking image handle of platform specific overriding driver\r
255 //\r
256 LIST_ENTRY OptionRomDriverList;\r
257\r
258 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ResourcePaddingDescriptors;\r
259 EFI_HPC_PADDING_ATTRIBUTES PaddingAttributes;\r
260\r
261 BOOLEAN IsPciExp;\r
262\r
263} PCI_IO_DEVICE;\r
264\r
265\r
266#define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \\r
267 CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)\r
268\r
269#define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) \\r
270 CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)\r
271\r
272#define PCI_IO_DEVICE_FROM_LINK(a) \\r
273 CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)\r
274\r
275//\r
276// Global Variables\r
277//\r
278extern EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding;\r
279extern EFI_COMPONENT_NAME_PROTOCOL gPciBusComponentName;\r
280extern LIST_ENTRY gPciDevicePool;\r
281extern BOOLEAN gFullEnumeration;\r
282extern UINTN gPciHostBridgeNumber;\r
283extern EFI_HANDLE gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];\r
284extern UINT64 gAllOne;\r
285extern UINT64 gAllZero;\r
286\r
287extern EFI_PCI_PLATFORM_PROTOCOL *gPciPlatformProtocol;\r
288\r
289#include "PciIo.h"\r
290#include "PciCommand.h"\r
291#include "PciDeviceSupport.h"\r
292#include "PciEnumerator.h"\r
293#include "PciEnumeratorSupport.h"\r
294#include "PciDriverOverride.h"\r
295#include "PciRomTable.h"\r
296#include "PciOptionRomSupport.h"\r
297#include "PciPowerManagement.h"\r
298#include "PciHotPlugSupport.h"\r
299#include "PciLib.h"\r
300\r
301//\r
302// PCI Bus Support Function Prototypes\r
303//\r
304EFI_STATUS\r
305EFIAPI\r
306PciBusDriverBindingSupported (\r
307 IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
308 IN EFI_HANDLE Controller,\r
309 IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
310 );\r
311\r
312EFI_STATUS\r
313EFIAPI\r
314PciBusDriverBindingStart (\r
315 IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
316 IN EFI_HANDLE Controller,\r
317 IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
318 );\r
319\r
320EFI_STATUS\r
321EFIAPI\r
322PciBusDriverBindingStop (\r
323 IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
324 IN EFI_HANDLE Controller,\r
325 IN UINTN NumberOfChildren,\r
326 IN EFI_HANDLE *ChildHandleBuffer\r
327 );\r
328\r
329#endif\r
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