[mirror_edk2.git] / IntelFrameworkModulePkg / Bus / Pci / PciBusDxe / PciCommand.h

/** @file\r
\r
Copyright (c) 2006 - 2009, Intel Corporation                                                         \r
All rights reserved. This program and the accompanying materials                          \r
are licensed and made available under the terms and conditions of the BSD License         \r
which accompanies this distribution.  The full text of the license may be found at        \r
http://opensource.org/licenses/bsd-license.php                                            \r
                                                                                          \r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
\r
**/\r
\r
\r
#ifndef _EFI_PCI_COMMAND_H_\r
#define _EFI_PCI_COMMAND_H_\r
\r
//\r
// The PCI Command register bits owned by PCI Bus driver.\r
//\r
// They should be cleared at the beginning. The other registers\r
// are owned by chipset, we should not touch them.\r
//\r
#define EFI_PCI_COMMAND_BITS_OWNED                          ( \\r
                EFI_PCI_COMMAND_IO_SPACE                    | \\r
                EFI_PCI_COMMAND_MEMORY_SPACE                | \\r
                EFI_PCI_COMMAND_BUS_MASTER                  | \\r
                EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE | \\r
                EFI_PCI_COMMAND_VGA_PALETTE_SNOOP           | \\r
                EFI_PCI_COMMAND_FAST_BACK_TO_BACK             \\r
                )\r
\r
//\r
// The PCI Bridge Control register bits owned by PCI Bus driver.\r
// \r
// They should be cleared at the beginning. The other registers\r
// are owned by chipset, we should not touch them.\r
//\r
#define EFI_PCI_BRIDGE_CONTROL_BITS_OWNED                   ( \\r
                EFI_PCI_BRIDGE_CONTROL_ISA                  | \\r
                EFI_PCI_BRIDGE_CONTROL_VGA                  | \\r
                EFI_PCI_BRIDGE_CONTROL_VGA_16               | \\r
                EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK      \\r
                )\r
\r
//\r
// The PCCard Bridge Control register bits owned by PCI Bus driver.\r
// \r
// They should be cleared at the beginning. The other registers\r
// are owned by chipset, we should not touch them.\r
//\r
#define EFI_PCCARD_BRIDGE_CONTROL_BITS_OWNED                ( \\r
                EFI_PCI_BRIDGE_CONTROL_ISA                  | \\r
                EFI_PCI_BRIDGE_CONTROL_VGA                  | \\r
                EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK      \\r
                )\r
\r
\r
#define EFI_GET_REGISTER      1\r
#define EFI_SET_REGISTER      2\r
#define EFI_ENABLE_REGISTER   3\r
#define EFI_DISABLE_REGISTER  4\r
\r
/**\r
  Operate the PCI register via PciIo function interface.\r
  \r
  @param PciIoDevice    Pointer to instance of PCI_IO_DEVICE\r
  @param Command        Operator command\r
  @param Offset         The address within the PCI configuration space for the PCI controller.\r
  @param Operation      Type of Operation\r
  @param PtrCommand     Return buffer holding old PCI command, if operation is not EFI_SET_REGISTER\r
  \r
  @return status of PciIo operation\r
**/\r
EFI_STATUS\r
PciOperateRegister (\r
  IN  PCI_IO_DEVICE *PciIoDevice,\r
  IN  UINT16        Command,\r
  IN  UINT8         Offset,\r
  IN  UINT8         Operation,\r
  OUT UINT16        *PtrCommand\r
  );\r
\r
/**\r
  check the cpability of this device supports\r
  \r
  @param PciIoDevice  Pointer to instance of PCI_IO_DEVICE\r
  \r
  @retval TRUE  Support\r
  @retval FALSE Not support.\r
**/\r
BOOLEAN\r
PciCapabilitySupport (\r
  IN PCI_IO_DEVICE  *PciIoDevice\r
  );\r
\r
/**\r
  Locate cap reg.\r
  \r
  @param PciIoDevice         - A pointer to the PCI_IO_DEVICE.\r
  @param CapId               - The cap ID.\r
  @param Offset              - A pointer to the offset.\r
  @param NextRegBlock        - A pointer to the next block.\r
  \r
  @retval EFI_UNSUPPORTED  Pci device does not support\r
  @retval EFI_NOT_FOUND    Pci device support but can not find register block.\r
  @retval EFI_SUCCESS      Success to locate capability register block\r
**/\r
EFI_STATUS\r
LocateCapabilityRegBlock (\r
  IN PCI_IO_DEVICE  *PciIoDevice,\r
  IN UINT8          CapId,\r
  IN OUT UINT8      *Offset,\r
  OUT UINT8         *NextRegBlock OPTIONAL\r
  );\r
\r
/**  \r
  Macro that reads command register.\r
\r
  @param a[in]            Pointer to instance of PCI_IO_DEVICE.\r
  @param b[out]           Pointer to the 16-bit value read from command register.\r
  \r
  @return status of PciIo operation\r
\r
**/\r
#define PCI_READ_COMMAND_REGISTER(a,b) \\r
        PciOperateRegister (a, 0, PCI_COMMAND_OFFSET, EFI_GET_REGISTER, b)\r
\r
/**  \r
  Macro that writes command register.\r
\r
  @param a[in]            Pointer to instance of PCI_IO_DEVICE.\r
  @param b[in]            The 16-bit value written into command register.\r
  \r
  @return status of PciIo operation\r
\r
**/\r
#define PCI_SET_COMMAND_REGISTER(a,b) \\r
        PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_SET_REGISTER, NULL)\r
\r
/**  \r
  Macro that enables command register.\r
\r
  @param a[in]            Pointer to instance of PCI_IO_DEVICE.\r
  @param b[in]            The enabled value written into command register.\r
  \r
  @return status of PciIo operation\r
\r
**/        \r
#define PCI_ENABLE_COMMAND_REGISTER(a,b) \\r
        PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_ENABLE_REGISTER, NULL)\r
\r
/**  \r
  Macro that disalbes command register.\r
\r
  @param a[in]            Pointer to instance of PCI_IO_DEVICE.\r
  @param b[in]            The disabled value written into command register.\r
  \r
  @return status of PciIo operation\r
\r
**/        \r
#define PCI_DISABLE_COMMAND_REGISTER(a,b) \\r
        PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_DISABLE_REGISTER, NULL)\r
\r
/**  \r
  Macro that reads PCI bridge control register.\r
\r
  @param a[in]            Pointer to instance of PCI_IO_DEVICE.\r
  @param b[out]           The 16-bit value read from control register.\r
  \r
  @return status of PciIo operation\r
\r
**/\r
#define PCI_READ_BRIDGE_CONTROL_REGISTER(a,b) \\r
        PciOperateRegister (a, 0, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_GET_REGISTER, b)\r
\r
/**  \r
  Macro that writes PCI bridge control register.\r
\r
  @param a[in]            Pointer to instance of PCI_IO_DEVICE.\r
  @param b[in]            The 16-bit value written into control register.\r
  \r
  @return status of PciIo operation\r
\r
**/        \r
#define PCI_SET_BRIDGE_CONTROL_REGISTER(a,b) \\r
        PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_SET_REGISTER, NULL)\r
\r
/**  \r
  Macro that enables PCI bridge control register.\r
\r
  @param a[in]            Pointer to instance of PCI_IO_DEVICE.\r
  @param b[in]            The enabled value written into command register.\r
  \r
  @return status of PciIo operation\r
\r
**/\r
#define PCI_ENABLE_BRIDGE_CONTROL_REGISTER(a,b) \\r
        PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_ENABLE_REGISTER, NULL)\r
\r
/**  \r
 Macro that disalbes PCI bridge control register.\r
\r
  @param a[in]            Pointer to instance of PCI_IO_DEVICE.\r
  @param b[in]            The disabled value written into command register.\r
  \r
  @return status of PciIo operation\r
\r
**/        \r
#define PCI_DISABLE_BRIDGE_CONTROL_REGISTER(a,b) \\r
        PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_DISABLE_REGISTER, NULL)\r
\r
#endif\r
Commit	Line	Data
97404058	1	/** @file\r
ead42efc	2	\r
94b9d5c6	3	Copyright (c) 2006 - 2009, Intel Corporation \r
ead42efc	4	All rights reserved. This program and the accompanying materials \r
	5	are licensed and made available under the terms and conditions of the BSD License \r
	6	which accompanies this distribution. The full text of the license may be found at \r
	7	http://opensource.org/licenses/bsd-license.php \r
	8	\r
	9	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
	10	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
	11	\r
3db51098	12	**/\r
ead42efc	13	\r
ead42efc	14	\r
eeefcb9d	15	#ifndef _EFI_PCI_COMMAND_H_\r
eeefcb9d	16	#define _EFI_PCI_COMMAND_H_\r
ead42efc	17	\r
	18	//\r
	19	// The PCI Command register bits owned by PCI Bus driver.\r
	20	//\r
	21	// They should be cleared at the beginning. The other registers\r
	22	// are owned by chipset, we should not touch them.\r
	23	//\r
	24	#define EFI_PCI_COMMAND_BITS_OWNED ( \\r
	25	EFI_PCI_COMMAND_IO_SPACE \| \\r
	26	EFI_PCI_COMMAND_MEMORY_SPACE \| \\r
	27	EFI_PCI_COMMAND_BUS_MASTER \| \\r
	28	EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE \| \\r
	29	EFI_PCI_COMMAND_VGA_PALETTE_SNOOP \| \\r
	30	EFI_PCI_COMMAND_FAST_BACK_TO_BACK \\r
	31	)\r
	32	\r
	33	//\r
	34	// The PCI Bridge Control register bits owned by PCI Bus driver.\r
	35	// \r
	36	// They should be cleared at the beginning. The other registers\r
	37	// are owned by chipset, we should not touch them.\r
	38	//\r
	39	#define EFI_PCI_BRIDGE_CONTROL_BITS_OWNED ( \\r
	40	EFI_PCI_BRIDGE_CONTROL_ISA \| \\r
	41	EFI_PCI_BRIDGE_CONTROL_VGA \| \\r
	42	EFI_PCI_BRIDGE_CONTROL_VGA_16 \| \\r
	43	EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK \\r
	44	)\r
	45	\r
	46	//\r
	47	// The PCCard Bridge Control register bits owned by PCI Bus driver.\r
	48	// \r
	49	// They should be cleared at the beginning. The other registers\r
	50	// are owned by chipset, we should not touch them.\r
	51	//\r
	52	#define EFI_PCCARD_BRIDGE_CONTROL_BITS_OWNED ( \\r
	53	EFI_PCI_BRIDGE_CONTROL_ISA \| \\r
	54	EFI_PCI_BRIDGE_CONTROL_VGA \| \\r
	55	EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK \\r
	56	)\r
	57	\r
	58	\r
	59	#define EFI_GET_REGISTER 1\r
	60	#define EFI_SET_REGISTER 2\r
	61	#define EFI_ENABLE_REGISTER 3\r
	62	#define EFI_DISABLE_REGISTER 4\r
	63	\r
a3b8e257	64	/**\r
	65	Operate the PCI register via PciIo function interface.\r
	66	\r
	67	@param PciIoDevice Pointer to instance of PCI_IO_DEVICE\r
	68	@param Command Operator command\r
	69	@param Offset The address within the PCI configuration space for the PCI controller.\r
	70	@param Operation Type of Operation\r
	71	@param PtrCommand Return buffer holding old PCI command, if operation is not EFI_SET_REGISTER\r
	72	\r
	73	@return status of PciIo operation\r
	74	**/\r
ead42efc	75	EFI_STATUS\r
	76	PciOperateRegister (\r
	77	IN PCI_IO_DEVICE *PciIoDevice,\r
	78	IN UINT16 Command,\r
	79	IN UINT8 Offset,\r
	80	IN UINT8 Operation,\r
	81	OUT UINT16 *PtrCommand\r
ed66e1bc	82	);\r
ead42efc	83	\r
a3b8e257	84	/**\r
	85	check the cpability of this device supports\r
	86	\r
	87	@param PciIoDevice Pointer to instance of PCI_IO_DEVICE\r
	88	\r
	89	@retval TRUE Support\r
97404058	90	@retval FALSE Not support.\r
a3b8e257	91	**/\r
ead42efc	92	BOOLEAN\r
	93	PciCapabilitySupport (\r
	94	IN PCI_IO_DEVICE *PciIoDevice\r
ed66e1bc	95	);\r
ead42efc	96	\r
a3b8e257	97	/**\r
	98	Locate cap reg.\r
	99	\r
	100	@param PciIoDevice - A pointer to the PCI_IO_DEVICE.\r
	101	@param CapId - The cap ID.\r
	102	@param Offset - A pointer to the offset.\r
	103	@param NextRegBlock - A pointer to the next block.\r
	104	\r
	105	@retval EFI_UNSUPPORTED Pci device does not support\r
	106	@retval EFI_NOT_FOUND Pci device support but can not find register block.\r
	107	@retval EFI_SUCCESS Success to locate capability register block\r
	108	**/\r
ead42efc	109	EFI_STATUS\r
	110	LocateCapabilityRegBlock (\r
	111	IN PCI_IO_DEVICE *PciIoDevice,\r
	112	IN UINT8 CapId,\r
	113	IN OUT UINT8 *Offset,\r
	114	OUT UINT8 *NextRegBlock OPTIONAL\r
ed66e1bc	115	);\r
ead42efc	116	\r
94b9d5c6	117	/** \r
94b9d5c6	118	Macro that reads command register.\r
ead42efc	119	\r
94b9d5c6	120	@param a[in] Pointer to instance of PCI_IO_DEVICE.\r
	121	@param b[out] Pointer to the 16-bit value read from command register.\r
	122	\r
	123	@return status of PciIo operation\r
	124	\r
	125	**/\r
	126	#define PCI_READ_COMMAND_REGISTER(a,b) \\r
	127	PciOperateRegister (a, 0, PCI_COMMAND_OFFSET, EFI_GET_REGISTER, b)\r
	128	\r
	129	/** \r
	130	Macro that writes command register.\r
	131	\r
	132	@param a[in] Pointer to instance of PCI_IO_DEVICE.\r
	133	@param b[in] The 16-bit value written into command register.\r
	134	\r
	135	@return status of PciIo operation\r
	136	\r
	137	**/\r
	138	#define PCI_SET_COMMAND_REGISTER(a,b) \\r
	139	PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_SET_REGISTER, NULL)\r
	140	\r
	141	/** \r
	142	Macro that enables command register.\r
	143	\r
	144	@param a[in] Pointer to instance of PCI_IO_DEVICE.\r
	145	@param b[in] The enabled value written into command register.\r
	146	\r
	147	@return status of PciIo operation\r
	148	\r
	149	**/ \r
	150	#define PCI_ENABLE_COMMAND_REGISTER(a,b) \\r
	151	PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_ENABLE_REGISTER, NULL)\r
	152	\r
	153	/** \r
	154	Macro that disalbes command register.\r
	155	\r
	156	@param a[in] Pointer to instance of PCI_IO_DEVICE.\r
	157	@param b[in] The disabled value written into command register.\r
	158	\r
	159	@return status of PciIo operation\r
	160	\r
	161	**/ \r
	162	#define PCI_DISABLE_COMMAND_REGISTER(a,b) \\r
	163	PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_DISABLE_REGISTER, NULL)\r
	164	\r
	165	/** \r
	166	Macro that reads PCI bridge control register.\r
	167	\r
	168	@param a[in] Pointer to instance of PCI_IO_DEVICE.\r
	169	@param b[out] The 16-bit value read from control register.\r
	170	\r
	171	@return status of PciIo operation\r
	172	\r
	173	**/\r
	174	#define PCI_READ_BRIDGE_CONTROL_REGISTER(a,b) \\r
	175	PciOperateRegister (a, 0, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_GET_REGISTER, b)\r
	176	\r
	177	/** \r
	178	Macro that writes PCI bridge control register.\r
	179	\r
	180	@param a[in] Pointer to instance of PCI_IO_DEVICE.\r
	181	@param b[in] The 16-bit value written into control register.\r
	182	\r
	183	@return status of PciIo operation\r
184	\r
185	**/ \r
186	#define PCI_SET_BRIDGE_CONTROL_REGISTER(a,b) \\r
187	PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_SET_REGISTER, NULL)\r
188	\r
189	/** \r
190	Macro that enables PCI bridge control register.\r
191	\r
192	@param a[in] Pointer to instance of PCI_IO_DEVICE.\r
193	@param b[in] The enabled value written into command register.\r
194	\r
195	@return status of PciIo operation\r
196	\r
197	**/\r
198	#define PCI_ENABLE_BRIDGE_CONTROL_REGISTER(a,b) \\r
199	PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_ENABLE_REGISTER, NULL)\r
200	\r
201	/** \r
202	Macro that disalbes PCI bridge control register.\r
203	\r
204	@param a[in] Pointer to instance of PCI_IO_DEVICE.\r
205	@param b[in] The disabled value written into command register.\r
206	\r
207	@return status of PciIo operation\r
208	\r
209	**/ \r
210	#define PCI_DISABLE_BRIDGE_CONTROL_REGISTER(a,b) \\r
211	PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_DISABLE_REGISTER, NULL)\r
ead42efc	212	\r
ead42efc	213	#endif\r