IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciCommand.h

   1 /** @file
   2
   3 Copyright (c) 2006 - 2009, Intel Corporation
   4 All rights reserved. This program and the accompanying materials
   5 are licensed and made available under the terms and conditions of the BSD License
   6 which accompanies this distribution.  The full text of the license may be found at
   7 http://opensource.org/licenses/bsd-license.php
   8
   9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11
  12 **/
  13
  14
  15 #ifndef _EFI_PCI_COMMAND_H_
  16 #define _EFI_PCI_COMMAND_H_
  17
  18 //
  19 // The PCI Command register bits owned by PCI Bus driver.
  20 //
  21 // They should be cleared at the beginning. The other registers
  22 // are owned by chipset, we should not touch them.
  23 //
  24 #define EFI_PCI_COMMAND_BITS_OWNED                          ( \
  25                 EFI_PCI_COMMAND_IO_SPACE                    | \
  26                 EFI_PCI_COMMAND_MEMORY_SPACE                | \
  27                 EFI_PCI_COMMAND_BUS_MASTER                  | \
  28                 EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE | \
  29                 EFI_PCI_COMMAND_VGA_PALETTE_SNOOP           | \
  30                 EFI_PCI_COMMAND_FAST_BACK_TO_BACK             \
  31                 )
  32
  33 //
  34 // The PCI Bridge Control register bits owned by PCI Bus driver.
  35 //
  36 // They should be cleared at the beginning. The other registers
  37 // are owned by chipset, we should not touch them.
  38 //
  39 #define EFI_PCI_BRIDGE_CONTROL_BITS_OWNED                   ( \
  40                 EFI_PCI_BRIDGE_CONTROL_ISA                  | \
  41                 EFI_PCI_BRIDGE_CONTROL_VGA                  | \
  42                 EFI_PCI_BRIDGE_CONTROL_VGA_16               | \
  43                 EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK      \
  44                 )
  45
  46 //
  47 // The PCCard Bridge Control register bits owned by PCI Bus driver.
  48 //
  49 // They should be cleared at the beginning. The other registers
  50 // are owned by chipset, we should not touch them.
  51 //
  52 #define EFI_PCCARD_BRIDGE_CONTROL_BITS_OWNED                ( \
  53                 EFI_PCI_BRIDGE_CONTROL_ISA                  | \
  54                 EFI_PCI_BRIDGE_CONTROL_VGA                  | \
  55                 EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK      \
  56                 )
  57
  58
  59 #define EFI_GET_REGISTER      1
  60 #define EFI_SET_REGISTER      2
  61 #define EFI_ENABLE_REGISTER   3
  62 #define EFI_DISABLE_REGISTER  4
  63
  64 /**
  65   Operate the PCI register via PciIo function interface.
  66
  67   @param PciIoDevice    Pointer to instance of PCI_IO_DEVICE
  68   @param Command        Operator command
  69   @param Offset         The address within the PCI configuration space for the PCI controller.
  70   @param Operation      Type of Operation
  71   @param PtrCommand     Return buffer holding old PCI command, if operation is not EFI_SET_REGISTER
  72
  73   @return status of PciIo operation
  74 **/
  75 EFI_STATUS
  76 PciOperateRegister (
  77   IN  PCI_IO_DEVICE *PciIoDevice,
  78   IN  UINT16        Command,
  79   IN  UINT8         Offset,
  80   IN  UINT8         Operation,
  81   OUT UINT16        *PtrCommand
  82   );
  83
  84 /**
  85   check the cpability of this device supports
  86
  87   @param PciIoDevice  Pointer to instance of PCI_IO_DEVICE
  88
  89   @retval TRUE  Support
  90   @retval FALSE Not support.
  91 **/
  92 BOOLEAN
  93 PciCapabilitySupport (
  94   IN PCI_IO_DEVICE  *PciIoDevice
  95   );
  96
  97 /**
  98   Locate cap reg.
  99
 100   @param PciIoDevice         - A pointer to the PCI_IO_DEVICE.
 101   @param CapId               - The cap ID.
 102   @param Offset              - A pointer to the offset.
 103   @param NextRegBlock        - A pointer to the next block.
 104
 105   @retval EFI_UNSUPPORTED  Pci device does not support
 106   @retval EFI_NOT_FOUND    Pci device support but can not find register block.
 107   @retval EFI_SUCCESS      Success to locate capability register block
 108 **/
 109 EFI_STATUS
 110 LocateCapabilityRegBlock (
 111   IN PCI_IO_DEVICE  *PciIoDevice,
 112   IN UINT8          CapId,
 113   IN OUT UINT8      *Offset,
 114   OUT UINT8         *NextRegBlock OPTIONAL
 115   );
 116
 117 /**
 118   Macro that reads command register.
 119
 120   @param a[in]            Pointer to instance of PCI_IO_DEVICE.
 121   @param b[out]           Pointer to the 16-bit value read from command register.
 122
 123   @return status of PciIo operation
 124
 125 **/
 126 #define PCI_READ_COMMAND_REGISTER(a,b) \
 127         PciOperateRegister (a, 0, PCI_COMMAND_OFFSET, EFI_GET_REGISTER, b)
 128
 129 /**
 130   Macro that writes command register.
 131
 132   @param a[in]            Pointer to instance of PCI_IO_DEVICE.
 133   @param b[in]            The 16-bit value written into command register.
 134
 135   @return status of PciIo operation
 136
 137 **/
 138 #define PCI_SET_COMMAND_REGISTER(a,b) \
 139         PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_SET_REGISTER, NULL)
 140
 141 /**
 142   Macro that enables command register.
 143
 144   @param a[in]            Pointer to instance of PCI_IO_DEVICE.
 145   @param b[in]            The enabled value written into command register.
 146
 147   @return status of PciIo operation
 148
 149 **/
 150 #define PCI_ENABLE_COMMAND_REGISTER(a,b) \
 151         PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_ENABLE_REGISTER, NULL)
 152
 153 /**
 154   Macro that disalbes command register.
 155
 156   @param a[in]            Pointer to instance of PCI_IO_DEVICE.
 157   @param b[in]            The disabled value written into command register.
 158
 159   @return status of PciIo operation
 160
 161 **/
 162 #define PCI_DISABLE_COMMAND_REGISTER(a,b) \
 163         PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_DISABLE_REGISTER, NULL)
 164
 165 /**
 166   Macro that reads PCI bridge control register.
 167
 168   @param a[in]            Pointer to instance of PCI_IO_DEVICE.
 169   @param b[out]           The 16-bit value read from control register.
 170
 171   @return status of PciIo operation
 172
 173 **/
 174 #define PCI_READ_BRIDGE_CONTROL_REGISTER(a,b) \
 175         PciOperateRegister (a, 0, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_GET_REGISTER, b)
 176
 177 /**
 178   Macro that writes PCI bridge control register.
 179
 180   @param a[in]            Pointer to instance of PCI_IO_DEVICE.
 181   @param b[in]            The 16-bit value written into control register.
 182
 183   @return status of PciIo operation
 184
 185 **/
 186 #define PCI_SET_BRIDGE_CONTROL_REGISTER(a,b) \
 187         PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_SET_REGISTER, NULL)
 188
 189 /**
 190   Macro that enables PCI bridge control register.
 191
 192   @param a[in]            Pointer to instance of PCI_IO_DEVICE.
 193   @param b[in]            The enabled value written into command register.
 194
 195   @return status of PciIo operation
 196
 197 **/
 198 #define PCI_ENABLE_BRIDGE_CONTROL_REGISTER(a,b) \
 199         PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_ENABLE_REGISTER, NULL)
 200
 201 /**
 202  Macro that disalbes PCI bridge control register.
 203
 204   @param a[in]            Pointer to instance of PCI_IO_DEVICE.
 205   @param b[in]            The disabled value written into command register.
 206
 207   @return status of PciIo operation
 208
 209 **/
 210 #define PCI_DISABLE_BRIDGE_CONTROL_REGISTER(a,b) \
 211         PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_DISABLE_REGISTER, NULL)
 212
 213 #endif