[mirror_edk2.git] / IntelFrameworkModulePkg / Bus / Pci / PciBusDxe / PciEnumerator.c

/** @file\r
  PCI eunmeration implementation on entire PCI bus system for PCI Bus module.\r
\r
Copyright (c) 2006 - 2009, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#include "PciBus.h"\r
\r
/**\r
  This routine is used to enumerate entire pci bus system\r
  in a given platform.\r
\r
  @param Controller  Parent controller handle.\r
\r
  @retval EFI_SUCCESS    PCI enumeration finished successfully.\r
  @retval other          Some error occurred when enumerating the pci bus system.\r
\r
**/\r
EFI_STATUS\r
PciEnumerator (\r
  IN EFI_HANDLE                    Controller\r
  )\r
{\r
\r
  EFI_HANDLE                                        HostBridgeHandle;\r
  EFI_STATUS                                        Status;\r
  EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL  *PciResAlloc;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL                   *PciRootBridgeIo;\r
\r
  //\r
  // If PCI bus has already done the full enumeration, never do it again\r
  //\r
  if (!gFullEnumeration) {\r
    return PciEnumeratorLight (Controller);\r
  }\r
\r
  //\r
  // Get the rootbridge Io protocol to find the host bridge handle\r
  //\r
  Status = gBS->OpenProtocol (\r
                  Controller,\r
                  &gEfiPciRootBridgeIoProtocolGuid,\r
                  (VOID **) &PciRootBridgeIo,\r
                  gPciBusDriverBinding.DriverBindingHandle,\r
                  Controller,\r
                  EFI_OPEN_PROTOCOL_GET_PROTOCOL\r
                  );\r
\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  //\r
  // Get the host bridge handle\r
  //\r
  HostBridgeHandle = PciRootBridgeIo->ParentHandle;\r
\r
  //\r
  // Get the pci host bridge resource allocation protocol\r
  //\r
  Status = gBS->OpenProtocol (\r
                  HostBridgeHandle,\r
                  &gEfiPciHostBridgeResourceAllocationProtocolGuid,\r
                  (VOID **) &PciResAlloc,\r
                  gPciBusDriverBinding.DriverBindingHandle,\r
                  Controller,\r
                  EFI_OPEN_PROTOCOL_GET_PROTOCOL\r
                  );\r
\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  //\r
  // Notify the pci bus enumeration is about to begin\r
  //\r
  NotifyPhase (PciResAlloc, EfiPciHostBridgeBeginEnumeration);\r
\r
  //\r
  // Start the bus allocation phase\r
  //\r
  Status = PciHostBridgeEnumerator (PciResAlloc);\r
\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  //\r
  // Submit the resource request\r
  //\r
  Status = PciHostBridgeResourceAllocator (PciResAlloc);\r
\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  //\r
  // Process P2C\r
  //\r
  Status = PciHostBridgeP2CProcess (PciResAlloc);\r
\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  //\r
  // Process attributes for devices on this host bridge\r
  //\r
  Status = PciHostBridgeDeviceAttribute (PciResAlloc);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  gFullEnumeration = FALSE;\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Enumerate PCI root bridge.\r
\r
  @param PciResAlloc   Pointer to protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r
  @param RootBridgeDev Instance of root bridge device.\r
\r
  @retval EFI_SUCCESS  Successfully enumerated root bridge.\r
  @retval other        Failed to enumerate root bridge.\r
\r
**/\r
EFI_STATUS\r
PciRootBridgeEnumerator (\r
  IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL  *PciResAlloc,\r
  IN PCI_IO_DEVICE                                     *RootBridgeDev\r
  )\r
{\r
  EFI_STATUS                        Status;\r
  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration;\r
  UINT8                             SubBusNumber;\r
  UINT8                             StartBusNumber;\r
  UINT8                             PaddedBusRange;\r
  EFI_HANDLE                        RootBridgeHandle;\r
\r
  SubBusNumber    = 0;\r
  StartBusNumber  = 0;\r
  PaddedBusRange  = 0;\r
\r
  //\r
  // Get the root bridge handle\r
  //\r
  RootBridgeHandle = RootBridgeDev->Handle;\r
\r
  REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
    EFI_PROGRESS_CODE,\r
    EFI_IO_BUS_PCI | EFI_IOB_PCI_PC_BUS_ENUM,\r
    RootBridgeDev->DevicePath\r
    );\r
\r
  //\r
  // Get the Bus information\r
  //\r
  Status = PciResAlloc->StartBusEnumeration (\r
                          PciResAlloc,\r
                          RootBridgeHandle,\r
                          (VOID **) &Configuration\r
                          );\r
\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  //\r
  // Get the bus number to start with\r
  //\r
  StartBusNumber = (UINT8) (Configuration->AddrRangeMin);\r
  PaddedBusRange  = (UINT8) (Configuration->AddrRangeMax);\r
\r
  //\r
  // Initialize the subordinate bus number\r
  //\r
  SubBusNumber = StartBusNumber;\r
\r
  //\r
  // Reset all assigned PCI bus number\r
  //\r
  ResetAllPpbBusNumber (\r
    RootBridgeDev,\r
    StartBusNumber\r
  );\r
\r
  //\r
  // Assign bus number\r
  //\r
  Status = PciScanBus (\r
            RootBridgeDev,\r
            (UINT8) (Configuration->AddrRangeMin),\r
            &SubBusNumber,\r
            &PaddedBusRange\r
            );\r
\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
\r
  //\r
  // Assign max bus number scanned\r
  //\r
  Configuration->AddrLen = SubBusNumber - StartBusNumber + 1 + PaddedBusRange;\r
\r
  //\r
  // Set bus number\r
  //\r
  Status = PciResAlloc->SetBusNumbers (\r
                          PciResAlloc,\r
                          RootBridgeHandle,\r
                          Configuration\r
                          );\r
\r
  FreePool (Configuration);\r
\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  This routine is used to process all PCI devices' Option Rom\r
  on a certain root bridge.\r
\r
  @param Bridge     Given parent's root bridge.\r
  @param RomBase    Base address of ROM driver loaded from.\r
  @param MaxLength  Maximum rom size.\r
\r
**/\r
VOID\r
ProcessOptionRom (\r
  IN PCI_IO_DEVICE *Bridge,\r
  IN UINT64        RomBase,\r
  IN UINT64        MaxLength\r
  )\r
{\r
  LIST_ENTRY      *CurrentLink;\r
  PCI_IO_DEVICE   *Temp;\r
\r
  //\r
  // Go through bridges to reach all devices\r
  //\r
  CurrentLink = Bridge->ChildList.ForwardLink;\r
  while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {\r
    Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);\r
    if (!IsListEmpty (&Temp->ChildList)) {\r
\r
      //\r
      // Go further to process the option rom under this bridge\r
      //\r
      ProcessOptionRom (Temp, RomBase, MaxLength);\r
    }\r
\r
    if (Temp->RomSize != 0 && Temp->RomSize <= MaxLength) {\r
\r
      //\r
      // Load and process the option rom\r
      //\r
      LoadOpRomImage (Temp, RomBase);\r
    }\r
\r
    CurrentLink = CurrentLink->ForwardLink;\r
  }\r
}\r
\r
/**\r
  This routine is used to assign bus number to the given PCI bus system\r
\r
  @param Bridge             Parent root bridge instance.\r
  @param StartBusNumber     Number of beginning.\r
  @param SubBusNumber       The number of sub bus.\r
\r
  @retval EFI_SUCCESS       Successfully assigned bus number.\r
  @retval EFI_DEVICE_ERROR  Failed to assign bus number.\r
\r
**/\r
EFI_STATUS\r
PciAssignBusNumber (\r
  IN PCI_IO_DEVICE                      *Bridge,\r
  IN UINT8                              StartBusNumber,\r
  OUT UINT8                             *SubBusNumber\r
  )\r
{\r
  EFI_STATUS                      Status;\r
  PCI_TYPE00                      Pci;\r
  UINT8                           Device;\r
  UINT8                           Func;\r
  UINT64                          Address;\r
  UINTN                           SecondBus;\r
  UINT16                          Register;\r
  UINT8                           Register8;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
\r
  PciRootBridgeIo = Bridge->PciRootBridgeIo;\r
\r
  SecondBus       = 0;\r
  Register        = 0;\r
\r
  *SubBusNumber = StartBusNumber;\r
\r
  //\r
  // First check to see whether the parent is ppb\r
  //\r
  for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {\r
    for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {\r
\r
      //\r
      // Check to see whether a pci device is present\r
      //\r
      Status = PciDevicePresent (\r
                PciRootBridgeIo,\r
                &Pci,\r
                StartBusNumber,\r
                Device,\r
                Func\r
                );\r
\r
      if (!EFI_ERROR (Status)   &&\r
          (IS_PCI_BRIDGE (&Pci) || IS_CARDBUS_BRIDGE (&Pci))) {\r
\r
        //\r
        // Reserved one bus for cardbus bridge\r
        //\r
        SecondBus = ++(*SubBusNumber);\r
\r
        Register  = (UINT16) ((SecondBus << 8) | (UINT16) StartBusNumber);\r
\r
        Address   = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x18);\r
\r
        Status = PciRootBridgeIo->Pci.Write (\r
                                        PciRootBridgeIo,\r
                                        EfiPciWidthUint16,\r
                                        Address,\r
                                        1,\r
                                        &Register\r
                                        );\r
\r
        //\r
        // Initialize SubBusNumber to SecondBus\r
        //\r
        Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);\r
        Status = PciRootBridgeIo->Pci.Write (\r
                                        PciRootBridgeIo,\r
                                        EfiPciWidthUint8,\r
                                        Address,\r
                                        1,\r
                                        SubBusNumber\r
                                        );\r
        //\r
        // If it is PPB, resursively search down this bridge\r
        //\r
        if (IS_PCI_BRIDGE (&Pci)) {\r
\r
          Register8 = 0xFF;\r
          Status = PciRootBridgeIo->Pci.Write (\r
                                          PciRootBridgeIo,\r
                                          EfiPciWidthUint8,\r
                                          Address,\r
                                          1,\r
                                          &Register8\r
                                          );\r
\r
          Status = PciAssignBusNumber (\r
                    Bridge,\r
                    (UINT8) (SecondBus),\r
                    SubBusNumber\r
                    );\r
\r
          if (EFI_ERROR (Status)) {\r
            return EFI_DEVICE_ERROR;\r
          }\r
        }\r
\r
        //\r
        // Set the current maximum bus number under the PPB\r
        //\r
        Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);\r
\r
        Status = PciRootBridgeIo->Pci.Write (\r
                                        PciRootBridgeIo,\r
                                        EfiPciWidthUint8,\r
                                        Address,\r
                                        1,\r
                                        SubBusNumber\r
                                        );\r
\r
      }\r
\r
      if (Func == 0 && !IS_PCI_MULTI_FUNC (&Pci)) {\r
\r
        //\r
        // Skip sub functions, this is not a multi function device\r
        //\r
        Func = PCI_MAX_FUNC;\r
      }\r
    }\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  This routine is used to determine the root bridge attribute by interfacing\r
  the host bridge resource allocation protocol.\r
\r
  @param PciResAlloc    Protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
  @param RootBridgeDev  Root bridge instance\r
\r
  @retval EFI_SUCCESS  Successfully got root bridge's attribute.\r
  @retval other        Failed to get attribute.\r
\r
**/\r
EFI_STATUS\r
DetermineRootBridgeAttributes (\r
  IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc,\r
  IN PCI_IO_DEVICE                                    *RootBridgeDev\r
  )\r
{\r
  UINT64      Attributes;\r
  EFI_STATUS  Status;\r
  EFI_HANDLE  RootBridgeHandle;\r
\r
  Attributes        = 0;\r
  RootBridgeHandle  = RootBridgeDev->Handle;\r
\r
  //\r
  // Get root bridge attribute by calling into pci host bridge resource allocation protocol\r
  //\r
  Status = PciResAlloc->GetAllocAttributes (\r
                          PciResAlloc,\r
                          RootBridgeHandle,\r
                          &Attributes\r
                          );\r
\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  //\r
  // Here is the point where PCI bus driver calls HOST bridge allocation protocol\r
  // Currently we hardcoded for ea815\r
  //\r
  if ((Attributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) != 0) {\r
    RootBridgeDev->Decodes |= EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED;\r
  }\r
\r
  if ((Attributes & EFI_PCI_HOST_BRIDGE_MEM64_DECODE) != 0) {\r
    RootBridgeDev->Decodes |= EFI_BRIDGE_PMEM64_DECODE_SUPPORTED;\r
  }\r
\r
  RootBridgeDev->Decodes |= EFI_BRIDGE_MEM32_DECODE_SUPPORTED;\r
  RootBridgeDev->Decodes |= EFI_BRIDGE_PMEM32_DECODE_SUPPORTED;\r
  RootBridgeDev->Decodes |= EFI_BRIDGE_IO16_DECODE_SUPPORTED;\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Get Max Option Rom size on specified bridge.\r
\r
  @param Bridge    Given bridge device instance.\r
\r
  @return Max size of option rom needed.\r
\r
**/\r
UINT64\r
GetMaxOptionRomSize (\r
  IN PCI_IO_DEVICE   *Bridge\r
  )\r
{\r
  LIST_ENTRY      *CurrentLink;\r
  PCI_IO_DEVICE   *Temp;\r
  UINT64          MaxOptionRomSize;\r
  UINT64          TempOptionRomSize;\r
\r
  MaxOptionRomSize = 0;\r
\r
  //\r
  // Go through bridges to reach all devices\r
  //\r
  CurrentLink = Bridge->ChildList.ForwardLink;\r
  while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {\r
    Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);\r
    if (!IsListEmpty (&Temp->ChildList)) {\r
\r
      //\r
      // Get max option rom size under this bridge\r
      //\r
      TempOptionRomSize = GetMaxOptionRomSize (Temp);\r
\r
      //\r
      // Compare with the option rom size of the bridge\r
      // Get the larger one\r
      //\r
      if (Temp->RomSize > TempOptionRomSize) {\r
        TempOptionRomSize = Temp->RomSize;\r
      }\r
\r
    } else {\r
\r
      //\r
      // For devices get the rom size directly\r
      //\r
      TempOptionRomSize = Temp->RomSize;\r
    }\r
\r
    //\r
    // Get the largest rom size on this bridge\r
    //\r
    if (TempOptionRomSize > MaxOptionRomSize) {\r
      MaxOptionRomSize = TempOptionRomSize;\r
    }\r
\r
    CurrentLink = CurrentLink->ForwardLink;\r
  }\r
\r
  return MaxOptionRomSize;\r
}\r
\r
/**\r
  Process attributes of devices on this host bridge\r
\r
  @param PciResAlloc Protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r
\r
  @retval EFI_SUCCESS   Successfully process attribute.\r
  @retval EFI_NOT_FOUND Can not find the specific root bridge device.\r
  @retval other         Failed to determine the root bridge device's attribute.\r
\r
**/\r
EFI_STATUS\r
PciHostBridgeDeviceAttribute (\r
  IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc\r
  )\r
{\r
  EFI_HANDLE    RootBridgeHandle;\r
  PCI_IO_DEVICE *RootBridgeDev;\r
  EFI_STATUS    Status;\r
\r
  RootBridgeHandle = NULL;\r
\r
  while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {\r
\r
    //\r
    // Get RootBridg Device by handle\r
    //\r
    RootBridgeDev = GetRootBridgeByHandle (RootBridgeHandle);\r
\r
    if (RootBridgeDev == NULL) {\r
      return EFI_NOT_FOUND;\r
    }\r
\r
    //\r
    // Set the attributes for devcies behind the Root Bridge\r
    //\r
    Status = DetermineDeviceAttribute (RootBridgeDev);\r
    if (EFI_ERROR (Status)) {\r
      return Status;\r
    }\r
\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Get resource allocation status from the ACPI resource descriptor.\r
\r
  @param AcpiConfig       Point to Acpi configuration table.\r
  @param IoResStatus      Return the status of I/O resource.\r
  @param Mem32ResStatus   Return the status of 32-bit Memory resource.\r
  @param PMem32ResStatus  Return the status of 32-bit Prefetchable Memory resource.\r
  @param Mem64ResStatus   Return the status of 64-bit Memory resource.\r
  @param PMem64ResStatus  Return the status of 64-bit Prefetchable Memory resource.\r
\r
**/\r
VOID\r
GetResourceAllocationStatus (\r
  VOID        *AcpiConfig,\r
  OUT UINT64  *IoResStatus,\r
  OUT UINT64  *Mem32ResStatus,\r
  OUT UINT64  *PMem32ResStatus,\r
  OUT UINT64  *Mem64ResStatus,\r
  OUT UINT64  *PMem64ResStatus\r
  )\r
{\r
  UINT8                             *Temp;\r
  UINT64                            ResStatus;\r
  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ACPIAddressDesc;\r
\r
  Temp = (UINT8 *) AcpiConfig;\r
\r
  while (*Temp == ACPI_ADDRESS_SPACE_DESCRIPTOR) {\r
\r
    ACPIAddressDesc       = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp;\r
    ResStatus = ACPIAddressDesc->AddrTranslationOffset;\r
\r
    switch (ACPIAddressDesc->ResType) {\r
    case 0:\r
      if (ACPIAddressDesc->AddrSpaceGranularity == 32) {\r
        if (ACPIAddressDesc->SpecificFlag == 0x06) {\r
          //\r
          // Pmem32\r
          //\r
          *PMem32ResStatus = ResStatus;\r
        } else {\r
          //\r
          // Mem32\r
          //\r
          *Mem32ResStatus = ResStatus;\r
        }\r
      }\r
\r
      if (ACPIAddressDesc->AddrSpaceGranularity == 64) {\r
        if (ACPIAddressDesc->SpecificFlag == 0x06) {\r
          //\r
          // PMem64\r
          //\r
          *PMem64ResStatus = ResStatus;\r
        } else {\r
          //\r
          // Mem64\r
          //\r
          *Mem64ResStatus = ResStatus;\r
        }\r
      }\r
\r
      break;\r
\r
    case 1:\r
      //\r
      // Io\r
      //\r
      *IoResStatus = ResStatus;\r
      break;\r
\r
    default:\r
      break;\r
    }\r
\r
    Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);\r
  }\r
}\r
\r
/**\r
  Remove a PCI device from device pool and mark its bar.\r
\r
  @param PciDevice Instance of Pci device.\r
\r
  @retval EFI_SUCCESS Successfully remove the PCI device.\r
  @retval EFI_ABORTED Pci device is a root bridge or a PCI-PCI bridge.\r
\r
**/\r
EFI_STATUS\r
RejectPciDevice (\r
  IN PCI_IO_DEVICE       *PciDevice\r
  )\r
{\r
  PCI_IO_DEVICE   *Bridge;\r
  PCI_IO_DEVICE   *Temp;\r
  LIST_ENTRY      *CurrentLink;\r
\r
  //\r
  // Remove the padding resource from a bridge\r
  //\r
  if ( IS_PCI_BRIDGE(&PciDevice->Pci) &&\r
       PciDevice->ResourcePaddingDescriptors != NULL ) {\r
    FreePool (PciDevice->ResourcePaddingDescriptors);\r
    PciDevice->ResourcePaddingDescriptors = NULL;\r
    return EFI_SUCCESS;\r
  }\r
\r
  //\r
  // Skip RB and PPB\r
  //\r
  if (IS_PCI_BRIDGE (&PciDevice->Pci) || (PciDevice->Parent == NULL)) {\r
    return EFI_ABORTED;\r
  }\r
\r
  if (IS_CARDBUS_BRIDGE (&PciDevice->Pci)) {\r
    //\r
    // Get the root bridge device\r
    //\r
    Bridge = PciDevice;\r
    while (Bridge->Parent != NULL) {\r
      Bridge = Bridge->Parent;\r
    }\r
\r
    RemoveAllPciDeviceOnBridge (Bridge->Handle, PciDevice);\r
\r
    //\r
    // Mark its bar\r
    //\r
    InitializeP2C (PciDevice);\r
  }\r
\r
  //\r
  // Remove the device\r
  //\r
  Bridge      = PciDevice->Parent;\r
  CurrentLink = Bridge->ChildList.ForwardLink;\r
  while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {\r
    Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);\r
    if (Temp == PciDevice) {\r
      InitializePciDevice (Temp);\r
      RemoveEntryList (CurrentLink);\r
      FreePciDevice (Temp);\r
      return EFI_SUCCESS;\r
    }\r
\r
    CurrentLink = CurrentLink->ForwardLink;\r
  }\r
\r
  return EFI_ABORTED;\r
}\r
\r
/**\r
  Determine whethter a PCI device can be rejected.\r
\r
  @param  PciResNode Pointer to Pci resource node instance.\r
\r
  @retval TRUE  The PCI device can be rejected.\r
  @retval TRUE  The PCI device cannot be rejected.\r
\r
**/\r
BOOLEAN\r
IsRejectiveDevice (\r
  IN  PCI_RESOURCE_NODE   *PciResNode\r
  )\r
{\r
  PCI_IO_DEVICE *Temp;\r
\r
  Temp = PciResNode->PciDev;\r
\r
  //\r
  // Ensure the device is present\r
  //\r
  if (Temp == NULL) {\r
    return FALSE;\r
  }\r
\r
  //\r
  // PPB and RB should go ahead\r
  //\r
  if (IS_PCI_BRIDGE (&Temp->Pci) || (Temp->Parent == NULL)) {\r
    return TRUE;\r
  }\r
\r
  //\r
  // Skip device on Bus0\r
  //\r
  if ((Temp->Parent != NULL) && (Temp->BusNumber == 0)) {\r
    return FALSE;\r
  }\r
\r
  //\r
  // Skip VGA\r
  //\r
  if (IS_PCI_VGA (&Temp->Pci)) {\r
    return FALSE;\r
  }\r
\r
  return TRUE;\r
}\r
\r
/**\r
  Compare two resource nodes and get the larger resource consumer.\r
\r
  @param PciResNode1  resource node 1 want to be compared\r
  @param PciResNode2  resource node 2 want to be compared\r
\r
  @return Larger resource node.\r
\r
**/\r
PCI_RESOURCE_NODE *\r
GetLargerConsumerDevice (\r
  IN  PCI_RESOURCE_NODE   *PciResNode1,\r
  IN  PCI_RESOURCE_NODE   *PciResNode2\r
  )\r
{\r
  if (PciResNode2 == NULL) {\r
    return PciResNode1;\r
  }\r
\r
  if ((IS_PCI_BRIDGE(&(PciResNode2->PciDev->Pci)) || (PciResNode2->PciDev->Parent == NULL)) \\r
       && (PciResNode2->ResourceUsage != PciResUsagePadding) )\r
  {\r
    return PciResNode1;\r
  }\r
\r
  if (PciResNode1 == NULL) {\r
    return PciResNode2;\r
  }\r
\r
  if ((PciResNode1->Length) > (PciResNode2->Length)) {\r
    return PciResNode1;\r
  }\r
\r
  return PciResNode2;\r
}\r
\r
\r
/**\r
  Get the max resource consumer in the host resource pool.\r
\r
  @param ResPool  Pointer to resource pool node.\r
\r
  @return The max resource consumer in the host resource pool.\r
\r
**/\r
PCI_RESOURCE_NODE *\r
GetMaxResourceConsumerDevice (\r
  IN  PCI_RESOURCE_NODE   *ResPool\r
  )\r
{\r
  PCI_RESOURCE_NODE *Temp;\r
  LIST_ENTRY        *CurrentLink;\r
  PCI_RESOURCE_NODE *PciResNode;\r
  PCI_RESOURCE_NODE *PPBResNode;\r
\r
  PciResNode  = NULL;\r
\r
  CurrentLink = ResPool->ChildList.ForwardLink;\r
  while (CurrentLink != NULL && CurrentLink != &ResPool->ChildList) {\r
\r
    Temp = RESOURCE_NODE_FROM_LINK (CurrentLink);\r
\r
    if (!IsRejectiveDevice (Temp)) {\r
      CurrentLink = CurrentLink->ForwardLink;\r
      continue;\r
    }\r
\r
    if ((IS_PCI_BRIDGE (&(Temp->PciDev->Pci)) || (Temp->PciDev->Parent == NULL)) \\r
          && (Temp->ResourceUsage != PciResUsagePadding))\r
    {\r
      PPBResNode  = GetMaxResourceConsumerDevice (Temp);\r
      PciResNode  = GetLargerConsumerDevice (PciResNode, PPBResNode);\r
    } else {\r
      PciResNode = GetLargerConsumerDevice (PciResNode, Temp);\r
    }\r
\r
    CurrentLink = CurrentLink->ForwardLink;\r
  }\r
\r
  return PciResNode;\r
}\r
\r
/**\r
  Adjust host bridge allocation so as to reduce resource requirement\r
\r
  @param IoPool           Pointer to instance of I/O resource Node.\r
  @param Mem32Pool        Pointer to instance of 32-bit memory resource Node.\r
  @param PMem32Pool       Pointer to instance of 32-bit Prefetchable memory resource node.\r
  @param Mem64Pool        Pointer to instance of 64-bit memory resource node.\r
  @param PMem64Pool       Pointer to instance of 64-bit Prefetchable memory resource node.\r
  @param IoResStatus      Status of I/O resource Node.\r
  @param Mem32ResStatus   Status of 32-bit memory resource Node.\r
  @param PMem32ResStatus  Status of 32-bit Prefetchable memory resource node.\r
  @param Mem64ResStatus   Status of 64-bit memory resource node.\r
  @param PMem64ResStatus  Status of 64-bit Prefetchable memory resource node.\r
\r
  @retval EFI_SUCCESS     Successfully adjusted resoruce on host bridge.\r
  @retval EFI_ABORTED     Host bridge hasn't this resource type or no resource be adjusted.\r
\r
**/\r
EFI_STATUS\r
PciHostBridgeAdjustAllocation (\r
  IN  PCI_RESOURCE_NODE   *IoPool,\r
  IN  PCI_RESOURCE_NODE   *Mem32Pool,\r
  IN  PCI_RESOURCE_NODE   *PMem32Pool,\r
  IN  PCI_RESOURCE_NODE   *Mem64Pool,\r
  IN  PCI_RESOURCE_NODE   *PMem64Pool,\r
  IN  UINT64              IoResStatus,\r
  IN  UINT64              Mem32ResStatus,\r
  IN  UINT64              PMem32ResStatus,\r
  IN  UINT64              Mem64ResStatus,\r
  IN  UINT64              PMem64ResStatus\r
  )\r
{\r
  BOOLEAN                               AllocationAjusted;\r
  PCI_RESOURCE_NODE                     *PciResNode;\r
  PCI_RESOURCE_NODE                     *ResPool[5];\r
  PCI_IO_DEVICE                         *RemovedPciDev[5];\r
  UINT64                                ResStatus[5];\r
  UINTN                                 RemovedPciDevNum;\r
  UINTN                                 DevIndex;\r
  UINTN                                 ResType;\r
  EFI_STATUS                            Status;\r
  EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA_PAYLOAD AllocFailExtendedData;\r
\r
  PciResNode = NULL;\r
  ZeroMem (RemovedPciDev, 5 * sizeof (PCI_IO_DEVICE *));\r
  RemovedPciDevNum  = 0;\r
\r
  ResPool[0]        = IoPool;\r
  ResPool[1]        = Mem32Pool;\r
  ResPool[2]        = PMem32Pool;\r
  ResPool[3]        = Mem64Pool;\r
  ResPool[4]        = PMem64Pool;\r
\r
  ResStatus[0]      = IoResStatus;\r
  ResStatus[1]      = Mem32ResStatus;\r
  ResStatus[2]      = PMem32ResStatus;\r
  ResStatus[3]      = Mem64ResStatus;\r
  ResStatus[4]      = PMem64ResStatus;\r
\r
  AllocationAjusted = FALSE;\r
\r
  for (ResType = 0; ResType < 5; ResType++) {\r
\r
    if (ResStatus[ResType] == EFI_RESOURCE_SATISFIED) {\r
      continue;\r
    }\r
\r
    if (ResStatus[ResType] == EFI_RESOURCE_NOT_SATISFIED) {\r
      //\r
      // Host bridge hasn't this resource type\r
      //\r
      return EFI_ABORTED;\r
    }\r
\r
    //\r
    // Hostbridge hasn't enough resource\r
    //\r
    PciResNode = GetMaxResourceConsumerDevice (ResPool[ResType]);\r
    if (PciResNode == NULL) {\r
      continue;\r
    }\r
\r
    //\r
    // Check if the device has been removed before\r
    //\r
    for (DevIndex = 0; DevIndex < RemovedPciDevNum; DevIndex++) {\r
      if (PciResNode->PciDev == RemovedPciDev[DevIndex]) {\r
        break;\r
      }\r
    }\r
\r
    if (DevIndex != RemovedPciDevNum) {\r
      continue;\r
    }\r
\r
    //\r
    // Remove the device if it isn't in the array\r
    //\r
    Status = RejectPciDevice (PciResNode->PciDev);\r
    if (Status == EFI_SUCCESS) {\r
\r
      //\r
      // Raise the EFI_IOB_EC_RESOURCE_CONFLICT status code\r
      //\r
      //\r
      // Have no way to get ReqRes, AllocRes & Bar here\r
      //\r
      ZeroMem (&AllocFailExtendedData, sizeof (AllocFailExtendedData));\r
      AllocFailExtendedData.DevicePathSize = sizeof (EFI_DEVICE_PATH_PROTOCOL);\r
      AllocFailExtendedData.DevicePath     = (UINT8 *) PciResNode->PciDev->DevicePath;\r
      AllocFailExtendedData.Bar            = PciResNode->Bar;\r
\r
      REPORT_STATUS_CODE_WITH_EXTENDED_DATA (\r
            EFI_PROGRESS_CODE,\r
            EFI_IO_BUS_PCI | EFI_IOB_EC_RESOURCE_CONFLICT,\r
            (VOID *) &AllocFailExtendedData,\r
            sizeof (AllocFailExtendedData)\r
            );\r
\r
      //\r
      // Add it to the array and indicate at least a device has been rejected\r
      //\r
      RemovedPciDev[RemovedPciDevNum++] = PciResNode->PciDev;\r
      AllocationAjusted                 = TRUE;\r
    }\r
  }\r
  //\r
  // End for\r
  //\r
\r
  if (AllocationAjusted) {\r
    return EFI_SUCCESS;\r
  } else {\r
    return EFI_ABORTED;\r
  }\r
}\r
\r
/**\r
  Summary requests for all resource type, and contruct ACPI resource\r
  requestor instance.\r
\r
  @param Bridge           detecting bridge\r
  @param IoNode           Pointer to instance of I/O resource Node\r
  @param Mem32Node        Pointer to instance of 32-bit memory resource Node\r
  @param PMem32Node       Pointer to instance of 32-bit Pmemory resource node\r
  @param Mem64Node        Pointer to instance of 64-bit memory resource node\r
  @param PMem64Node       Pointer to instance of 64-bit Pmemory resource node\r
  @param Config           Output buffer holding new constructed APCI resource requestor\r
\r
  @retval EFI_SUCCESS           Successfully constructed ACPI resource.\r
  @retval EFI_OUT_OF_RESOURCES  No memory availabe.\r
\r
**/\r
EFI_STATUS\r
ConstructAcpiResourceRequestor (\r
  IN PCI_IO_DEVICE      *Bridge,\r
  IN PCI_RESOURCE_NODE  *IoNode,\r
  IN PCI_RESOURCE_NODE  *Mem32Node,\r
  IN PCI_RESOURCE_NODE  *PMem32Node,\r
  IN PCI_RESOURCE_NODE  *Mem64Node,\r
  IN PCI_RESOURCE_NODE  *PMem64Node,\r
  OUT VOID              **Config\r
  )\r
{\r
  UINT8                             NumConfig;\r
  UINT8                             Aperture;\r
  UINT8                             *Configuration;\r
  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;\r
  EFI_ACPI_END_TAG_DESCRIPTOR       *PtrEnd;\r
\r
  NumConfig = 0;\r
  Aperture  = 0;\r
\r
  *Config  = NULL;\r
\r
  //\r
  // if there is io request, add to the io aperture\r
  //\r
  if (ResourceRequestExisted (IoNode)) {\r
    NumConfig++;\r
    Aperture |= 0x01;\r
  }\r
\r
  //\r
  // if there is mem32 request, add to the mem32 aperture\r
  //\r
  if (ResourceRequestExisted (Mem32Node)) {\r
    NumConfig++;\r
    Aperture |= 0x02;\r
  }\r
\r
  //\r
  // if there is pmem32 request, add to the pmem32 aperture\r
  //\r
  if (ResourceRequestExisted (PMem32Node)) {\r
    NumConfig++;\r
    Aperture |= 0x04;\r
  }\r
\r
  //\r
  // if there is mem64 request, add to the mem64 aperture\r
  //\r
  if (ResourceRequestExisted (Mem64Node)) {\r
    NumConfig++;\r
    Aperture |= 0x08;\r
  }\r
\r
  //\r
  // if there is pmem64 request, add to the pmem64 aperture\r
  //\r
  if (ResourceRequestExisted (PMem64Node)) {\r
    NumConfig++;\r
    Aperture |= 0x10;\r
  }\r
\r
  if (NumConfig != 0) {\r
\r
    //\r
    // If there is at least one type of resource request,\r
    // allocate a acpi resource node\r
    //\r
    Configuration = AllocateZeroPool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));\r
    if (Configuration == NULL) {\r
      return EFI_OUT_OF_RESOURCES;\r
    }\r
\r
    Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;\r
\r
    //\r
    // Deal with io aperture\r
    //\r
    if ((Aperture & 0x01) != 0) {\r
      Ptr->Desc     = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
      Ptr->Len      = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;\r
      //\r
      // Io\r
      //\r
      Ptr->ResType  = ACPI_ADDRESS_SPACE_TYPE_IO;\r
      //\r
      // non ISA range\r
      //\r
      Ptr->SpecificFlag = 1;\r
      Ptr->AddrLen      = IoNode->Length;\r
      Ptr->AddrRangeMax = IoNode->Alignment;\r
\r
      Ptr++;\r
    }\r
    //\r
    // Deal with mem32 aperture\r
    //\r
    if ((Aperture & 0x02) != 0) {\r
      Ptr->Desc     = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
      Ptr->Len      = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;\r
      //\r
      // Mem\r
      //\r
      Ptr->ResType  = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
      //\r
      // Nonprefechable\r
      //\r
      Ptr->SpecificFlag = 0;\r
      //\r
      // 32 bit\r
      //\r
      Ptr->AddrSpaceGranularity = 32;\r
      Ptr->AddrLen      = Mem32Node->Length;\r
      Ptr->AddrRangeMax = Mem32Node->Alignment;\r
\r
      Ptr++;\r
    }\r
\r
    //\r
    // Deal with Pmem32 aperture\r
    //\r
    if ((Aperture & 0x04) != 0) {\r
      Ptr->Desc     = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
      Ptr->Len      = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;\r
      //\r
      // Mem\r
      //\r
      Ptr->ResType  = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
      //\r
      // prefechable\r
      //\r
      Ptr->SpecificFlag = 0x6;\r
      //\r
      // 32 bit\r
      //\r
      Ptr->AddrSpaceGranularity = 32;\r
      Ptr->AddrLen      = PMem32Node->Length;\r
      Ptr->AddrRangeMax = PMem32Node->Alignment;\r
\r
      Ptr++;\r
    }\r
    //\r
    // Deal with mem64 aperture\r
    //\r
    if ((Aperture & 0x08) != 0) {\r
      Ptr->Desc     = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
      Ptr->Len      = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;\r
      //\r
      // Mem\r
      //\r
      Ptr->ResType  = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
      //\r
      // nonprefechable\r
      //\r
      Ptr->SpecificFlag = 0;\r
      //\r
      // 64 bit\r
      //\r
      Ptr->AddrSpaceGranularity = 64;\r
      Ptr->AddrLen      = Mem64Node->Length;\r
      Ptr->AddrRangeMax = Mem64Node->Alignment;\r
\r
      Ptr++;\r
    }\r
    //\r
    // Deal with Pmem64 aperture\r
    //\r
    if ((Aperture & 0x10) != 0) {\r
      Ptr->Desc     = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
      Ptr->Len      = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;\r
      //\r
      // Mem\r
      //\r
      Ptr->ResType  = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
      //\r
      // prefechable\r
      //\r
      Ptr->SpecificFlag = 0x06;\r
      //\r
      // 64 bit\r
      //\r
      Ptr->AddrSpaceGranularity = 64;\r
      Ptr->AddrLen      = PMem64Node->Length;\r
      Ptr->AddrRangeMax = PMem64Node->Alignment;\r
\r
      Ptr++;\r
    }\r
\r
    //\r
    // put the checksum\r
    //\r
    PtrEnd            = (EFI_ACPI_END_TAG_DESCRIPTOR *) Ptr;\r
\r
    PtrEnd->Desc      = ACPI_END_TAG_DESCRIPTOR;\r
    PtrEnd->Checksum  = 0;\r
\r
  } else {\r
\r
    //\r
    // If there is no resource request\r
    //\r
    Configuration = AllocateZeroPool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));\r
    if (Configuration == NULL) {\r
      return EFI_OUT_OF_RESOURCES;\r
    }\r
\r
    Ptr               = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) (Configuration);\r
    Ptr->Desc         = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
\r
    PtrEnd            = (EFI_ACPI_END_TAG_DESCRIPTOR *) (Ptr + 1);\r
    PtrEnd->Desc      = ACPI_END_TAG_DESCRIPTOR;\r
    PtrEnd->Checksum  = 0;\r
  }\r
\r
  *Config = Configuration;\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Get resource base from an acpi configuration descriptor.\r
\r
  @param Config       An acpi configuration descriptor.\r
  @param IoBase       Output of I/O resource base address.\r
  @param Mem32Base    Output of 32-bit memory base address.\r
  @param PMem32Base   Output of 32-bit prefetchable memory base address.\r
  @param Mem64Base    Output of 64-bit memory base address.\r
  @param PMem64Base   Output of 64-bit prefetchable memory base address.\r
\r
**/\r
VOID\r
GetResourceBase (\r
  IN VOID     *Config,\r
  OUT UINT64  *IoBase,\r
  OUT UINT64  *Mem32Base,\r
  OUT UINT64  *PMem32Base,\r
  OUT UINT64  *Mem64Base,\r
  OUT UINT64  *PMem64Base\r
  )\r
{\r
  UINT8                             *Temp;\r
  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;\r
  UINT64                            ResStatus;\r
\r
  ASSERT (Config != NULL);\r
\r
  *IoBase     = 0xFFFFFFFFFFFFFFFFULL;\r
  *Mem32Base  = 0xFFFFFFFFFFFFFFFFULL;\r
  *PMem32Base = 0xFFFFFFFFFFFFFFFFULL;\r
  *Mem64Base  = 0xFFFFFFFFFFFFFFFFULL;\r
  *PMem64Base = 0xFFFFFFFFFFFFFFFFULL;\r
\r
  Temp        = (UINT8 *) Config;\r
\r
  while (*Temp == ACPI_ADDRESS_SPACE_DESCRIPTOR) {\r
\r
    Ptr       = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp;\r
    ResStatus = Ptr->AddrTranslationOffset;\r
\r
    if (ResStatus == EFI_RESOURCE_SATISFIED) {\r
\r
      switch (Ptr->ResType) {\r
\r
      //\r
      // Memory type aperture\r
      //\r
      case 0:\r
\r
        //\r
        // Check to see the granularity\r
        //\r
        if (Ptr->AddrSpaceGranularity == 32) {\r
          if ((Ptr->SpecificFlag & 0x06) != 0) {\r
            *PMem32Base = Ptr->AddrRangeMin;\r
          } else {\r
            *Mem32Base = Ptr->AddrRangeMin;\r
          }\r
        }\r
\r
        if (Ptr->AddrSpaceGranularity == 64) {\r
          if ((Ptr->SpecificFlag & 0x06) != 0) {\r
            *PMem64Base = Ptr->AddrRangeMin;\r
          } else {\r
            *Mem64Base = Ptr->AddrRangeMin;\r
          }\r
        }\r
        break;\r
\r
      case 1:\r
\r
        //\r
        // Io type aperture\r
        //\r
        *IoBase = Ptr->AddrRangeMin;\r
        break;\r
\r
      default:\r
        break;\r
\r
      }\r
      //\r
      // End switch\r
      //\r
    }\r
    //\r
    // End for\r
    //\r
    Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);\r
  }\r
}\r
\r
/**\r
  Enumerate pci bridge, allocate resource and determine attribute\r
  for devices on this bridge.\r
\r
  @param BridgeDev    Pointer to instance of bridge device.\r
\r
  @retval EFI_SUCCESS Successfully enumerated PCI bridge.\r
  @retval other       Failed to enumerate.\r
\r
**/\r
EFI_STATUS\r
PciBridgeEnumerator (\r
  IN PCI_IO_DEVICE                                     *BridgeDev\r
  )\r
{\r
  UINT8               SubBusNumber;\r
  UINT8               StartBusNumber;\r
  EFI_PCI_IO_PROTOCOL *PciIo;\r
  EFI_STATUS          Status;\r
\r
  SubBusNumber    = 0;\r
  StartBusNumber  = 0;\r
  PciIo           = &(BridgeDev->PciIo);\r
  Status          = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x19, 1, &StartBusNumber);\r
\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  Status = PciAssignBusNumber (\r
            BridgeDev,\r
            StartBusNumber,\r
            &SubBusNumber\r
            );\r
\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  Status = PciPciDeviceInfoCollector (BridgeDev, StartBusNumber);\r
\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  Status = PciBridgeResourceAllocator (BridgeDev);\r
\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  Status = DetermineDeviceAttribute (BridgeDev);\r
\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  return EFI_SUCCESS;\r
\r
}\r
\r
/**\r
  Allocate all kinds of resource for PCI bridge.\r
\r
  @param  Bridge      Pointer to bridge instance.\r
\r
  @retval EFI_SUCCESS Successfully allocated resource for PCI bridge.\r
  @retval other       Failed to allocate resource for bridge.\r
\r
**/\r
EFI_STATUS\r
PciBridgeResourceAllocator (\r
  IN PCI_IO_DEVICE  *Bridge\r
  )\r
{\r
  PCI_RESOURCE_NODE *IoBridge;\r
  PCI_RESOURCE_NODE *Mem32Bridge;\r
  PCI_RESOURCE_NODE *PMem32Bridge;\r
  PCI_RESOURCE_NODE *Mem64Bridge;\r
  PCI_RESOURCE_NODE *PMem64Bridge;\r
  UINT64            IoBase;\r
  UINT64            Mem32Base;\r
  UINT64            PMem32Base;\r
  UINT64            Mem64Base;\r
  UINT64            PMem64Base;\r
  EFI_STATUS        Status;\r
\r
  IoBridge = CreateResourceNode (\r
               Bridge,\r
               0,\r
               0xFFF,\r
               0,\r
               PciBarTypeIo16,\r
               PciResUsageTypical\r
               );\r
\r
  Mem32Bridge = CreateResourceNode (\r
                  Bridge,\r
                  0,\r
                  0xFFFFF,\r
                  0,\r
                  PciBarTypeMem32,\r
                  PciResUsageTypical\r
                  );\r
\r
  PMem32Bridge = CreateResourceNode (\r
                   Bridge,\r
                   0,\r
                   0xFFFFF,\r
                   0,\r
                   PciBarTypePMem32,\r
                   PciResUsageTypical\r
                   );\r
\r
  Mem64Bridge = CreateResourceNode (\r
                  Bridge,\r
                  0,\r
                  0xFFFFF,\r
                  0,\r
                  PciBarTypeMem64,\r
                  PciResUsageTypical\r
                  );\r
\r
  PMem64Bridge = CreateResourceNode (\r
                   Bridge,\r
                   0,\r
                   0xFFFFF,\r
                   0,\r
                   PciBarTypePMem64,\r
                   PciResUsageTypical\r
                   );\r
\r
  //\r
  // Create resourcemap by going through all the devices subject to this root bridge\r
  //\r
  CreateResourceMap (\r
    Bridge,\r
    IoBridge,\r
    Mem32Bridge,\r
    PMem32Bridge,\r
    Mem64Bridge,\r
    PMem64Bridge\r
    );\r
\r
  Status = GetResourceBaseFromBridge (\r
             Bridge,\r
             &IoBase,\r
             &Mem32Base,\r
             &PMem32Base,\r
             &Mem64Base,\r
             &PMem64Base\r
             );\r
\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  //\r
  // Program IO resources\r
  //\r
  ProgramResource (\r
    IoBase,\r
    IoBridge\r
    );\r
\r
  //\r
  // Program Mem32 resources\r
  //\r
  ProgramResource (\r
    Mem32Base,\r
    Mem32Bridge\r
    );\r
\r
  //\r
  // Program PMem32 resources\r
  //\r
  ProgramResource (\r
    PMem32Base,\r
    PMem32Bridge\r
    );\r
\r
  //\r
  // Program Mem64 resources\r
  //\r
  ProgramResource (\r
    Mem64Base,\r
    Mem64Bridge\r
    );\r
\r
  //\r
  // Program PMem64 resources\r
  //\r
  ProgramResource (\r
    PMem64Base,\r
    PMem64Bridge\r
    );\r
\r
  DestroyResourceTree (IoBridge);\r
  DestroyResourceTree (Mem32Bridge);\r
  DestroyResourceTree (PMem32Bridge);\r
  DestroyResourceTree (PMem64Bridge);\r
  DestroyResourceTree (Mem64Bridge);\r
\r
  gBS->FreePool (IoBridge);\r
  gBS->FreePool (Mem32Bridge);\r
  gBS->FreePool (PMem32Bridge);\r
  gBS->FreePool (PMem64Bridge);\r
  gBS->FreePool (Mem64Bridge);\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Get resource base address for a pci bridge device.\r
\r
  @param Bridge     Given Pci driver instance.\r
  @param IoBase     Output for base address of I/O type resource.\r
  @param Mem32Base  Output for base address of 32-bit memory type resource.\r
  @param PMem32Base Ooutput for base address of 32-bit Pmemory type resource.\r
  @param Mem64Base  Output for base address of 64-bit memory type resource.\r
  @param PMem64Base Output for base address of 64-bit Pmemory type resource.\r
\r
  @retval EFI_SUCCESS           Successfully got resource base address.\r
  @retval EFI_OUT_OF_RESOURCES  PCI bridge is not available.\r
\r
**/\r
EFI_STATUS\r
GetResourceBaseFromBridge (\r
  IN  PCI_IO_DEVICE *Bridge,\r
  OUT UINT64        *IoBase,\r
  OUT UINT64        *Mem32Base,\r
  OUT UINT64        *PMem32Base,\r
  OUT UINT64        *Mem64Base,\r
  OUT UINT64        *PMem64Base\r
  )\r
{\r
  if (!Bridge->Allocated) {\r
    return EFI_OUT_OF_RESOURCES;\r
  }\r
\r
  *IoBase     = gAllOne;\r
  *Mem32Base  = gAllOne;\r
  *PMem32Base = gAllOne;\r
  *Mem64Base  = gAllOne;\r
  *PMem64Base = gAllOne;\r
\r
  if (IS_PCI_BRIDGE (&Bridge->Pci)) {\r
\r
    if (Bridge->PciBar[PPB_IO_RANGE].Length > 0) {\r
      *IoBase = Bridge->PciBar[PPB_IO_RANGE].BaseAddress;\r
    }\r
\r
    if (Bridge->PciBar[PPB_MEM32_RANGE].Length > 0) {\r
      *Mem32Base = Bridge->PciBar[PPB_MEM32_RANGE].BaseAddress;\r
    }\r
\r
    if (Bridge->PciBar[PPB_PMEM32_RANGE].Length > 0) {\r
      *PMem32Base = Bridge->PciBar[PPB_PMEM32_RANGE].BaseAddress;\r
    }\r
\r
    if (Bridge->PciBar[PPB_PMEM64_RANGE].Length > 0) {\r
      *PMem64Base = Bridge->PciBar[PPB_PMEM64_RANGE].BaseAddress;\r
    } else {\r
      *PMem64Base = gAllOne;\r
    }\r
\r
  }\r
\r
  if (IS_CARDBUS_BRIDGE (&Bridge->Pci)) {\r
    if (Bridge->PciBar[P2C_IO_1].Length > 0) {\r
      *IoBase = Bridge->PciBar[P2C_IO_1].BaseAddress;\r
    } else {\r
      if (Bridge->PciBar[P2C_IO_2].Length > 0) {\r
        *IoBase = Bridge->PciBar[P2C_IO_2].BaseAddress;\r
      }\r
    }\r
\r
    if (Bridge->PciBar[P2C_MEM_1].Length > 0) {\r
      if (Bridge->PciBar[P2C_MEM_1].BarType == PciBarTypePMem32) {\r
        *PMem32Base = Bridge->PciBar[P2C_MEM_1].BaseAddress;\r
      }\r
\r
      if (Bridge->PciBar[P2C_MEM_1].BarType == PciBarTypeMem32) {\r
        *Mem32Base = Bridge->PciBar[P2C_MEM_1].BaseAddress;\r
      }\r
    }\r
\r
    if (Bridge->PciBar[P2C_MEM_2].Length > 0) {\r
      if (Bridge->PciBar[P2C_MEM_2].BarType == PciBarTypePMem32) {\r
        *PMem32Base = Bridge->PciBar[P2C_MEM_2].BaseAddress;\r
      }\r
\r
      if (Bridge->PciBar[P2C_MEM_2].BarType == PciBarTypeMem32) {\r
        *Mem32Base = Bridge->PciBar[P2C_MEM_2].BaseAddress;\r
      }\r
    }\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
   These are the notifications from the PCI bus driver that it is about to enter a certain\r
   phase of the PCI enumeration process.\r
\r
   This member function can be used to notify the host bridge driver to perform specific actions,\r
   including any chipset-specific initialization, so that the chipset is ready to enter the next phase.\r
   Eight notification points are defined at this time. See belows:\r
   EfiPciHostBridgeBeginEnumeration       Resets the host bridge PCI apertures and internal data\r
                                          structures. The PCI enumerator should issue this notification\r
                                          before starting a fresh enumeration process. Enumeration cannot\r
                                          be restarted after sending any other notification such as\r
                                          EfiPciHostBridgeBeginBusAllocation.\r
   EfiPciHostBridgeBeginBusAllocation     The bus allocation phase is about to begin. No specific action is\r
                                          required here. This notification can be used to perform any\r
                                          chipset-specific programming.\r
   EfiPciHostBridgeEndBusAllocation       The bus allocation and bus programming phase is complete. No\r
                                          specific action is required here. This notification can be used to\r
                                          perform any chipset-specific programming.\r
   EfiPciHostBridgeBeginResourceAllocation\r
                                          The resource allocation phase is about to begin. No specific\r
                                          action is required here. This notification can be used to perform\r
                                          any chipset-specific programming.\r
   EfiPciHostBridgeAllocateResources      Allocates resources per previously submitted requests for all the PCI\r
                                          root bridges. These resource settings are returned on the next call to\r
                                          GetProposedResources(). Before calling NotifyPhase() with a Phase of\r
                                          EfiPciHostBridgeAllocateResource, the PCI bus enumerator is responsible\r
                                          for gathering I/O and memory requests for\r
                                          all the PCI root bridges and submitting these requests using\r
                                          SubmitResources(). This function pads the resource amount\r
                                          to suit the root bridge hardware, takes care of dependencies between\r
                                          the PCI root bridges, and calls the Global Coherency Domain (GCD)\r
                                          with the allocation request. In the case of padding, the allocated range\r
                                          could be bigger than what was requested.\r
   EfiPciHostBridgeSetResources           Programs the host bridge hardware to decode previously allocated\r
                                          resources (proposed resources) for all the PCI root bridges. After the\r
                                          hardware is programmed, reassigning resources will not be supported.\r
                                          The bus settings are not affected.\r
   EfiPciHostBridgeFreeResources          Deallocates resources that were previously allocated for all the PCI\r
                                          root bridges and resets the I/O and memory apertures to their initial\r
                                          state. The bus settings are not affected. If the request to allocate\r
                                          resources fails, the PCI enumerator can use this notification to\r
                                          deallocate previous resources, adjust the requests, and retry\r
                                          allocation.\r
   EfiPciHostBridgeEndResourceAllocation  The resource allocation phase is completed. No specific action is\r
                                          required here. This notification can be used to perform any chipsetspecific\r
                                          programming.\r
\r
   @param[in] PciResAlloc         The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
   @param[in] Phase               The phase during enumeration\r
\r
   @retval EFI_NOT_READY          This phase cannot be entered at this time. For example, this error\r
                                  is valid for a Phase of EfiPciHostBridgeAllocateResources if\r
                                  SubmitResources() has not been called for one or more\r
                                  PCI root bridges before this call\r
   @retval EFI_DEVICE_ERROR       Programming failed due to a hardware error. This error is valid\r
                                  for a Phase of EfiPciHostBridgeSetResources.\r
   @retval EFI_INVALID_PARAMETER  Invalid phase parameter\r
   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a lack of resources.\r
                                  This error is valid for a Phase of EfiPciHostBridgeAllocateResources if the\r
                                  previously submitted resource requests cannot be fulfilled or\r
                                  were only partially fulfilled.\r
   @retval EFI_SUCCESS            The notification was accepted without any errors.\r
\r
**/\r
EFI_STATUS\r
NotifyPhase (\r
  IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc,\r
  EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE       Phase\r
  )\r
{\r
  EFI_HANDLE                      HostBridgeHandle;\r
  EFI_HANDLE                      RootBridgeHandle;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
  EFI_STATUS                      Status;\r
\r
  HostBridgeHandle  = NULL;\r
  RootBridgeHandle  = NULL;\r
  if (gPciPlatformProtocol != NULL) {\r
    //\r
    // Get Host Bridge Handle.\r
    //\r
    PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle);\r
\r
    //\r
    // Get the rootbridge Io protocol to find the host bridge handle\r
    //\r
    Status = gBS->HandleProtocol (\r
                    RootBridgeHandle,\r
                    &gEfiPciRootBridgeIoProtocolGuid,\r
                    (VOID **) &PciRootBridgeIo\r
                    );\r
\r
    if (EFI_ERROR (Status)) {\r
      return EFI_NOT_FOUND;\r
    }\r
\r
    HostBridgeHandle = PciRootBridgeIo->ParentHandle;\r
\r
    //\r
    // Call PlatformPci::PlatformNotify() if the protocol is present.\r
    //\r
    gPciPlatformProtocol->PlatformNotify (\r
                            gPciPlatformProtocol,\r
                            HostBridgeHandle,\r
                            Phase,\r
                            ChipsetEntry\r
                            );\r
  }\r
\r
  Status = PciResAlloc->NotifyPhase (\r
                          PciResAlloc,\r
                          Phase\r
                          );\r
\r
  if (gPciPlatformProtocol != NULL) {\r
    //\r
    // Call PlatformPci::PlatformNotify() if the protocol is present.\r
    //\r
    gPciPlatformProtocol->PlatformNotify (\r
                            gPciPlatformProtocol,\r
                            HostBridgeHandle,\r
                            Phase,\r
                            ChipsetExit\r
                            );\r
\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various\r
  stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual\r
  PCI controllers before enumeration.\r
\r
  This function is called during the PCI enumeration process. No specific action is expected from this\r
  member function. It allows the host bridge driver to preinitialize individual PCI controllers before\r
  enumeration.\r
\r
  @param Bridge            Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.\r
  @param Bus               The bus number of the pci device.\r
  @param Device            The device number of the pci device.\r
  @param Func              The function number of the pci device.\r
  @param Phase             The phase of the PCI device enumeration.\r
\r
  @retval EFI_SUCCESS              The requested parameters were returned.\r
  @retval EFI_INVALID_PARAMETER    RootBridgeHandle is not a valid root bridge handle.\r
  @retval EFI_INVALID_PARAMETER    Phase is not a valid phase that is defined in\r
                                   EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.\r
  @retval EFI_DEVICE_ERROR         Programming failed due to a hardware error. The PCI enumerator should\r
                                   not enumerate this device, including its child devices if it is a PCI-to-PCI\r
                                   bridge.\r
\r
**/\r
EFI_STATUS\r
PreprocessController (\r
  IN PCI_IO_DEVICE                                    *Bridge,\r
  IN UINT8                                            Bus,\r
  IN UINT8                                            Device,\r
  IN UINT8                                            Func,\r
  IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE     Phase\r
  )\r
{\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS       RootBridgePciAddress;\r
  EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL  *PciResAlloc;\r
  EFI_HANDLE                                        RootBridgeHandle;\r
  EFI_HANDLE                                        HostBridgeHandle;\r
  EFI_STATUS                                        Status;\r
\r
  //\r
  // Get the host bridge handle\r
  //\r
  HostBridgeHandle = Bridge->PciRootBridgeIo->ParentHandle;\r
\r
  //\r
  // Get the pci host bridge resource allocation protocol\r
  //\r
  Status = gBS->OpenProtocol (\r
                  HostBridgeHandle,\r
                  &gEfiPciHostBridgeResourceAllocationProtocolGuid,\r
                  (VOID **) &PciResAlloc,\r
                  NULL,\r
                  NULL,\r
                  EFI_OPEN_PROTOCOL_GET_PROTOCOL\r
                  );\r
\r
  if (EFI_ERROR (Status)) {\r
    return EFI_UNSUPPORTED;\r
  }\r
\r
  //\r
  // Get Root Brige Handle\r
  //\r
  while (Bridge->Parent != NULL) {\r
    Bridge = Bridge->Parent;\r
  }\r
\r
  RootBridgeHandle                      = Bridge->Handle;\r
\r
  RootBridgePciAddress.Register         = 0;\r
  RootBridgePciAddress.Function         = Func;\r
  RootBridgePciAddress.Device           = Device;\r
  RootBridgePciAddress.Bus              = Bus;\r
  RootBridgePciAddress.ExtendedRegister = 0;\r
\r
  if (gPciPlatformProtocol != NULL) {\r
    //\r
    // Call PlatformPci::PrepController() if the protocol is present.\r
    //\r
    gPciPlatformProtocol->PlatformPrepController (\r
                            gPciPlatformProtocol,\r
                            HostBridgeHandle,\r
                            RootBridgeHandle,\r
                            RootBridgePciAddress,\r
                            Phase,\r
                            ChipsetEntry\r
                            );\r
  }\r
\r
  Status = PciResAlloc->PreprocessController (\r
                          PciResAlloc,\r
                          RootBridgeHandle,\r
                          RootBridgePciAddress,\r
                          Phase\r
                          );\r
\r
  if (gPciPlatformProtocol != NULL) {\r
    //\r
    // Call PlatformPci::PrepController() if the protocol is present.\r
    //\r
    gPciPlatformProtocol->PlatformPrepController (\r
                            gPciPlatformProtocol,\r
                            HostBridgeHandle,\r
                            RootBridgeHandle,\r
                            RootBridgePciAddress,\r
                            Phase,\r
                            ChipsetExit\r
                            );\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  This function allows the PCI bus driver to be notified to act as requested when a hot-plug event has\r
  happened on the hot-plug controller. Currently, the operations include add operation and remove operation..\r
\r
  @param This                 A pointer to the hot plug request protocol.\r
  @param Operation            The operation the PCI bus driver is requested to make.\r
  @param Controller           The handle of the hot-plug controller.\r
  @param RemainingDevicePath  The remaining device path for the PCI-like hot-plug device.\r
  @param NumberOfChildren     The number of child handles.\r
                              For a add operation, it is an output parameter.\r