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caf45c98 1/** @file\r
5259c97d 2 This file declares the PciCfg PPI used to access the PCI configuration space in PEI\r
caf45c98 3\r
1c2f052d 4Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
22a69a5e 5SPDX-License-Identifier: BSD-2-Clause-Patent\r
caf45c98 6\r
caf45c98 7 @par Revision Reference:\r
8 This PPI is defined in PEI CIS\r
9 Version 0.91.\r
10\r
11**/\r
12\r
13#ifndef __PEI_PCI_CFG_H__\r
14#define __PEI_PCI_CFG_H__\r
15\r
0e0eeeca 16#include <Ppi/PciCfg2.h>\r
24980534 17//\r
18// Get the common definitions for EFI_PEI_PCI_CFG_PPI_WIDTH.\r
19//\r
7459094d 20\r
caf45c98 21#define EFI_PEI_PCI_CFG_PPI_INSTALLED_GUID \\r
22 { \\r
23 0xe1f2eba0, 0xf7b9, 0x4a26, {0x86, 0x20, 0x13, 0x12, 0x21, 0x64, 0x2a, 0x90 } \\r
24 }\r
25\r
26typedef struct _EFI_PEI_PCI_CFG_PPI EFI_PEI_PCI_CFG_PPI;\r
27\r
28#define PEI_PCI_CFG_ADDRESS(bus, dev, func, reg) ( \\r
29 (UINT64) ((((UINTN) bus) << 24) + (((UINTN) dev) << 16) + (((UINTN) func) << 8) + ((UINTN) reg)) \\r
30 ) & 0x00000000ffffffff\r
31\r
32/**\r
33 PCI read and write operation.\r
34\r
35 @param PeiServices An indirect pointer to the PEI Services Table\r
36 published by the PEI Foundation.\r
37 @param This Pointer to local data for the interface.\r
38 @param Width The width of the access. Enumerated in bytes.\r
39 @param Address The physical address of the access.\r
40 @param Buffer A pointer to the buffer of data.\r
41\r
42 @retval EFI_SUCCESS The function completed successfully.\r
43 @retval EFI_NOT_YET_AVAILABLE The service has not been installed.\r
44\r
45**/\r
46typedef\r
47EFI_STATUS\r
69686d56 48(EFIAPI *EFI_PEI_PCI_CFG_PPI_IO)(\r
caf45c98 49 IN EFI_PEI_SERVICES **PeiServices,\r
50 IN EFI_PEI_PCI_CFG_PPI *This,\r
51 IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r
52 IN UINT64 Address,\r
53 IN OUT VOID *Buffer\r
54 );\r
55\r
56/**\r
57 PCI read-modify-write operation.\r
58\r
59 @param PeiServices An indirect pointer to the PEI Services Table\r
60 published by the PEI Foundation.\r
f22f941e 61 @param This The pointer to local data for the interface.\r
caf45c98 62 @param Width The width of the access. Enumerated in bytes.\r
63 @param Address The physical address of the access.\r
64 @param SetBits Value of the bits to set.\r
65 @param ClearBits Value of the bits to clear.\r
66\r
67 @retval EFI_SUCCESS The function completed successfully.\r
68\r
69**/\r
70typedef\r
71EFI_STATUS\r
69686d56 72(EFIAPI *EFI_PEI_PCI_CFG_PPI_RW)(\r
caf45c98 73 IN EFI_PEI_SERVICES **PeiServices,\r
74 IN EFI_PEI_PCI_CFG_PPI *This,\r
75 IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r
76 IN UINT64 Address,\r
77 IN UINTN SetBits,\r
78 IN UINTN ClearBits\r
79 );\r
80\r
81/**\r
1c2f052d 82 The EFI_PEI_PCI_CFG_PPI interfaces are used to abstract accesses to PCI\r
caf45c98 83 controllers behind a PCI root bridge controller.\r
caf45c98 84**/\r
85struct _EFI_PEI_PCI_CFG_PPI {\r
2bbaeb0d 86 ///\r
87 /// PCI read services. See the Read() function description.\r
88 ///\r
caf45c98 89 EFI_PEI_PCI_CFG_PPI_IO Read;\r
1c2f052d 90\r
2bbaeb0d 91 ///\r
92 /// PCI write services. See the Write() function description.\r
93 ///\r
caf45c98 94 EFI_PEI_PCI_CFG_PPI_IO Write;\r
1c2f052d 95\r
2bbaeb0d 96 ///\r
97 /// PCI read-modify-write services. See the Modify() function description.\r
98 ///\r
caf45c98 99 EFI_PEI_PCI_CFG_PPI_RW Modify;\r
100};\r
101\r
102extern EFI_GUID gEfiPciCfgPpiInServiceTableGuid;\r
103\r
104#endif\r